1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sc7280 fragment for devices with Chrome bootloader 4 * 5 * This file mainly tries to abstract out the memory protections put into 6 * place by the Chrome bootloader which are different than what's put into 7 * place by Qualcomm's typical bootloader. It also has a smattering of other 8 * things that will hold true for any conceivable Chrome design 9 * 10 * Copyright 2022 Google LLC. 11 */ 12 13/* 14 * Reserved memory changes 15 * 16 * Delete all unused memory nodes and define the peripheral memory regions 17 * required by the setup for Chrome boards. 18 */ 19 20/delete-node/ &hyp_mem; 21/delete-node/ &xbl_mem; 22/delete-node/ &reserved_xbl_uefi_log; 23/delete-node/ &sec_apps_mem; 24 25/ { 26 reserved-memory { 27 adsp_mem: memory@86700000 { 28 reg = <0x0 0x86700000 0x0 0x2800000>; 29 no-map; 30 }; 31 32 camera_mem: memory@8ad00000 { 33 reg = <0x0 0x8ad00000 0x0 0x500000>; 34 no-map; 35 }; 36 37 venus_mem: memory@8b200000 { 38 reg = <0x0 0x8b200000 0x0 0x500000>; 39 no-map; 40 }; 41 42 wpss_mem: memory@9ae00000 { 43 reg = <0x0 0x9ae00000 0x0 0x1900000>; 44 no-map; 45 }; 46 }; 47}; 48 49/* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */ 50&pmk8350_pon { 51 status = "disabled"; 52}; 53 54/* 55 * Chrome designs always boot from SPI flash hooked up to the qspi. 56 * 57 * It's expected that all boards will support "dual SPI" at 37.5 MHz. 58 * If some boards need a different speed or have a package that allows 59 * Quad SPI together with WP then those boards can easily override. 60 */ 61&qspi { 62 status = "okay"; 63 pinctrl-names = "default"; 64 pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; 65 66 spi_flash: flash@0 { 67 compatible = "jedec,spi-nor"; 68 reg = <0>; 69 70 spi-max-frequency = <37500000>; 71 spi-tx-bus-width = <2>; 72 spi-rx-bus-width = <2>; 73 }; 74}; 75 76&remoteproc_wpss { 77 status = "okay"; 78 firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt"; 79}; 80 81&wifi { 82 status = "okay"; 83 84 wifi-firmware { 85 iommus = <&apps_smmu 0x1c02 0x1>; 86 }; 87}; 88