1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sm6350.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm6350-camcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interconnect/qcom,icc.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sm6350.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <76800000>; 31 clock-output-names = "xo_board"; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 clock-frequency = <32764>; 37 #clock-cells = <0>; 38 }; 39 }; 40 41 cpus { 42 #address-cells = <2>; 43 #size-cells = <0>; 44 45 CPU0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "qcom,kryo560"; 48 reg = <0x0 0x0>; 49 enable-method = "psci"; 50 capacity-dmips-mhz = <1024>; 51 dynamic-power-coefficient = <100>; 52 next-level-cache = <&L2_0>; 53 qcom,freq-domain = <&cpufreq_hw 0>; 54 operating-points-v2 = <&cpu0_opp_table>; 55 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 56 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 57 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 58 #cooling-cells = <2>; 59 L2_0: l2-cache { 60 compatible = "cache"; 61 cache-level = <2>; 62 next-level-cache = <&L3_0>; 63 L3_0: l3-cache { 64 compatible = "cache"; 65 cache-level = <3>; 66 }; 67 }; 68 }; 69 70 CPU1: cpu@100 { 71 device_type = "cpu"; 72 compatible = "qcom,kryo560"; 73 reg = <0x0 0x100>; 74 enable-method = "psci"; 75 capacity-dmips-mhz = <1024>; 76 dynamic-power-coefficient = <100>; 77 next-level-cache = <&L2_100>; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 operating-points-v2 = <&cpu0_opp_table>; 80 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 81 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 82 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 83 #cooling-cells = <2>; 84 L2_100: l2-cache { 85 compatible = "cache"; 86 cache-level = <2>; 87 next-level-cache = <&L3_0>; 88 }; 89 }; 90 91 CPU2: cpu@200 { 92 device_type = "cpu"; 93 compatible = "qcom,kryo560"; 94 reg = <0x0 0x200>; 95 enable-method = "psci"; 96 capacity-dmips-mhz = <1024>; 97 dynamic-power-coefficient = <100>; 98 next-level-cache = <&L2_200>; 99 qcom,freq-domain = <&cpufreq_hw 0>; 100 operating-points-v2 = <&cpu0_opp_table>; 101 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 102 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 103 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 104 #cooling-cells = <2>; 105 L2_200: l2-cache { 106 compatible = "cache"; 107 cache-level = <2>; 108 next-level-cache = <&L3_0>; 109 }; 110 }; 111 112 CPU3: cpu@300 { 113 device_type = "cpu"; 114 compatible = "qcom,kryo560"; 115 reg = <0x0 0x300>; 116 enable-method = "psci"; 117 capacity-dmips-mhz = <1024>; 118 dynamic-power-coefficient = <100>; 119 next-level-cache = <&L2_300>; 120 qcom,freq-domain = <&cpufreq_hw 0>; 121 operating-points-v2 = <&cpu0_opp_table>; 122 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 123 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 124 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 125 #cooling-cells = <2>; 126 L2_300: l2-cache { 127 compatible = "cache"; 128 cache-level = <2>; 129 next-level-cache = <&L3_0>; 130 }; 131 }; 132 133 CPU4: cpu@400 { 134 device_type = "cpu"; 135 compatible = "qcom,kryo560"; 136 reg = <0x0 0x400>; 137 enable-method = "psci"; 138 capacity-dmips-mhz = <1024>; 139 dynamic-power-coefficient = <100>; 140 next-level-cache = <&L2_400>; 141 qcom,freq-domain = <&cpufreq_hw 0>; 142 operating-points-v2 = <&cpu0_opp_table>; 143 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 144 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 145 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 146 #cooling-cells = <2>; 147 L2_400: l2-cache { 148 compatible = "cache"; 149 cache-level = <2>; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU5: cpu@500 { 155 device_type = "cpu"; 156 compatible = "qcom,kryo560"; 157 reg = <0x0 0x500>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <1024>; 160 dynamic-power-coefficient = <100>; 161 next-level-cache = <&L2_500>; 162 qcom,freq-domain = <&cpufreq_hw 0>; 163 operating-points-v2 = <&cpu0_opp_table>; 164 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 165 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 166 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 167 #cooling-cells = <2>; 168 L2_500: l2-cache { 169 compatible = "cache"; 170 cache-level = <2>; 171 next-level-cache = <&L3_0>; 172 }; 173 174 }; 175 176 CPU6: cpu@600 { 177 device_type = "cpu"; 178 compatible = "qcom,kryo560"; 179 reg = <0x0 0x600>; 180 enable-method = "psci"; 181 capacity-dmips-mhz = <1894>; 182 dynamic-power-coefficient = <703>; 183 next-level-cache = <&L2_600>; 184 qcom,freq-domain = <&cpufreq_hw 1>; 185 operating-points-v2 = <&cpu6_opp_table>; 186 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 187 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 188 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 189 #cooling-cells = <2>; 190 L2_600: l2-cache { 191 compatible = "cache"; 192 cache-level = <2>; 193 next-level-cache = <&L3_0>; 194 }; 195 }; 196 197 CPU7: cpu@700 { 198 device_type = "cpu"; 199 compatible = "qcom,kryo560"; 200 reg = <0x0 0x700>; 201 enable-method = "psci"; 202 capacity-dmips-mhz = <1894>; 203 dynamic-power-coefficient = <703>; 204 next-level-cache = <&L2_700>; 205 qcom,freq-domain = <&cpufreq_hw 1>; 206 operating-points-v2 = <&cpu6_opp_table>; 207 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 208 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 209 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 210 #cooling-cells = <2>; 211 L2_700: l2-cache { 212 compatible = "cache"; 213 cache-level = <2>; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 cpu-map { 219 cluster0 { 220 core0 { 221 cpu = <&CPU0>; 222 }; 223 224 core1 { 225 cpu = <&CPU1>; 226 }; 227 228 core2 { 229 cpu = <&CPU2>; 230 }; 231 232 core3 { 233 cpu = <&CPU3>; 234 }; 235 236 core4 { 237 cpu = <&CPU4>; 238 }; 239 240 core5 { 241 cpu = <&CPU5>; 242 }; 243 244 core6 { 245 cpu = <&CPU6>; 246 }; 247 248 core7 { 249 cpu = <&CPU7>; 250 }; 251 }; 252 }; 253 }; 254 255 firmware { 256 scm: scm { 257 compatible = "qcom,scm-sm6350", "qcom,scm"; 258 #reset-cells = <1>; 259 }; 260 }; 261 262 memory@80000000 { 263 device_type = "memory"; 264 /* We expect the bootloader to fill in the size */ 265 reg = <0x0 0x80000000 0x0 0x0>; 266 }; 267 268 cpu0_opp_table: opp-table-cpu0 { 269 compatible = "operating-points-v2"; 270 opp-shared; 271 272 opp-300000000 { 273 opp-hz = /bits/ 64 <300000000>; 274 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ 275 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 276 }; 277 278 opp-576000000 { 279 opp-hz = /bits/ 64 <576000000>; 280 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>; 281 }; 282 283 opp-768000000 { 284 opp-hz = /bits/ 64 <768000000>; 285 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 286 }; 287 288 opp-1017600000 { 289 opp-hz = /bits/ 64 <1017600000>; 290 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 291 }; 292 293 opp-1248000000 { 294 opp-hz = /bits/ 64 <1248000000>; 295 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 296 }; 297 298 opp-1324800000 { 299 opp-hz = /bits/ 64 <1324800000>; 300 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>; 301 }; 302 303 opp-1516800000 { 304 opp-hz = /bits/ 64 <1516800000>; 305 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 306 }; 307 308 opp-1612800000 { 309 opp-hz = /bits/ 64 <1612800000>; 310 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 311 }; 312 313 opp-1708800000 { 314 opp-hz = /bits/ 64 <1708800000>; 315 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 316 }; 317 }; 318 319 cpu6_opp_table: opp-table-cpu6 { 320 compatible = "operating-points-v2"; 321 opp-shared; 322 323 opp-300000000 { 324 opp-hz = /bits/ 64 <300000000>; 325 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 326 }; 327 328 opp-787200000 { 329 opp-hz = /bits/ 64 <787200000>; 330 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 331 }; 332 333 opp-979200000 { 334 opp-hz = /bits/ 64 <979200000>; 335 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>; 336 }; 337 338 opp-1036800000 { 339 opp-hz = /bits/ 64 <1036800000>; 340 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 341 }; 342 343 opp-1248000000 { 344 opp-hz = /bits/ 64 <1248000000>; 345 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 346 }; 347 348 opp-1401600000 { 349 opp-hz = /bits/ 64 <1401600000>; 350 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>; 351 }; 352 353 opp-1555200000 { 354 opp-hz = /bits/ 64 <1555200000>; 355 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 356 }; 357 358 opp-1766400000 { 359 opp-hz = /bits/ 64 <1766400000>; 360 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 361 }; 362 363 opp-1900800000 { 364 opp-hz = /bits/ 64 <1900800000>; 365 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 366 }; 367 368 opp-2073600000 { 369 opp-hz = /bits/ 64 <2073600000>; 370 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 371 }; 372 }; 373 374 pmu { 375 compatible = "arm,armv8-pmuv3"; 376 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 377 }; 378 379 psci { 380 compatible = "arm,psci-1.0"; 381 method = "smc"; 382 }; 383 384 reserved_memory: reserved-memory { 385 #address-cells = <2>; 386 #size-cells = <2>; 387 ranges; 388 389 hyp_mem: memory@80000000 { 390 reg = <0 0x80000000 0 0x600000>; 391 no-map; 392 }; 393 394 xbl_aop_mem: memory@80700000 { 395 reg = <0 0x80700000 0 0x160000>; 396 no-map; 397 }; 398 399 cmd_db: memory@80860000 { 400 compatible = "qcom,cmd-db"; 401 reg = <0 0x80860000 0 0x20000>; 402 no-map; 403 }; 404 405 sec_apps_mem: memory@808ff000 { 406 reg = <0 0x808ff000 0 0x1000>; 407 no-map; 408 }; 409 410 smem_mem: memory@80900000 { 411 reg = <0 0x80900000 0 0x200000>; 412 no-map; 413 }; 414 415 cdsp_sec_mem: memory@80b00000 { 416 reg = <0 0x80b00000 0 0x1e00000>; 417 no-map; 418 }; 419 420 pil_camera_mem: memory@86000000 { 421 reg = <0 0x86000000 0 0x500000>; 422 no-map; 423 }; 424 425 pil_npu_mem: memory@86500000 { 426 reg = <0 0x86500000 0 0x500000>; 427 no-map; 428 }; 429 430 pil_video_mem: memory@86a00000 { 431 reg = <0 0x86a00000 0 0x500000>; 432 no-map; 433 }; 434 435 pil_cdsp_mem: memory@86f00000 { 436 reg = <0 0x86f00000 0 0x1e00000>; 437 no-map; 438 }; 439 440 pil_adsp_mem: memory@88d00000 { 441 reg = <0 0x88d00000 0 0x2800000>; 442 no-map; 443 }; 444 445 wlan_fw_mem: memory@8b500000 { 446 reg = <0 0x8b500000 0 0x200000>; 447 no-map; 448 }; 449 450 pil_ipa_fw_mem: memory@8b700000 { 451 reg = <0 0x8b700000 0 0x10000>; 452 no-map; 453 }; 454 455 pil_ipa_gsi_mem: memory@8b710000 { 456 reg = <0 0x8b710000 0 0x5400>; 457 no-map; 458 }; 459 460 pil_gpu_mem: memory@8b715400 { 461 reg = <0 0x8b715400 0 0x2000>; 462 no-map; 463 }; 464 465 pil_modem_mem: memory@8b800000 { 466 reg = <0 0x8b800000 0 0xf800000>; 467 no-map; 468 }; 469 470 cont_splash_memory: memory@a0000000 { 471 reg = <0 0xa0000000 0 0x2300000>; 472 no-map; 473 }; 474 475 dfps_data_memory: memory@a2300000 { 476 reg = <0 0xa2300000 0 0x100000>; 477 no-map; 478 }; 479 480 removed_region: memory@c0000000 { 481 reg = <0 0xc0000000 0 0x3900000>; 482 no-map; 483 }; 484 485 debug_region: memory@ffb00000 { 486 reg = <0 0xffb00000 0 0xc0000>; 487 no-map; 488 }; 489 490 last_log_region: memory@ffbc0000 { 491 reg = <0 0xffbc0000 0 0x40000>; 492 no-map; 493 }; 494 495 ramoops: ramoops@ffc00000 { 496 compatible = "ramoops"; 497 reg = <0 0xffc00000 0 0x100000>; 498 record-size = <0x1000>; 499 console-size = <0x40000>; 500 msg-size = <0x20000 0x20000>; 501 ecc-size = <16>; 502 no-map; 503 }; 504 505 cmdline_region: memory@ffd00000 { 506 reg = <0 0xffd00000 0 0x1000>; 507 no-map; 508 }; 509 }; 510 511 smem { 512 compatible = "qcom,smem"; 513 memory-region = <&smem_mem>; 514 hwlocks = <&tcsr_mutex 3>; 515 }; 516 517 smp2p-adsp { 518 compatible = "qcom,smp2p"; 519 qcom,smem = <443>, <429>; 520 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 521 IPCC_MPROC_SIGNAL_SMP2P 522 IRQ_TYPE_EDGE_RISING>; 523 mboxes = <&ipcc IPCC_CLIENT_LPASS 524 IPCC_MPROC_SIGNAL_SMP2P>; 525 526 qcom,local-pid = <0>; 527 qcom,remote-pid = <2>; 528 529 smp2p_adsp_out: master-kernel { 530 qcom,entry-name = "master-kernel"; 531 #qcom,smem-state-cells = <1>; 532 }; 533 534 smp2p_adsp_in: slave-kernel { 535 qcom,entry-name = "slave-kernel"; 536 interrupt-controller; 537 #interrupt-cells = <2>; 538 }; 539 }; 540 541 smp2p-cdsp { 542 compatible = "qcom,smp2p"; 543 qcom,smem = <94>, <432>; 544 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 545 IPCC_MPROC_SIGNAL_SMP2P 546 IRQ_TYPE_EDGE_RISING>; 547 mboxes = <&ipcc IPCC_CLIENT_CDSP 548 IPCC_MPROC_SIGNAL_SMP2P>; 549 550 qcom,local-pid = <0>; 551 qcom,remote-pid = <5>; 552 553 smp2p_cdsp_out: master-kernel { 554 qcom,entry-name = "master-kernel"; 555 #qcom,smem-state-cells = <1>; 556 }; 557 558 smp2p_cdsp_in: slave-kernel { 559 qcom,entry-name = "slave-kernel"; 560 interrupt-controller; 561 #interrupt-cells = <2>; 562 }; 563 }; 564 565 smp2p-mpss { 566 compatible = "qcom,smp2p"; 567 qcom,smem = <435>, <428>; 568 569 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 570 IPCC_MPROC_SIGNAL_SMP2P 571 IRQ_TYPE_EDGE_RISING>; 572 mboxes = <&ipcc IPCC_CLIENT_MPSS 573 IPCC_MPROC_SIGNAL_SMP2P>; 574 575 qcom,local-pid = <0>; 576 qcom,remote-pid = <1>; 577 578 modem_smp2p_out: master-kernel { 579 qcom,entry-name = "master-kernel"; 580 #qcom,smem-state-cells = <1>; 581 }; 582 583 modem_smp2p_in: slave-kernel { 584 qcom,entry-name = "slave-kernel"; 585 interrupt-controller; 586 #interrupt-cells = <2>; 587 }; 588 589 ipa_smp2p_out: ipa-ap-to-modem { 590 qcom,entry-name = "ipa"; 591 #qcom,smem-state-cells = <1>; 592 }; 593 594 ipa_smp2p_in: ipa-modem-to-ap { 595 qcom,entry-name = "ipa"; 596 interrupt-controller; 597 #interrupt-cells = <2>; 598 }; 599 }; 600 601 soc: soc@0 { 602 #address-cells = <2>; 603 #size-cells = <2>; 604 ranges = <0 0 0 0 0x10 0>; 605 dma-ranges = <0 0 0 0 0x10 0>; 606 compatible = "simple-bus"; 607 608 gcc: clock-controller@100000 { 609 compatible = "qcom,gcc-sm6350"; 610 reg = <0 0x00100000 0 0x1f0000>; 611 #clock-cells = <1>; 612 #reset-cells = <1>; 613 #power-domain-cells = <1>; 614 clock-names = "bi_tcxo", 615 "bi_tcxo_ao", 616 "sleep_clk"; 617 clocks = <&rpmhcc RPMH_CXO_CLK>, 618 <&rpmhcc RPMH_CXO_CLK_A>, 619 <&sleep_clk>; 620 }; 621 622 ipcc: mailbox@408000 { 623 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 624 reg = <0 0x00408000 0 0x1000>; 625 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 626 interrupt-controller; 627 #interrupt-cells = <3>; 628 #mbox-cells = <2>; 629 }; 630 631 rng: rng@793000 { 632 compatible = "qcom,prng-ee"; 633 reg = <0 0x00793000 0 0x1000>; 634 clocks = <&gcc GCC_PRNG_AHB_CLK>; 635 clock-names = "core"; 636 }; 637 638 sdhc_1: mmc@7c4000 { 639 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 640 reg = <0 0x007c4000 0 0x1000>, 641 <0 0x007c5000 0 0x1000>, 642 <0 0x007c8000 0 0x8000>; 643 reg-names = "hc", "cqhci", "ice"; 644 645 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 647 interrupt-names = "hc_irq", "pwr_irq"; 648 iommus = <&apps_smmu 0x60 0x0>; 649 650 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 651 <&gcc GCC_SDCC1_APPS_CLK>, 652 <&rpmhcc RPMH_CXO_CLK>; 653 clock-names = "iface", "core", "xo"; 654 resets = <&gcc GCC_SDCC1_BCR>; 655 qcom,dll-config = <0x000f642c>; 656 qcom,ddr-config = <0x80040868>; 657 power-domains = <&rpmhpd SM6350_CX>; 658 operating-points-v2 = <&sdhc1_opp_table>; 659 bus-width = <8>; 660 non-removable; 661 supports-cqe; 662 663 status = "disabled"; 664 665 sdhc1_opp_table: opp-table { 666 compatible = "operating-points-v2"; 667 668 opp-19200000 { 669 opp-hz = /bits/ 64 <19200000>; 670 required-opps = <&rpmhpd_opp_min_svs>; 671 }; 672 673 opp-100000000 { 674 opp-hz = /bits/ 64 <100000000>; 675 required-opps = <&rpmhpd_opp_low_svs>; 676 }; 677 678 opp-384000000 { 679 opp-hz = /bits/ 64 <384000000>; 680 required-opps = <&rpmhpd_opp_svs_l1>; 681 }; 682 }; 683 }; 684 685 gpi_dma0: dma-controller@800000 { 686 compatible = "qcom,sm6350-gpi-dma"; 687 reg = <0 0x00800000 0 0x60000>; 688 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 698 dma-channels = <10>; 699 dma-channel-mask = <0x1f>; 700 iommus = <&apps_smmu 0x56 0x0>; 701 #dma-cells = <3>; 702 status = "disabled"; 703 }; 704 705 qupv3_id_0: geniqup@8c0000 { 706 compatible = "qcom,geni-se-qup"; 707 reg = <0x0 0x008c0000 0x0 0x2000>; 708 clock-names = "m-ahb", "s-ahb"; 709 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 710 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 711 #address-cells = <2>; 712 #size-cells = <2>; 713 iommus = <&apps_smmu 0x43 0x0>; 714 ranges; 715 status = "disabled"; 716 717 i2c0: i2c@880000 { 718 compatible = "qcom,geni-i2c"; 719 reg = <0 0x00880000 0 0x4000>; 720 clock-names = "se"; 721 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 722 pinctrl-names = "default"; 723 pinctrl-0 = <&qup_i2c0_default>; 724 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 725 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 726 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 727 dma-names = "tx", "rx"; 728 #address-cells = <1>; 729 #size-cells = <0>; 730 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 731 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 732 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 733 interconnect-names = "qup-core", "qup-config", "qup-memory"; 734 status = "disabled"; 735 }; 736 737 i2c2: i2c@888000 { 738 compatible = "qcom,geni-i2c"; 739 reg = <0 0x00888000 0 0x4000>; 740 clock-names = "se"; 741 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 742 pinctrl-names = "default"; 743 pinctrl-0 = <&qup_i2c2_default>; 744 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 745 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 746 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 747 dma-names = "tx", "rx"; 748 #address-cells = <1>; 749 #size-cells = <0>; 750 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 751 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 752 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 753 interconnect-names = "qup-core", "qup-config", "qup-memory"; 754 status = "disabled"; 755 }; 756 }; 757 758 gpi_dma1: dma-controller@900000 { 759 compatible = "qcom,sm6350-gpi-dma"; 760 reg = <0 0x00900000 0 0x60000>; 761 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 771 dma-channels = <10>; 772 dma-channel-mask = <0x3f>; 773 iommus = <&apps_smmu 0x4d6 0x0>; 774 #dma-cells = <3>; 775 status = "disabled"; 776 }; 777 778 qupv3_id_1: geniqup@9c0000 { 779 compatible = "qcom,geni-se-qup"; 780 reg = <0x0 0x009c0000 0x0 0x2000>; 781 clock-names = "m-ahb", "s-ahb"; 782 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 783 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 784 #address-cells = <2>; 785 #size-cells = <2>; 786 iommus = <&apps_smmu 0x4c3 0x0>; 787 ranges; 788 status = "disabled"; 789 790 i2c6: i2c@980000 { 791 compatible = "qcom,geni-i2c"; 792 reg = <0 0x00980000 0 0x4000>; 793 clock-names = "se"; 794 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 795 pinctrl-names = "default"; 796 pinctrl-0 = <&qup_i2c6_default>; 797 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 798 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 799 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 800 dma-names = "tx", "rx"; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 804 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 805 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 806 interconnect-names = "qup-core", "qup-config", "qup-memory"; 807 status = "disabled"; 808 }; 809 810 i2c7: i2c@984000 { 811 compatible = "qcom,geni-i2c"; 812 reg = <0 0x00984000 0 0x4000>; 813 clock-names = "se"; 814 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 815 pinctrl-names = "default"; 816 pinctrl-0 = <&qup_i2c7_default>; 817 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 818 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 819 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 820 dma-names = "tx", "rx"; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 824 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 825 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 826 interconnect-names = "qup-core", "qup-config", "qup-memory"; 827 status = "disabled"; 828 }; 829 830 i2c8: i2c@988000 { 831 compatible = "qcom,geni-i2c"; 832 reg = <0 0x00988000 0 0x4000>; 833 clock-names = "se"; 834 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 835 pinctrl-names = "default"; 836 pinctrl-0 = <&qup_i2c8_default>; 837 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 838 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 839 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 840 dma-names = "tx", "rx"; 841 #address-cells = <1>; 842 #size-cells = <0>; 843 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 844 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 845 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 846 interconnect-names = "qup-core", "qup-config", "qup-memory"; 847 status = "disabled"; 848 }; 849 850 uart9: serial@98c000 { 851 compatible = "qcom,geni-debug-uart"; 852 reg = <0 0x0098c000 0 0x4000>; 853 clock-names = "se"; 854 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 855 pinctrl-names = "default"; 856 pinctrl-0 = <&qup_uart9_default>; 857 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 858 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 859 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 860 interconnect-names = "qup-core", "qup-config"; 861 status = "disabled"; 862 }; 863 864 i2c10: i2c@990000 { 865 compatible = "qcom,geni-i2c"; 866 reg = <0 0x00990000 0 0x4000>; 867 clock-names = "se"; 868 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 869 pinctrl-names = "default"; 870 pinctrl-0 = <&qup_i2c10_default>; 871 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 872 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 873 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 874 dma-names = "tx", "rx"; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 878 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 879 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 880 interconnect-names = "qup-core", "qup-config", "qup-memory"; 881 status = "disabled"; 882 }; 883 884 }; 885 886 config_noc: interconnect@1500000 { 887 compatible = "qcom,sm6350-config-noc"; 888 reg = <0 0x01500000 0 0x28000>; 889 #interconnect-cells = <2>; 890 qcom,bcm-voters = <&apps_bcm_voter>; 891 }; 892 893 system_noc: interconnect@1620000 { 894 compatible = "qcom,sm6350-system-noc"; 895 reg = <0 0x01620000 0 0x17080>; 896 #interconnect-cells = <2>; 897 qcom,bcm-voters = <&apps_bcm_voter>; 898 899 clk_virt: interconnect-clk-virt { 900 compatible = "qcom,sm6350-clk-virt"; 901 #interconnect-cells = <2>; 902 qcom,bcm-voters = <&apps_bcm_voter>; 903 }; 904 }; 905 906 aggre1_noc: interconnect@16e0000 { 907 compatible = "qcom,sm6350-aggre1-noc"; 908 reg = <0 0x016e0000 0 0x15080>; 909 #interconnect-cells = <2>; 910 qcom,bcm-voters = <&apps_bcm_voter>; 911 }; 912 913 aggre2_noc: interconnect@1700000 { 914 compatible = "qcom,sm6350-aggre2-noc"; 915 reg = <0 0x01700000 0 0x1f880>; 916 #interconnect-cells = <2>; 917 qcom,bcm-voters = <&apps_bcm_voter>; 918 919 compute_noc: interconnect-compute-noc { 920 compatible = "qcom,sm6350-compute-noc"; 921 #interconnect-cells = <2>; 922 qcom,bcm-voters = <&apps_bcm_voter>; 923 }; 924 }; 925 926 mmss_noc: interconnect@1740000 { 927 compatible = "qcom,sm6350-mmss-noc"; 928 reg = <0 0x01740000 0 0x1c100>; 929 #interconnect-cells = <2>; 930 qcom,bcm-voters = <&apps_bcm_voter>; 931 }; 932 933 ufs_mem_hc: ufs@1d84000 { 934 compatible = "qcom,sm6350-ufshc", "qcom,ufshc", 935 "jedec,ufs-2.0"; 936 reg = <0 0x01d84000 0 0x3000>, 937 <0 0x01d90000 0 0x8000>; 938 reg-names = "std", "ice"; 939 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 940 phys = <&ufs_mem_phy_lanes>; 941 phy-names = "ufsphy"; 942 lanes-per-direction = <2>; 943 #reset-cells = <1>; 944 resets = <&gcc GCC_UFS_PHY_BCR>; 945 reset-names = "rst"; 946 947 power-domains = <&gcc UFS_PHY_GDSC>; 948 949 iommus = <&apps_smmu 0x80 0x0>; 950 951 clock-names = "core_clk", 952 "bus_aggr_clk", 953 "iface_clk", 954 "core_clk_unipro", 955 "ref_clk", 956 "tx_lane0_sync_clk", 957 "rx_lane0_sync_clk", 958 "rx_lane1_sync_clk", 959 "ice_core_clk"; 960 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 961 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 962 <&gcc GCC_UFS_PHY_AHB_CLK>, 963 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 964 <&rpmhcc RPMH_QLINK_CLK>, 965 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 966 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 967 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 968 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 969 freq-table-hz = 970 <50000000 200000000>, 971 <0 0>, 972 <0 0>, 973 <37500000 150000000>, 974 <75000000 300000000>, 975 <0 0>, 976 <0 0>, 977 <0 0>, 978 <0 0>; 979 980 status = "disabled"; 981 }; 982 983 ufs_mem_phy: phy@1d87000 { 984 compatible = "qcom,sm6350-qmp-ufs-phy"; 985 reg = <0 0x01d87000 0 0x18c>; 986 #address-cells = <2>; 987 #size-cells = <2>; 988 ranges; 989 990 clock-names = "ref", 991 "ref_aux"; 992 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 993 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 994 995 resets = <&ufs_mem_hc 0>; 996 reset-names = "ufsphy"; 997 998 status = "disabled"; 999 1000 ufs_mem_phy_lanes: phy@1d87400 { 1001 reg = <0 0x01d87400 0 0x128>, 1002 <0 0x01d87600 0 0x1fc>, 1003 <0 0x01d87c00 0 0x1dc>, 1004 <0 0x01d87800 0 0x128>, 1005 <0 0x01d87a00 0 0x1fc>; 1006 #phy-cells = <0>; 1007 }; 1008 }; 1009 1010 ipa: ipa@1e40000 { 1011 compatible = "qcom,sm6350-ipa"; 1012 1013 iommus = <&apps_smmu 0x440 0x0>, 1014 <&apps_smmu 0x442 0x0>; 1015 reg = <0 0x01e40000 0 0x8000>, 1016 <0 0x01e50000 0 0x3000>, 1017 <0 0x01e04000 0 0x23000>; 1018 reg-names = "ipa-reg", 1019 "ipa-shared", 1020 "gsi"; 1021 1022 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1023 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1024 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1025 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1026 interrupt-names = "ipa", 1027 "gsi", 1028 "ipa-clock-query", 1029 "ipa-setup-ready"; 1030 1031 clocks = <&rpmhcc RPMH_IPA_CLK>; 1032 clock-names = "core"; 1033 1034 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>, 1035 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, 1036 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; 1037 interconnect-names = "memory", "imem", "config"; 1038 1039 qcom,smem-states = <&ipa_smp2p_out 0>, 1040 <&ipa_smp2p_out 1>; 1041 qcom,smem-state-names = "ipa-clock-enabled-valid", 1042 "ipa-clock-enabled"; 1043 1044 status = "disabled"; 1045 }; 1046 1047 tcsr_mutex: hwlock@1f40000 { 1048 compatible = "qcom,tcsr-mutex"; 1049 reg = <0x0 0x01f40000 0x0 0x40000>; 1050 #hwlock-cells = <1>; 1051 }; 1052 1053 adsp: remoteproc@3000000 { 1054 compatible = "qcom,sm6350-adsp-pas"; 1055 reg = <0 0x03000000 0 0x100>; 1056 1057 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 1058 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1059 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1060 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1061 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1062 interrupt-names = "wdog", "fatal", "ready", 1063 "handover", "stop-ack"; 1064 1065 clocks = <&rpmhcc RPMH_CXO_CLK>; 1066 clock-names = "xo"; 1067 1068 power-domains = <&rpmhpd SM6350_LCX>, 1069 <&rpmhpd SM6350_LMX>; 1070 power-domain-names = "lcx", "lmx"; 1071 1072 memory-region = <&pil_adsp_mem>; 1073 1074 qcom,qmp = <&aoss_qmp>; 1075 1076 qcom,smem-states = <&smp2p_adsp_out 0>; 1077 qcom,smem-state-names = "stop"; 1078 1079 status = "disabled"; 1080 1081 glink-edge { 1082 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1083 IPCC_MPROC_SIGNAL_GLINK_QMP 1084 IRQ_TYPE_EDGE_RISING>; 1085 mboxes = <&ipcc IPCC_CLIENT_LPASS 1086 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1087 1088 label = "lpass"; 1089 qcom,remote-pid = <2>; 1090 1091 fastrpc { 1092 compatible = "qcom,fastrpc"; 1093 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1094 label = "adsp"; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 1098 compute-cb@3 { 1099 compatible = "qcom,fastrpc-compute-cb"; 1100 reg = <3>; 1101 iommus = <&apps_smmu 0x1003 0x0>; 1102 }; 1103 1104 compute-cb@4 { 1105 compatible = "qcom,fastrpc-compute-cb"; 1106 reg = <4>; 1107 iommus = <&apps_smmu 0x1004 0x0>; 1108 }; 1109 1110 compute-cb@5 { 1111 compatible = "qcom,fastrpc-compute-cb"; 1112 reg = <5>; 1113 iommus = <&apps_smmu 0x1005 0x0>; 1114 qcom,nsessions = <5>; 1115 }; 1116 }; 1117 }; 1118 }; 1119 1120 mpss: remoteproc@4080000 { 1121 compatible = "qcom,sm6350-mpss-pas"; 1122 reg = <0x0 0x04080000 0x0 0x4040>; 1123 1124 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 1125 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1126 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1127 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1128 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1129 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1130 interrupt-names = "wdog", "fatal", "ready", "handover", 1131 "stop-ack", "shutdown-ack"; 1132 1133 clocks = <&rpmhcc RPMH_CXO_CLK>; 1134 clock-names = "xo"; 1135 1136 power-domains = <&rpmhpd SM6350_CX>, 1137 <&rpmhpd SM6350_MSS>; 1138 power-domain-names = "cx", "mss"; 1139 1140 memory-region = <&pil_modem_mem>; 1141 1142 qcom,qmp = <&aoss_qmp>; 1143 1144 qcom,smem-states = <&modem_smp2p_out 0>; 1145 qcom,smem-state-names = "stop"; 1146 1147 status = "disabled"; 1148 1149 glink-edge { 1150 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1151 IPCC_MPROC_SIGNAL_GLINK_QMP 1152 IRQ_TYPE_EDGE_RISING>; 1153 mboxes = <&ipcc IPCC_CLIENT_MPSS 1154 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1155 label = "modem"; 1156 qcom,remote-pid = <1>; 1157 }; 1158 }; 1159 1160 cdsp: remoteproc@8300000 { 1161 compatible = "qcom,sm6350-cdsp-pas"; 1162 reg = <0 0x08300000 0 0x10000>; 1163 1164 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 1165 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1166 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1167 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1168 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1169 interrupt-names = "wdog", "fatal", "ready", 1170 "handover", "stop-ack"; 1171 1172 clocks = <&rpmhcc RPMH_CXO_CLK>; 1173 clock-names = "xo"; 1174 1175 power-domains = <&rpmhpd SM6350_CX>, 1176 <&rpmhpd SM6350_MX>; 1177 power-domain-names = "cx", "mx"; 1178 1179 memory-region = <&pil_cdsp_mem>; 1180 1181 qcom,qmp = <&aoss_qmp>; 1182 1183 qcom,smem-states = <&smp2p_cdsp_out 0>; 1184 qcom,smem-state-names = "stop"; 1185 1186 status = "disabled"; 1187 1188 glink-edge { 1189 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1190 IPCC_MPROC_SIGNAL_GLINK_QMP 1191 IRQ_TYPE_EDGE_RISING>; 1192 mboxes = <&ipcc IPCC_CLIENT_CDSP 1193 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1194 1195 label = "cdsp"; 1196 qcom,remote-pid = <5>; 1197 1198 fastrpc { 1199 compatible = "qcom,fastrpc"; 1200 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1201 label = "cdsp"; 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 1205 compute-cb@1 { 1206 compatible = "qcom,fastrpc-compute-cb"; 1207 reg = <1>; 1208 iommus = <&apps_smmu 0x1401 0x20>; 1209 }; 1210 1211 compute-cb@2 { 1212 compatible = "qcom,fastrpc-compute-cb"; 1213 reg = <2>; 1214 iommus = <&apps_smmu 0x1402 0x20>; 1215 }; 1216 1217 compute-cb@3 { 1218 compatible = "qcom,fastrpc-compute-cb"; 1219 reg = <3>; 1220 iommus = <&apps_smmu 0x1403 0x20>; 1221 }; 1222 1223 compute-cb@4 { 1224 compatible = "qcom,fastrpc-compute-cb"; 1225 reg = <4>; 1226 iommus = <&apps_smmu 0x1404 0x20>; 1227 }; 1228 1229 compute-cb@5 { 1230 compatible = "qcom,fastrpc-compute-cb"; 1231 reg = <5>; 1232 iommus = <&apps_smmu 0x1405 0x20>; 1233 }; 1234 1235 compute-cb@6 { 1236 compatible = "qcom,fastrpc-compute-cb"; 1237 reg = <6>; 1238 iommus = <&apps_smmu 0x1406 0x20>; 1239 }; 1240 1241 compute-cb@7 { 1242 compatible = "qcom,fastrpc-compute-cb"; 1243 reg = <7>; 1244 iommus = <&apps_smmu 0x1407 0x20>; 1245 }; 1246 1247 compute-cb@8 { 1248 compatible = "qcom,fastrpc-compute-cb"; 1249 reg = <8>; 1250 iommus = <&apps_smmu 0x1408 0x20>; 1251 }; 1252 1253 /* note: secure cb9 in downstream */ 1254 }; 1255 }; 1256 }; 1257 1258 sdhc_2: mmc@8804000 { 1259 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 1260 reg = <0 0x08804000 0 0x1000>; 1261 1262 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1264 interrupt-names = "hc_irq", "pwr_irq"; 1265 iommus = <&apps_smmu 0x560 0x0>; 1266 1267 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1268 <&gcc GCC_SDCC2_APPS_CLK>, 1269 <&rpmhcc RPMH_CXO_CLK>; 1270 clock-names = "iface", "core", "xo"; 1271 resets = <&gcc GCC_SDCC2_BCR>; 1272 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, 1273 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; 1274 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1275 1276 pinctrl-0 = <&sdc2_on_state>; 1277 pinctrl-1 = <&sdc2_off_state>; 1278 pinctrl-names = "default", "sleep"; 1279 1280 qcom,dll-config = <0x0007642c>; 1281 qcom,ddr-config = <0x80040868>; 1282 power-domains = <&rpmhpd SM6350_CX>; 1283 operating-points-v2 = <&sdhc2_opp_table>; 1284 bus-width = <4>; 1285 1286 status = "disabled"; 1287 1288 sdhc2_opp_table: opp-table { 1289 compatible = "operating-points-v2"; 1290 1291 opp-100000000 { 1292 opp-hz = /bits/ 64 <100000000>; 1293 required-opps = <&rpmhpd_opp_svs_l1>; 1294 opp-peak-kBps = <790000 131000>; 1295 opp-avg-kBps = <50000 50000>; 1296 }; 1297 1298 opp-202000000 { 1299 opp-hz = /bits/ 64 <202000000>; 1300 required-opps = <&rpmhpd_opp_nom>; 1301 opp-peak-kBps = <3190000 294000>; 1302 opp-avg-kBps = <261438 300000>; 1303 }; 1304 }; 1305 }; 1306 1307 usb_1_hsphy: phy@88e3000 { 1308 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 1309 reg = <0 0x088e3000 0 0x400>; 1310 status = "disabled"; 1311 #phy-cells = <0>; 1312 1313 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 1314 clock-names = "cfg_ahb", "ref"; 1315 1316 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1317 }; 1318 1319 usb_1_qmpphy: phy@88e8000 { 1320 compatible = "qcom,sm6350-qmp-usb3-dp-phy"; 1321 reg = <0 0x088e8000 0 0x3000>; 1322 1323 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1324 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1325 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1326 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1327 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 1328 1329 power-domains = <&gcc USB30_PRIM_GDSC>; 1330 1331 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1332 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1333 reset-names = "phy", "common"; 1334 1335 #clock-cells = <1>; 1336 #phy-cells = <1>; 1337 1338 status = "disabled"; 1339 }; 1340 1341 dc_noc: interconnect@9160000 { 1342 compatible = "qcom,sm6350-dc-noc"; 1343 reg = <0 0x09160000 0 0x3200>; 1344 #interconnect-cells = <2>; 1345 qcom,bcm-voters = <&apps_bcm_voter>; 1346 }; 1347 1348 system-cache-controller@9200000 { 1349 compatible = "qcom,sm6350-llcc"; 1350 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 1351 reg-names = "llcc_base", "llcc_broadcast_base"; 1352 }; 1353 1354 gem_noc: interconnect@9680000 { 1355 compatible = "qcom,sm6350-gem-noc"; 1356 reg = <0 0x09680000 0 0x3e200>; 1357 #interconnect-cells = <2>; 1358 qcom,bcm-voters = <&apps_bcm_voter>; 1359 }; 1360 1361 npu_noc: interconnect@9990000 { 1362 compatible = "qcom,sm6350-npu-noc"; 1363 reg = <0 0x09990000 0 0x1600>; 1364 #interconnect-cells = <2>; 1365 qcom,bcm-voters = <&apps_bcm_voter>; 1366 }; 1367 1368 usb_1: usb@a6f8800 { 1369 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 1370 reg = <0 0x0a6f8800 0 0x400>; 1371 status = "disabled"; 1372 #address-cells = <2>; 1373 #size-cells = <2>; 1374 ranges; 1375 1376 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1377 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1378 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1379 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1380 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1381 clock-names = "cfg_noc", 1382 "core", 1383 "iface", 1384 "sleep", 1385 "mock_utmi"; 1386 1387 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1388 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 1389 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1390 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 1391 1392 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1393 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1394 1395 power-domains = <&gcc USB30_PRIM_GDSC>; 1396 1397 resets = <&gcc GCC_USB30_PRIM_BCR>; 1398 1399 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, 1400 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1401 interconnect-names = "usb-ddr", "apps-usb"; 1402 1403 usb_1_dwc3: usb@a600000 { 1404 compatible = "snps,dwc3"; 1405 reg = <0 0x0a600000 0 0xcd00>; 1406 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1407 iommus = <&apps_smmu 0x540 0x0>; 1408 snps,dis_u2_susphy_quirk; 1409 snps,dis_enblslpm_quirk; 1410 snps,has-lpm-erratum; 1411 snps,hird-threshold = /bits/ 8 <0x10>; 1412 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 1413 phy-names = "usb2-phy", "usb3-phy"; 1414 }; 1415 }; 1416 1417 cci0: cci@ac4a000 { 1418 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 1419 reg = <0 0x0ac4a000 0 0x1000>; 1420 interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; 1421 power-domains = <&camcc TITAN_TOP_GDSC>; 1422 1423 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1424 <&camcc CAMCC_SOC_AHB_CLK>, 1425 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 1426 <&camcc CAMCC_CPAS_AHB_CLK>, 1427 <&camcc CAMCC_CCI_0_CLK>, 1428 <&camcc CAMCC_CCI_0_CLK_SRC>; 1429 clock-names = "camnoc_axi", 1430 "soc_ahb", 1431 "slow_ahb_src", 1432 "cpas_ahb", 1433 "cci", 1434 "cci_src"; 1435 1436 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1437 <&camcc CAMCC_CCI_0_CLK>; 1438 assigned-clock-rates = <80000000>, <37500000>; 1439 1440 pinctrl-0 = <&cci0_default &cci1_default>; 1441 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 1442 pinctrl-names = "default", "sleep"; 1443 1444 #address-cells = <1>; 1445 #size-cells = <0>; 1446 1447 status = "disabled"; 1448 1449 cci0_i2c0: i2c-bus@0 { 1450 reg = <0>; 1451 clock-frequency = <1000000>; 1452 #address-cells = <1>; 1453 #size-cells = <0>; 1454 }; 1455 1456 cci0_i2c1: i2c-bus@1 { 1457 reg = <1>; 1458 clock-frequency = <1000000>; 1459 #address-cells = <1>; 1460 #size-cells = <0>; 1461 }; 1462 }; 1463 1464 cci1: cci@ac4b000 { 1465 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 1466 reg = <0 0x0ac4b000 0 0x1000>; 1467 interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; 1468 power-domains = <&camcc TITAN_TOP_GDSC>; 1469 1470 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1471 <&camcc CAMCC_SOC_AHB_CLK>, 1472 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 1473 <&camcc CAMCC_CPAS_AHB_CLK>, 1474 <&camcc CAMCC_CCI_1_CLK>, 1475 <&camcc CAMCC_CCI_1_CLK_SRC>; 1476 clock-names = "camnoc_axi", 1477 "soc_ahb", 1478 "slow_ahb_src", 1479 "cpas_ahb", 1480 "cci", 1481 "cci_src"; 1482 1483 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1484 <&camcc CAMCC_CCI_1_CLK>; 1485 assigned-clock-rates = <80000000>, <37500000>; 1486 1487 pinctrl-0 = <&cci2_default>; 1488 pinctrl-1 = <&cci2_sleep>; 1489 pinctrl-names = "default", "sleep"; 1490 1491 #address-cells = <1>; 1492 #size-cells = <0>; 1493 1494 status = "disabled"; 1495 1496 cci1_i2c0: i2c-bus@0 { 1497 reg = <0>; 1498 clock-frequency = <1000000>; 1499 #address-cells = <1>; 1500 #size-cells = <0>; 1501 }; 1502 1503 /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ 1504 }; 1505 1506 camcc: clock-controller@ad00000 { 1507 compatible = "qcom,sm6350-camcc"; 1508 reg = <0 0x0ad00000 0 0x16000>; 1509 clocks = <&rpmhcc RPMH_CXO_CLK>; 1510 #clock-cells = <1>; 1511 #reset-cells = <1>; 1512 #power-domain-cells = <1>; 1513 }; 1514 1515 pdc: interrupt-controller@b220000 { 1516 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 1517 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; 1518 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 1519 <125 63 1>, <126 655 12>, <138 139 15>; 1520 #interrupt-cells = <2>; 1521 interrupt-parent = <&intc>; 1522 interrupt-controller; 1523 }; 1524 1525 tsens0: thermal-sensor@c263000 { 1526 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1527 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1528 <0 0x0c222000 0 0x8>; /* SROT */ 1529 #qcom,sensors = <16>; 1530 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 1531 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 1532 interrupt-names = "uplow", "critical"; 1533 #thermal-sensor-cells = <1>; 1534 }; 1535 1536 tsens1: thermal-sensor@c265000 { 1537 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1538 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1539 <0 0x0c223000 0 0x8>; /* SROT */ 1540 #qcom,sensors = <16>; 1541 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 1542 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 1543 interrupt-names = "uplow", "critical"; 1544 #thermal-sensor-cells = <1>; 1545 }; 1546 1547 aoss_qmp: power-management@c300000 { 1548 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 1549 reg = <0 0x0c300000 0 0x1000>; 1550 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 1551 IRQ_TYPE_EDGE_RISING>; 1552 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 1553 1554 #clock-cells = <0>; 1555 }; 1556 1557 spmi_bus: spmi@c440000 { 1558 compatible = "qcom,spmi-pmic-arb"; 1559 reg = <0 0x0c440000 0 0x1100>, 1560 <0 0x0c600000 0 0x2000000>, 1561 <0 0x0e600000 0 0x100000>, 1562 <0 0x0e700000 0 0xa0000>, 1563 <0 0x0c40a000 0 0x26000>; 1564 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1565 interrupt-names = "periph_irq"; 1566 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1567 qcom,ee = <0>; 1568 qcom,channel = <0>; 1569 #address-cells = <2>; 1570 #size-cells = <0>; 1571 interrupt-controller; 1572 #interrupt-cells = <4>; 1573 }; 1574 1575 tlmm: pinctrl@f100000 { 1576 compatible = "qcom,sm6350-tlmm"; 1577 reg = <0 0x0f100000 0 0x300000>; 1578 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1582 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 1587 gpio-controller; 1588 #gpio-cells = <2>; 1589 interrupt-controller; 1590 #interrupt-cells = <2>; 1591 gpio-ranges = <&tlmm 0 0 157>; 1592 1593 cci0_default: cci0-default-state { 1594 pins = "gpio39", "gpio40"; 1595 function = "cci_i2c"; 1596 drive-strength = <2>; 1597 bias-pull-up; 1598 }; 1599 1600 cci0_sleep: cci0-sleep-state { 1601 pins = "gpio39", "gpio40"; 1602 function = "cci_i2c"; 1603 drive-strength = <2>; 1604 bias-pull-down; 1605 }; 1606 1607 cci1_default: cci1-default-state { 1608 pins = "gpio41", "gpio42"; 1609 function = "cci_i2c"; 1610 drive-strength = <2>; 1611 bias-pull-up; 1612 }; 1613 1614 cci1_sleep: cci1-sleep-state { 1615 pins = "gpio41", "gpio42"; 1616 function = "cci_i2c"; 1617 drive-strength = <2>; 1618 bias-pull-down; 1619 }; 1620 1621 cci2_default: cci2-default-state { 1622 pins = "gpio43", "gpio44"; 1623 function = "cci_i2c"; 1624 drive-strength = <2>; 1625 bias-pull-up; 1626 }; 1627 1628 cci2_sleep: cci2-sleep-state { 1629 pins = "gpio43", "gpio44"; 1630 function = "cci_i2c"; 1631 drive-strength = <2>; 1632 bias-pull-down; 1633 }; 1634 1635 sdc2_off_state: sdc2-off-state { 1636 clk-pins { 1637 pins = "sdc2_clk"; 1638 drive-strength = <2>; 1639 bias-disable; 1640 }; 1641 1642 cmd-pins { 1643 pins = "sdc2_cmd"; 1644 drive-strength = <2>; 1645 bias-pull-up; 1646 }; 1647 1648 data-pins { 1649 pins = "sdc2_data"; 1650 drive-strength = <2>; 1651 bias-pull-up; 1652 }; 1653 }; 1654 1655 sdc2_on_state: sdc2-on-state { 1656 clk-pins { 1657 pins = "sdc2_clk"; 1658 drive-strength = <16>; 1659 bias-disable; 1660 }; 1661 1662 cmd-pins { 1663 pins = "sdc2_cmd"; 1664 drive-strength = <10>; 1665 bias-pull-up; 1666 }; 1667 1668 data-pins { 1669 pins = "sdc2_data"; 1670 drive-strength = <10>; 1671 bias-pull-up; 1672 }; 1673 }; 1674 1675 qup_uart9_default: qup-uart9-default-state { 1676 pins = "gpio25", "gpio26"; 1677 function = "qup13_f2"; 1678 drive-strength = <2>; 1679 bias-disable; 1680 }; 1681 1682 qup_i2c0_default: qup-i2c0-default-state { 1683 pins = "gpio0", "gpio1"; 1684 function = "qup00"; 1685 drive-strength = <2>; 1686 bias-pull-up; 1687 }; 1688 1689 qup_i2c2_default: qup-i2c2-default-state { 1690 pins = "gpio45", "gpio46"; 1691 function = "qup02"; 1692 drive-strength = <2>; 1693 bias-pull-up; 1694 }; 1695 1696 qup_i2c6_default: qup-i2c6-default-state { 1697 pins = "gpio13", "gpio14"; 1698 function = "qup10"; 1699 drive-strength = <2>; 1700 bias-pull-up; 1701 }; 1702 1703 qup_i2c7_default: qup-i2c7-default-state { 1704 pins = "gpio27", "gpio28"; 1705 function = "qup11"; 1706 drive-strength = <2>; 1707 bias-pull-up; 1708 }; 1709 1710 qup_i2c8_default: qup-i2c8-default-state { 1711 pins = "gpio19", "gpio20"; 1712 function = "qup12"; 1713 drive-strength = <2>; 1714 bias-pull-up; 1715 }; 1716 1717 qup_i2c10_default: qup-i2c10-default-state { 1718 pins = "gpio4", "gpio5"; 1719 function = "qup14"; 1720 drive-strength = <2>; 1721 bias-pull-up; 1722 }; 1723 }; 1724 1725 apps_smmu: iommu@15000000 { 1726 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 1727 reg = <0 0x15000000 0 0x100000>; 1728 #iommu-cells = <2>; 1729 #global-interrupts = <1>; 1730 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1748 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1749 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1811 }; 1812 1813 intc: interrupt-controller@17a00000 { 1814 compatible = "arm,gic-v3"; 1815 #interrupt-cells = <3>; 1816 interrupt-controller; 1817 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 1818 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 1819 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 1820 }; 1821 1822 watchdog@17c10000 { 1823 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 1824 reg = <0 0x17c10000 0 0x1000>; 1825 clocks = <&sleep_clk>; 1826 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1827 }; 1828 1829 timer@17c20000 { 1830 compatible = "arm,armv7-timer-mem"; 1831 reg = <0x0 0x17c20000 0x0 0x1000>; 1832 clock-frequency = <19200000>; 1833 #address-cells = <1>; 1834 #size-cells = <1>; 1835 ranges = <0 0 0 0x20000000>; 1836 1837 frame@17c21000 { 1838 frame-number = <0>; 1839 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1841 reg = <0x17c21000 0x1000>, 1842 <0x17c22000 0x1000>; 1843 }; 1844 1845 frame@17c23000 { 1846 frame-number = <1>; 1847 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1848 reg = <0x17c23000 0x1000>; 1849 status = "disabled"; 1850 }; 1851 1852 frame@17c25000 { 1853 frame-number = <2>; 1854 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1855 reg = <0x17c25000 0x1000>; 1856 status = "disabled"; 1857 }; 1858 1859 frame@17c27000 { 1860 frame-number = <3>; 1861 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1862 reg = <0x17c27000 0x1000>; 1863 status = "disabled"; 1864 }; 1865 1866 frame@17c29000 { 1867 frame-number = <4>; 1868 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1869 reg = <0x17c29000 0x1000>; 1870 status = "disabled"; 1871 }; 1872 1873 frame@17c2b000 { 1874 frame-number = <5>; 1875 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1876 reg = <0x17c2b000 0x1000>; 1877 status = "disabled"; 1878 }; 1879 1880 frame@17c2d000 { 1881 frame-number = <6>; 1882 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1883 reg = <0x17c2d000 0x1000>; 1884 status = "disabled"; 1885 }; 1886 }; 1887 1888 wifi: wifi@18800000 { 1889 compatible = "qcom,wcn3990-wifi"; 1890 reg = <0 0x18800000 0 0x800000>; 1891 reg-names = "membase"; 1892 memory-region = <&wlan_fw_mem>; 1893 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 1905 iommus = <&apps_smmu 0x20 0x1>; 1906 qcom,msa-fixed-perm; 1907 status = "disabled"; 1908 }; 1909 1910 apps_rsc: rsc@18200000 { 1911 compatible = "qcom,rpmh-rsc"; 1912 label = "apps_rsc"; 1913 reg = <0x0 0x18200000 0x0 0x10000>, 1914 <0x0 0x18210000 0x0 0x10000>, 1915 <0x0 0x18220000 0x0 0x10000>; 1916 reg-names = "drv-0", "drv-1", "drv-2"; 1917 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1920 qcom,tcs-offset = <0xd00>; 1921 qcom,drv-id = <2>; 1922 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 1923 <WAKE_TCS 3>, <CONTROL_TCS 1>; 1924 1925 rpmhcc: clock-controller { 1926 compatible = "qcom,sm6350-rpmh-clk"; 1927 #clock-cells = <1>; 1928 clock-names = "xo"; 1929 clocks = <&xo_board>; 1930 }; 1931 1932 rpmhpd: power-controller { 1933 compatible = "qcom,sm6350-rpmhpd"; 1934 #power-domain-cells = <1>; 1935 operating-points-v2 = <&rpmhpd_opp_table>; 1936 1937 rpmhpd_opp_table: opp-table { 1938 compatible = "operating-points-v2"; 1939 1940 rpmhpd_opp_ret: opp1 { 1941 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1942 }; 1943 1944 rpmhpd_opp_min_svs: opp2 { 1945 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1946 }; 1947 1948 rpmhpd_opp_low_svs: opp3 { 1949 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1950 }; 1951 1952 rpmhpd_opp_svs: opp4 { 1953 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1954 }; 1955 1956 rpmhpd_opp_svs_l1: opp5 { 1957 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1958 }; 1959 1960 rpmhpd_opp_nom: opp6 { 1961 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1962 }; 1963 1964 rpmhpd_opp_nom_l1: opp7 { 1965 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1966 }; 1967 1968 rpmhpd_opp_nom_l2: opp8 { 1969 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1970 }; 1971 1972 rpmhpd_opp_turbo: opp9 { 1973 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1974 }; 1975 1976 rpmhpd_opp_turbo_l1: opp10 { 1977 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1978 }; 1979 }; 1980 }; 1981 1982 apps_bcm_voter: bcm-voter { 1983 compatible = "qcom,bcm-voter"; 1984 }; 1985 }; 1986 1987 osm_l3: interconnect@18321000 { 1988 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3"; 1989 reg = <0x0 0x18321000 0x0 0x1000>; 1990 1991 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 1992 clock-names = "xo", "alternate"; 1993 1994 #interconnect-cells = <1>; 1995 }; 1996 1997 cpufreq_hw: cpufreq@18323000 { 1998 compatible = "qcom,cpufreq-hw"; 1999 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; 2000 reg-names = "freq-domain0", "freq-domain1"; 2001 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2002 clock-names = "xo", "alternate"; 2003 2004 #freq-domain-cells = <1>; 2005 }; 2006 }; 2007 2008 timer { 2009 compatible = "arm,armv8-timer"; 2010 clock-frequency = <19200000>; 2011 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2012 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2013 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2014 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2015 }; 2016}; 2017