1// SPDX-License-Identifier: (GPL-2.0 or MIT)
2/*
3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/power/r8a779f0-sysc.h>
11
12/ {
13	compatible = "renesas,r8a779f0";
14	#address-cells = <2>;
15	#size-cells = <2>;
16
17	cluster01_opp: opp-table-0 {
18		compatible = "operating-points-v2";
19		opp-shared;
20
21		opp-500000000 {
22			opp-hz = /bits/ 64 <500000000>;
23			opp-microvolt = <880000>;
24			clock-latency-ns = <500000>;
25		};
26		opp-800000000 {
27			opp-hz = /bits/ 64 <800000000>;
28			opp-microvolt = <880000>;
29			clock-latency-ns = <500000>;
30		};
31		opp-1000000000 {
32			opp-hz = /bits/ 64 <1000000000>;
33			opp-microvolt = <880000>;
34			clock-latency-ns = <500000>;
35		};
36		opp-1200000000 {
37			opp-hz = /bits/ 64 <1200000000>;
38			opp-microvolt = <880000>;
39			clock-latency-ns = <500000>;
40			opp-suspend;
41		};
42	};
43
44	cluster23_opp: opp-table-1 {
45		compatible = "operating-points-v2";
46		opp-shared;
47
48		opp-500000000 {
49			opp-hz = /bits/ 64 <500000000>;
50			opp-microvolt = <880000>;
51			clock-latency-ns = <500000>;
52		};
53		opp-800000000 {
54			opp-hz = /bits/ 64 <800000000>;
55			opp-microvolt = <880000>;
56			clock-latency-ns = <500000>;
57		};
58		opp-1000000000 {
59			opp-hz = /bits/ 64 <1000000000>;
60			opp-microvolt = <880000>;
61			clock-latency-ns = <500000>;
62		};
63		opp-1200000000 {
64			opp-hz = /bits/ 64 <1200000000>;
65			opp-microvolt = <880000>;
66			clock-latency-ns = <500000>;
67			opp-suspend;
68		};
69	};
70
71	cpus {
72		#address-cells = <1>;
73		#size-cells = <0>;
74
75		cpu-map {
76			cluster0 {
77				core0 {
78					cpu = <&a55_0>;
79				};
80				core1 {
81					cpu = <&a55_1>;
82				};
83			};
84
85			cluster1 {
86				core0 {
87					cpu = <&a55_2>;
88				};
89				core1 {
90					cpu = <&a55_3>;
91				};
92			};
93
94			cluster2 {
95				core0 {
96					cpu = <&a55_4>;
97				};
98				core1 {
99					cpu = <&a55_5>;
100				};
101			};
102
103			cluster3 {
104				core0 {
105					cpu = <&a55_6>;
106				};
107				core1 {
108					cpu = <&a55_7>;
109				};
110			};
111		};
112
113		a55_0: cpu@0 {
114			compatible = "arm,cortex-a55";
115			reg = <0>;
116			device_type = "cpu";
117			power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
118			next-level-cache = <&L3_CA55_0>;
119			enable-method = "psci";
120			cpu-idle-states = <&CPU_SLEEP_0>;
121			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
122			operating-points-v2 = <&cluster01_opp>;
123		};
124
125		a55_1: cpu@100 {
126			compatible = "arm,cortex-a55";
127			reg = <0x100>;
128			device_type = "cpu";
129			power-domains = <&sysc R8A779F0_PD_A1E0D0C1>;
130			next-level-cache = <&L3_CA55_0>;
131			enable-method = "psci";
132			cpu-idle-states = <&CPU_SLEEP_0>;
133			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
134			operating-points-v2 = <&cluster01_opp>;
135		};
136
137		a55_2: cpu@10000 {
138			compatible = "arm,cortex-a55";
139			reg = <0x10000>;
140			device_type = "cpu";
141			power-domains = <&sysc R8A779F0_PD_A1E0D1C0>;
142			next-level-cache = <&L3_CA55_1>;
143			enable-method = "psci";
144			cpu-idle-states = <&CPU_SLEEP_0>;
145			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
146			operating-points-v2 = <&cluster01_opp>;
147		};
148
149		a55_3: cpu@10100 {
150			compatible = "arm,cortex-a55";
151			reg = <0x10100>;
152			device_type = "cpu";
153			power-domains = <&sysc R8A779F0_PD_A1E0D1C1>;
154			next-level-cache = <&L3_CA55_1>;
155			enable-method = "psci";
156			cpu-idle-states = <&CPU_SLEEP_0>;
157			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
158			operating-points-v2 = <&cluster01_opp>;
159		};
160
161		a55_4: cpu@20000 {
162			compatible = "arm,cortex-a55";
163			reg = <0x20000>;
164			device_type = "cpu";
165			power-domains = <&sysc R8A779F0_PD_A1E1D0C0>;
166			next-level-cache = <&L3_CA55_2>;
167			enable-method = "psci";
168			cpu-idle-states = <&CPU_SLEEP_0>;
169			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
170			operating-points-v2 = <&cluster23_opp>;
171		};
172
173		a55_5: cpu@20100 {
174			compatible = "arm,cortex-a55";
175			reg = <0x20100>;
176			device_type = "cpu";
177			power-domains = <&sysc R8A779F0_PD_A1E1D0C1>;
178			next-level-cache = <&L3_CA55_2>;
179			enable-method = "psci";
180			cpu-idle-states = <&CPU_SLEEP_0>;
181			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
182			operating-points-v2 = <&cluster23_opp>;
183		};
184
185		a55_6: cpu@30000 {
186			compatible = "arm,cortex-a55";
187			reg = <0x30000>;
188			device_type = "cpu";
189			power-domains = <&sysc R8A779F0_PD_A1E1D1C0>;
190			next-level-cache = <&L3_CA55_3>;
191			enable-method = "psci";
192			cpu-idle-states = <&CPU_SLEEP_0>;
193			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
194			operating-points-v2 = <&cluster23_opp>;
195		};
196
197		a55_7: cpu@30100 {
198			compatible = "arm,cortex-a55";
199			reg = <0x30100>;
200			device_type = "cpu";
201			power-domains = <&sysc R8A779F0_PD_A1E1D1C1>;
202			next-level-cache = <&L3_CA55_3>;
203			enable-method = "psci";
204			cpu-idle-states = <&CPU_SLEEP_0>;
205			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
206			operating-points-v2 = <&cluster23_opp>;
207		};
208
209		L3_CA55_0: cache-controller-0 {
210			compatible = "cache";
211			power-domains = <&sysc R8A779F0_PD_A2E0D0>;
212			cache-unified;
213			cache-level = <3>;
214		};
215
216		L3_CA55_1: cache-controller-1 {
217			compatible = "cache";
218			power-domains = <&sysc R8A779F0_PD_A2E0D1>;
219			cache-unified;
220			cache-level = <3>;
221		};
222
223		L3_CA55_2: cache-controller-2 {
224			compatible = "cache";
225			power-domains = <&sysc R8A779F0_PD_A2E1D0>;
226			cache-unified;
227			cache-level = <3>;
228		};
229
230		L3_CA55_3: cache-controller-3 {
231			compatible = "cache";
232			power-domains = <&sysc R8A779F0_PD_A2E1D1>;
233			cache-unified;
234			cache-level = <3>;
235		};
236
237		idle-states {
238			entry-method = "psci";
239
240			CPU_SLEEP_0: cpu-sleep-0 {
241				compatible = "arm,idle-state";
242				arm,psci-suspend-param = <0x0010000>;
243				local-timer-stop;
244				entry-latency-us = <400>;
245				exit-latency-us = <500>;
246				min-residency-us = <4000>;
247			};
248		};
249	};
250
251	extal_clk: extal {
252		compatible = "fixed-clock";
253		#clock-cells = <0>;
254		/* This value must be overridden by the board */
255		clock-frequency = <0>;
256	};
257
258	extalr_clk: extalr {
259		compatible = "fixed-clock";
260		#clock-cells = <0>;
261		/* This value must be overridden by the board */
262		clock-frequency = <0>;
263	};
264
265	pmu_a55 {
266		compatible = "arm,cortex-a55-pmu";
267		interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
268	};
269
270	psci {
271		compatible = "arm,psci-1.0", "arm,psci-0.2";
272		method = "smc";
273	};
274
275	/* External SCIF clock - to be overridden by boards that provide it */
276	scif_clk: scif {
277		compatible = "fixed-clock";
278		#clock-cells = <0>;
279		clock-frequency = <0>;
280	};
281
282	soc: soc {
283		compatible = "simple-bus";
284		interrupt-parent = <&gic>;
285		#address-cells = <2>;
286		#size-cells = <2>;
287		ranges;
288
289		rwdt: watchdog@e6020000 {
290			compatible = "renesas,r8a779f0-wdt",
291				     "renesas,rcar-gen4-wdt";
292			reg = <0 0xe6020000 0 0x0c>;
293			interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
294			clocks = <&cpg CPG_MOD 907>;
295			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
296			resets = <&cpg 907>;
297			status = "disabled";
298		};
299
300		pfc: pinctrl@e6050000 {
301			compatible = "renesas,pfc-r8a779f0";
302			reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
303			      <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>;
304		};
305
306		gpio0: gpio@e6050180 {
307			compatible = "renesas,gpio-r8a779f0",
308				     "renesas,rcar-gen4-gpio";
309			reg = <0 0xe6050180 0 0x54>;
310			interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
311			clocks = <&cpg CPG_MOD 915>;
312			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
313			resets = <&cpg 915>;
314			gpio-controller;
315			#gpio-cells = <2>;
316			gpio-ranges = <&pfc 0 0 21>;
317			interrupt-controller;
318			#interrupt-cells = <2>;
319		};
320
321		gpio1: gpio@e6050980 {
322			compatible = "renesas,gpio-r8a779f0",
323				     "renesas,rcar-gen4-gpio";
324			reg = <0 0xe6050980 0 0x54>;
325			interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
326			clocks = <&cpg CPG_MOD 915>;
327			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
328			resets = <&cpg 915>;
329			gpio-controller;
330			#gpio-cells = <2>;
331			gpio-ranges = <&pfc 0 32 25>;
332			interrupt-controller;
333			#interrupt-cells = <2>;
334		};
335
336		gpio2: gpio@e6051180 {
337			compatible = "renesas,gpio-r8a779f0",
338				     "renesas,rcar-gen4-gpio";
339			reg = <0 0xe6051180 0 0x54>;
340			interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
341			clocks = <&cpg CPG_MOD 915>;
342			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
343			resets = <&cpg 915>;
344			gpio-controller;
345			#gpio-cells = <2>;
346			gpio-ranges = <&pfc 0 64 17>;
347			interrupt-controller;
348			#interrupt-cells = <2>;
349		};
350
351		gpio3: gpio@e6051980 {
352			compatible = "renesas,gpio-r8a779f0",
353				     "renesas,rcar-gen4-gpio";
354			reg = <0 0xe6051980 0 0x54>;
355			interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
356			clocks = <&cpg CPG_MOD 915>;
357			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
358			resets = <&cpg 915>;
359			gpio-controller;
360			#gpio-cells = <2>;
361			gpio-ranges = <&pfc 0 96 19>;
362			interrupt-controller;
363			#interrupt-cells = <2>;
364		};
365
366		cmt0: timer@e60f0000 {
367			compatible = "renesas,r8a779f0-cmt0",
368				     "renesas,rcar-gen4-cmt0";
369			reg = <0 0xe60f0000 0 0x1004>;
370			interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
371				     <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
372			clocks = <&cpg CPG_MOD 910>;
373			clock-names = "fck";
374			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
375			resets = <&cpg 910>;
376			status = "disabled";
377		};
378
379		cmt1: timer@e6130000 {
380			compatible = "renesas,r8a779f0-cmt1",
381				     "renesas,rcar-gen4-cmt1";
382			reg = <0 0xe6130000 0 0x1004>;
383			interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
384				     <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
385				     <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
386				     <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
387				     <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
388				     <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
389				     <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
390				     <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
391			clocks = <&cpg CPG_MOD 911>;
392			clock-names = "fck";
393			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
394			resets = <&cpg 911>;
395			status = "disabled";
396		};
397
398		cmt2: timer@e6140000 {
399			compatible = "renesas,r8a779f0-cmt1",
400				     "renesas,rcar-gen4-cmt1";
401			reg = <0 0xe6140000 0 0x1004>;
402			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
403				     <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
404				     <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
405				     <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
406				     <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
407				     <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
408				     <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
409				     <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
410			clocks = <&cpg CPG_MOD 912>;
411			clock-names = "fck";
412			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
413			resets = <&cpg 912>;
414			status = "disabled";
415		};
416
417		cmt3: timer@e6148000 {
418			compatible = "renesas,r8a779f0-cmt1",
419				     "renesas,rcar-gen4-cmt1";
420			reg = <0 0xe6148000 0 0x1004>;
421			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
422				     <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
423				     <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
424				     <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
425				     <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
426				     <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
427				     <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
428				     <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
429			clocks = <&cpg CPG_MOD 913>;
430			clock-names = "fck";
431			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
432			resets = <&cpg 913>;
433			status = "disabled";
434		};
435
436		cpg: clock-controller@e6150000 {
437			compatible = "renesas,r8a779f0-cpg-mssr";
438			reg = <0 0xe6150000 0 0x4000>;
439			clocks = <&extal_clk>, <&extalr_clk>;
440			clock-names = "extal", "extalr";
441			#clock-cells = <2>;
442			#power-domain-cells = <0>;
443			#reset-cells = <1>;
444		};
445
446		rst: reset-controller@e6160000 {
447			compatible = "renesas,r8a779f0-rst";
448			reg = <0 0xe6160000 0 0x4000>;
449		};
450
451		sysc: system-controller@e6180000 {
452			compatible = "renesas,r8a779f0-sysc";
453			reg = <0 0xe6180000 0 0x4000>;
454			#power-domain-cells = <1>;
455		};
456
457		tsc: thermal@e6198000 {
458			compatible = "renesas,r8a779f0-thermal";
459			/* The 4th sensor is in control domain and not for Linux */
460			reg = <0 0xe6198000 0 0x200>,
461			      <0 0xe61a0000 0 0x200>,
462			      <0 0xe61a8000 0 0x200>;
463			clocks = <&cpg CPG_MOD 919>;
464			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
465			resets = <&cpg 919>;
466			#thermal-sensor-cells = <1>;
467		};
468
469		tmu0: timer@e61e0000 {
470			compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
471			reg = <0 0xe61e0000 0 0x30>;
472			interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
473				     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
474				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
475			clocks = <&cpg CPG_MOD 713>;
476			clock-names = "fck";
477			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
478			resets = <&cpg 713>;
479			status = "disabled";
480		};
481
482		tmu1: timer@e6fc0000 {
483			compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
484			reg = <0 0xe6fc0000 0 0x30>;
485			interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
486				     <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
487				     <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
488			clocks = <&cpg CPG_MOD 714>;
489			clock-names = "fck";
490			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
491			resets = <&cpg 714>;
492			status = "disabled";
493		};
494
495		tmu2: timer@e6fd0000 {
496			compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
497			reg = <0 0xe6fd0000 0 0x30>;
498			interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>,
499				     <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>,
500				     <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>;
501			clocks = <&cpg CPG_MOD 715>;
502			clock-names = "fck";
503			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
504			resets = <&cpg 715>;
505			status = "disabled";
506		};
507
508		tmu3: timer@e6fe0000 {
509			compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
510			reg = <0 0xe6fe0000 0 0x30>;
511			interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>,
512				     <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
513				     <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>;
514			clocks = <&cpg CPG_MOD 716>;
515			clock-names = "fck";
516			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
517			resets = <&cpg 716>;
518			status = "disabled";
519		};
520
521		tmu4: timer@ffc00000 {
522			compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
523			reg = <0 0xffc00000 0 0x30>;
524			interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
525				     <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
526				     <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
527			clocks = <&cpg CPG_MOD 717>;
528			clock-names = "fck";
529			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
530			resets = <&cpg 717>;
531			status = "disabled";
532		};
533
534		eth_serdes: phy@e6444000 {
535			compatible = "renesas,r8a779f0-ether-serdes";
536			reg = <0 0xe6444000 0 0x2800>;
537			clocks = <&cpg CPG_MOD 1506>;
538			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
539			resets = <&cpg 1506>;
540			#phy-cells = <1>;
541			status = "disabled";
542		};
543
544		i2c0: i2c@e6500000 {
545			compatible = "renesas,i2c-r8a779f0",
546				     "renesas,rcar-gen4-i2c";
547			reg = <0 0xe6500000 0 0x40>;
548			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
549			clocks = <&cpg CPG_MOD 518>;
550			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
551			resets = <&cpg 518>;
552			dmas = <&dmac0 0x91>, <&dmac0 0x90>,
553			       <&dmac1 0x91>, <&dmac1 0x90>;
554			dma-names = "tx", "rx", "tx", "rx";
555			i2c-scl-internal-delay-ns = <110>;
556			#address-cells = <1>;
557			#size-cells = <0>;
558			status = "disabled";
559		};
560
561		i2c1: i2c@e6508000 {
562			compatible = "renesas,i2c-r8a779f0",
563				     "renesas,rcar-gen4-i2c";
564			reg = <0 0xe6508000 0 0x40>;
565			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
566			clocks = <&cpg CPG_MOD 519>;
567			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
568			resets = <&cpg 519>;
569			dmas = <&dmac0 0x93>, <&dmac0 0x92>,
570			       <&dmac1 0x93>, <&dmac1 0x92>;
571			dma-names = "tx", "rx", "tx", "rx";
572			i2c-scl-internal-delay-ns = <110>;
573			#address-cells = <1>;
574			#size-cells = <0>;
575			status = "disabled";
576		};
577
578		i2c2: i2c@e6510000 {
579			compatible = "renesas,i2c-r8a779f0",
580				     "renesas,rcar-gen4-i2c";
581			reg = <0 0xe6510000 0 0x40>;
582			interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>;
583			clocks = <&cpg CPG_MOD 520>;
584			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
585			resets = <&cpg 520>;
586			dmas = <&dmac0 0x95>, <&dmac0 0x94>,
587			       <&dmac1 0x95>, <&dmac1 0x94>;
588			dma-names = "tx", "rx", "tx", "rx";
589			i2c-scl-internal-delay-ns = <110>;
590			#address-cells = <1>;
591			#size-cells = <0>;
592			status = "disabled";
593		};
594
595		i2c3: i2c@e66d0000 {
596			compatible = "renesas,i2c-r8a779f0",
597				     "renesas,rcar-gen4-i2c";
598			reg = <0 0xe66d0000 0 0x40>;
599			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
600			clocks = <&cpg CPG_MOD 521>;
601			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
602			resets = <&cpg 521>;
603			dmas = <&dmac0 0x97>, <&dmac0 0x96>,
604			       <&dmac1 0x97>, <&dmac1 0x96>;
605			dma-names = "tx", "rx", "tx", "rx";
606			i2c-scl-internal-delay-ns = <110>;
607			#address-cells = <1>;
608			#size-cells = <0>;
609			status = "disabled";
610		};
611
612		i2c4: i2c@e66d8000 {
613			compatible = "renesas,i2c-r8a779f0",
614				     "renesas,rcar-gen4-i2c";
615			reg = <0 0xe66d8000 0 0x40>;
616			interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
617			clocks = <&cpg CPG_MOD 522>;
618			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
619			resets = <&cpg 522>;
620			dmas = <&dmac0 0x99>, <&dmac0 0x98>,
621			       <&dmac1 0x99>, <&dmac1 0x98>;
622			dma-names = "tx", "rx", "tx", "rx";
623			i2c-scl-internal-delay-ns = <110>;
624			#address-cells = <1>;
625			#size-cells = <0>;
626			status = "disabled";
627		};
628
629		i2c5: i2c@e66e0000 {
630			compatible = "renesas,i2c-r8a779f0",
631				     "renesas,rcar-gen4-i2c";
632			reg = <0 0xe66e0000 0 0x40>;
633			interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
634			clocks = <&cpg CPG_MOD 523>;
635			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
636			resets = <&cpg 523>;
637			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
638			       <&dmac1 0x9b>, <&dmac1 0x9a>;
639			dma-names = "tx", "rx", "tx", "rx";
640			i2c-scl-internal-delay-ns = <110>;
641			#address-cells = <1>;
642			#size-cells = <0>;
643			status = "disabled";
644		};
645
646		hscif0: serial@e6540000 {
647			compatible = "renesas,hscif-r8a779f0",
648				     "renesas,rcar-gen4-hscif", "renesas,hscif";
649			reg = <0 0xe6540000 0 0x60>;
650			interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
651			clocks = <&cpg CPG_MOD 514>,
652				 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
653				 <&scif_clk>;
654			clock-names = "fck", "brg_int", "scif_clk";
655			dmas = <&dmac0 0x31>, <&dmac0 0x30>,
656			       <&dmac1 0x31>, <&dmac1 0x30>;
657			dma-names = "tx", "rx", "tx", "rx";
658			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
659			resets = <&cpg 514>;
660			status = "disabled";
661		};
662
663		hscif1: serial@e6550000 {
664			compatible = "renesas,hscif-r8a779f0",
665				     "renesas,rcar-gen4-hscif", "renesas,hscif";
666			reg = <0 0xe6550000 0 0x60>;
667			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
668			clocks = <&cpg CPG_MOD 515>,
669				 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
670				 <&scif_clk>;
671			clock-names = "fck", "brg_int", "scif_clk";
672			dmas = <&dmac0 0x33>, <&dmac0 0x32>,
673			       <&dmac1 0x33>, <&dmac1 0x32>;
674			dma-names = "tx", "rx", "tx", "rx";
675			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
676			resets = <&cpg 515>;
677			status = "disabled";
678		};
679
680		hscif2: serial@e6560000 {
681			compatible = "renesas,hscif-r8a779f0",
682				     "renesas,rcar-gen4-hscif", "renesas,hscif";
683			reg = <0 0xe6560000 0 0x60>;
684			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
685			clocks = <&cpg CPG_MOD 516>,
686				 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
687				 <&scif_clk>;
688			clock-names = "fck", "brg_int", "scif_clk";
689			dmas = <&dmac0 0x35>, <&dmac0 0x34>,
690			       <&dmac1 0x35>, <&dmac1 0x34>;
691			dma-names = "tx", "rx", "tx", "rx";
692			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
693			resets = <&cpg 516>;
694			status = "disabled";
695		};
696
697		hscif3: serial@e66a0000 {
698			compatible = "renesas,hscif-r8a779f0",
699				     "renesas,rcar-gen4-hscif", "renesas,hscif";
700			reg = <0 0xe66a0000 0 0x60>;
701			interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
702			clocks = <&cpg CPG_MOD 517>,
703				 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
704				 <&scif_clk>;
705			clock-names = "fck", "brg_int", "scif_clk";
706			dmas = <&dmac0 0x37>, <&dmac0 0x36>,
707			       <&dmac1 0x37>, <&dmac1 0x36>;
708			dma-names = "tx", "rx", "tx", "rx";
709			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
710			resets = <&cpg 517>;
711			status = "disabled";
712		};
713
714		ufs: ufs@e6860000 {
715			compatible = "renesas,r8a779f0-ufs";
716			reg = <0 0xe6860000 0 0x100>;
717			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
718			clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>;
719			clock-names = "fck", "ref_clk";
720			freq-table-hz = <200000000 200000000>, <38400000 38400000>;
721			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
722			resets = <&cpg 1514>;
723			status = "disabled";
724		};
725
726		rswitch: ethernet@e6880000 {
727			compatible = "renesas,r8a779f0-ether-switch";
728			reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>;
729			reg-names = "base", "secure_base";
730			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
731				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
732				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
733				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
734				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
735				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
736				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
737				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
738				     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
739				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
740				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
741				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
742				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
743				     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
744				     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
745				     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
746				     <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
747				     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
748				     <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
749				     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
750				     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
751				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
752				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
753				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
754				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
755				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
756				     <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
757				     <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
758				     <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
759				     <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
760				     <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
761				     <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
762				     <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
763				     <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
764				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
765				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
766				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
767				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
768				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
769				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
770				     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
771				     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
772				     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
773				     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
774				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
775				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
776				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
777			interrupt-names = "mfwd_error", "race_error",
778					  "coma_error", "gwca0_error",
779					  "gwca1_error", "etha0_error",
780					  "etha1_error", "etha2_error",
781					  "gptp0_status", "gptp1_status",
782					  "mfwd_status", "race_status",
783					  "coma_status", "gwca0_status",
784					  "gwca1_status", "etha0_status",
785					  "etha1_status", "etha2_status",
786					  "rmac0_status", "rmac1_status",
787					  "rmac2_status",
788					  "gwca0_rxtx0", "gwca0_rxtx1",
789					  "gwca0_rxtx2", "gwca0_rxtx3",
790					  "gwca0_rxtx4", "gwca0_rxtx5",
791					  "gwca0_rxtx6", "gwca0_rxtx7",
792					  "gwca1_rxtx0", "gwca1_rxtx1",
793					  "gwca1_rxtx2", "gwca1_rxtx3",
794					  "gwca1_rxtx4", "gwca1_rxtx5",
795					  "gwca1_rxtx6", "gwca1_rxtx7",
796					  "gwca0_rxts0", "gwca0_rxts1",
797					  "gwca1_rxts0", "gwca1_rxts1",
798					  "rmac0_mdio", "rmac1_mdio",
799					  "rmac2_mdio",
800					  "rmac0_phy", "rmac1_phy",
801					  "rmac2_phy";
802			clocks = <&cpg CPG_MOD 1505>;
803			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
804			resets = <&cpg 1505>;
805			status = "disabled";
806
807			ethernet-ports {
808				#address-cells = <1>;
809				#size-cells = <0>;
810
811				port@0 {
812					reg = <0>;
813					phys = <&eth_serdes 0>;
814				};
815				port@1 {
816					reg = <1>;
817					phys = <&eth_serdes 1>;
818				};
819				port@2 {
820					reg = <2>;
821					phys = <&eth_serdes 2>;
822				};
823			};
824		};
825
826		scif0: serial@e6e60000 {
827			compatible = "renesas,scif-r8a779f0",
828				     "renesas,rcar-gen4-scif", "renesas,scif";
829			reg = <0 0xe6e60000 0 64>;
830			interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
831			clocks = <&cpg CPG_MOD 702>,
832				 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
833				 <&scif_clk>;
834			clock-names = "fck", "brg_int", "scif_clk";
835			dmas = <&dmac0 0x51>, <&dmac0 0x50>,
836			       <&dmac1 0x51>, <&dmac1 0x50>;
837			dma-names = "tx", "rx", "tx", "rx";
838			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
839			resets = <&cpg 702>;
840			status = "disabled";
841		};
842
843		scif1: serial@e6e68000 {
844			compatible = "renesas,scif-r8a779f0",
845				     "renesas,rcar-gen4-scif", "renesas,scif";
846			reg = <0 0xe6e68000 0 64>;
847			interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
848			clocks = <&cpg CPG_MOD 703>,
849				 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
850				 <&scif_clk>;
851			clock-names = "fck", "brg_int", "scif_clk";
852			dmas = <&dmac0 0x53>, <&dmac0 0x52>,
853			       <&dmac1 0x53>, <&dmac1 0x52>;
854			dma-names = "tx", "rx", "tx", "rx";
855			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
856			resets = <&cpg 703>;
857			status = "disabled";
858		};
859
860		scif3: serial@e6c50000 {
861			compatible = "renesas,scif-r8a779f0",
862				     "renesas,rcar-gen4-scif", "renesas,scif";
863			reg = <0 0xe6c50000 0 64>;
864			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
865			clocks = <&cpg CPG_MOD 704>,
866				 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
867				 <&scif_clk>;
868			clock-names = "fck", "brg_int", "scif_clk";
869			dmas = <&dmac0 0x57>, <&dmac0 0x56>,
870			       <&dmac1 0x57>, <&dmac1 0x56>;
871			dma-names = "tx", "rx", "tx", "rx";
872			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
873			resets = <&cpg 704>;
874			status = "disabled";
875		};
876
877		scif4: serial@e6c40000 {
878			compatible = "renesas,scif-r8a779f0",
879				     "renesas,rcar-gen4-scif", "renesas,scif";
880			reg = <0 0xe6c40000 0 64>;
881			interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
882			clocks = <&cpg CPG_MOD 705>,
883				 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
884				 <&scif_clk>;
885			clock-names = "fck", "brg_int", "scif_clk";
886			dmas = <&dmac0 0x59>, <&dmac0 0x58>,
887			       <&dmac1 0x59>, <&dmac1 0x58>;
888			dma-names = "tx", "rx", "tx", "rx";
889			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
890			resets = <&cpg 705>;
891			status = "disabled";
892		};
893
894		msiof0: spi@e6e90000 {
895			compatible = "renesas,msiof-r8a779f0",
896				     "renesas,rcar-gen4-msiof";
897			reg = <0 0xe6e90000 0 0x0064>;
898			interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
899			clocks = <&cpg CPG_MOD 618>;
900			dmas = <&dmac0 0x41>, <&dmac0 0x40>,
901			       <&dmac1 0x41>, <&dmac1 0x40>;
902			dma-names = "tx", "rx", "tx", "rx";
903			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
904			resets = <&cpg 618>;
905			#address-cells = <1>;
906			#size-cells = <0>;
907			status = "disabled";
908		};
909
910		msiof1: spi@e6ea0000 {
911			compatible = "renesas,msiof-r8a779f0",
912				     "renesas,rcar-gen4-msiof";
913			reg = <0 0xe6ea0000 0 0x0064>;
914			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
915			clocks = <&cpg CPG_MOD 619>;
916			dmas = <&dmac0 0x43>, <&dmac0 0x42>,
917			       <&dmac1 0x43>, <&dmac1 0x42>;
918			dma-names = "tx", "rx", "tx", "rx";
919			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
920			resets = <&cpg 619>;
921			#address-cells = <1>;
922			#size-cells = <0>;
923			status = "disabled";
924		};
925
926		msiof2: spi@e6c00000 {
927			compatible = "renesas,msiof-r8a779f0",
928				     "renesas,rcar-gen4-msiof";
929			reg = <0 0xe6c00000 0 0x0064>;
930			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
931			clocks = <&cpg CPG_MOD 620>;
932			dmas = <&dmac0 0x45>, <&dmac0 0x44>,
933			       <&dmac1 0x45>, <&dmac1 0x44>;
934			dma-names = "tx", "rx", "tx", "rx";
935			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
936			resets = <&cpg 620>;
937			#address-cells = <1>;
938			#size-cells = <0>;
939			status = "disabled";
940		};
941
942		msiof3: spi@e6c10000 {
943			compatible = "renesas,msiof-r8a779f0",
944				     "renesas,rcar-gen4-msiof";
945			reg = <0 0xe6c10000 0 0x0064>;
946			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
947			clocks = <&cpg CPG_MOD 621>;
948			dmas = <&dmac0 0x47>, <&dmac0 0x46>,
949			       <&dmac1 0x47>, <&dmac1 0x46>;
950			dma-names = "tx", "rx", "tx", "rx";
951			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
952			resets = <&cpg 621>;
953			#address-cells = <1>;
954			#size-cells = <0>;
955			status = "disabled";
956		};
957
958		dmac0: dma-controller@e7350000 {
959			compatible = "renesas,dmac-r8a779f0",
960				     "renesas,rcar-gen4-dmac";
961			reg = <0 0xe7350000 0 0x1000>,
962			      <0 0xe7300000 0 0x10000>;
963			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
964				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
965				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
966				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
967				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
968				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
969				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
970				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
971				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
972				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
973				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
974				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
975				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
976				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
977				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
978				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
979				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
980			interrupt-names = "error",
981					  "ch0", "ch1", "ch2", "ch3", "ch4",
982					  "ch5", "ch6", "ch7", "ch8", "ch9",
983					  "ch10", "ch11", "ch12", "ch13",
984					  "ch14", "ch15";
985			clocks = <&cpg CPG_MOD 709>;
986			clock-names = "fck";
987			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
988			resets = <&cpg 709>;
989			#dma-cells = <1>;
990			dma-channels = <16>;
991			iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
992				 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
993				 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
994				 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
995				 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
996				 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
997				 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
998				 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
999		};
1000
1001		dmac1: dma-controller@e7351000 {
1002			compatible = "renesas,dmac-r8a779f0",
1003				     "renesas,rcar-gen4-dmac";
1004			reg = <0 0xe7351000 0 0x1000>,
1005			      <0 0xe7310000 0 0x10000>;
1006			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1007				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1008				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1009				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1010				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1011				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1012				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1013				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1014				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1015				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1016				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1017				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1018				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1019				     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1020				     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
1021				     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1022				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1023			interrupt-names = "error",
1024					  "ch0", "ch1", "ch2", "ch3", "ch4",
1025					  "ch5", "ch6", "ch7", "ch8", "ch9",
1026					  "ch10", "ch11", "ch12", "ch13",
1027					  "ch14", "ch15";
1028			clocks = <&cpg CPG_MOD 710>;
1029			clock-names = "fck";
1030			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1031			resets = <&cpg 710>;
1032			#dma-cells = <1>;
1033			dma-channels = <16>;
1034			iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
1035				 <&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
1036				 <&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
1037				 <&ipmmu_ds0 22>, <&ipmmu_ds0 23>,
1038				 <&ipmmu_ds0 24>, <&ipmmu_ds0 25>,
1039				 <&ipmmu_ds0 26>, <&ipmmu_ds0 27>,
1040				 <&ipmmu_ds0 28>, <&ipmmu_ds0 29>,
1041				 <&ipmmu_ds0 30>, <&ipmmu_ds0 31>;
1042		};
1043
1044		mmc0: mmc@ee140000 {
1045			compatible = "renesas,sdhi-r8a779f0",
1046				     "renesas,rcar-gen4-sdhi";
1047			reg = <0 0xee140000 0 0x2000>;
1048			interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
1049			clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>;
1050			clock-names = "core", "clkh";
1051			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1052			resets = <&cpg 706>;
1053			max-frequency = <200000000>;
1054			iommus = <&ipmmu_ds0 32>;
1055			status = "disabled";
1056		};
1057
1058		ipmmu_rt0: iommu@ee480000 {
1059			compatible = "renesas,ipmmu-r8a779f0",
1060				     "renesas,rcar-gen4-ipmmu-vmsa";
1061			reg = <0 0xee480000 0 0x20000>;
1062			renesas,ipmmu-main = <&ipmmu_mm 10>;
1063			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1064			#iommu-cells = <1>;
1065		};
1066
1067		ipmmu_rt1: iommu@ee4c0000 {
1068			compatible = "renesas,ipmmu-r8a779f0",
1069				     "renesas,rcar-gen4-ipmmu-vmsa";
1070			reg = <0 0xee4c0000 0 0x20000>;
1071			renesas,ipmmu-main = <&ipmmu_mm 19>;
1072			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1073			#iommu-cells = <1>;
1074		};
1075
1076		ipmmu_ds0: iommu@eed00000 {
1077			compatible = "renesas,ipmmu-r8a779f0",
1078				     "renesas,rcar-gen4-ipmmu-vmsa";
1079			reg = <0 0xeed00000 0 0x20000>;
1080			renesas,ipmmu-main = <&ipmmu_mm 0>;
1081			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1082			#iommu-cells = <1>;
1083		};
1084
1085		ipmmu_hc: iommu@eed40000 {
1086			compatible = "renesas,ipmmu-r8a779f0",
1087				     "renesas,rcar-gen4-ipmmu-vmsa";
1088			reg = <0 0xeed40000 0 0x20000>;
1089			renesas,ipmmu-main = <&ipmmu_mm 2>;
1090			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1091			#iommu-cells = <1>;
1092		};
1093
1094		ipmmu_mm: iommu@eefc0000 {
1095			compatible = "renesas,ipmmu-r8a779f0",
1096				     "renesas,rcar-gen4-ipmmu-vmsa";
1097			reg = <0 0xeefc0000 0 0x20000>;
1098			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
1099				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1100			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1101			#iommu-cells = <1>;
1102		};
1103
1104		gic: interrupt-controller@f1000000 {
1105			compatible = "arm,gic-v3";
1106			#interrupt-cells = <3>;
1107			#address-cells = <0>;
1108			interrupt-controller;
1109			reg = <0x0 0xf1000000 0 0x20000>,
1110			      <0x0 0xf1060000 0 0x110000>;
1111			interrupts = <GIC_PPI 9
1112				      (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1113		};
1114
1115		prr: chipid@fff00044 {
1116			compatible = "renesas,prr";
1117			reg = <0 0xfff00044 0 4>;
1118		};
1119	};
1120
1121	thermal-zones {
1122		sensor_thermal1: sensor1-thermal {
1123			polling-delay-passive = <250>;
1124			polling-delay = <1000>;
1125			thermal-sensors = <&tsc 0>;
1126
1127			trips {
1128				sensor1_crit: sensor1-crit {
1129					temperature = <120000>;
1130					hysteresis = <1000>;
1131					type = "critical";
1132				};
1133			};
1134		};
1135
1136		sensor_thermal2: sensor2-thermal {
1137			polling-delay-passive = <250>;
1138			polling-delay = <1000>;
1139			thermal-sensors = <&tsc 1>;
1140
1141			trips {
1142				sensor2_crit: sensor2-crit {
1143					temperature = <120000>;
1144					hysteresis = <1000>;
1145					type = "critical";
1146				};
1147			};
1148		};
1149
1150		sensor_thermal3: sensor3-thermal {
1151			polling-delay-passive = <250>;
1152			polling-delay = <1000>;
1153			thermal-sensors = <&tsc 2>;
1154
1155			trips {
1156				sensor3_crit: sensor3-crit {
1157					temperature = <120000>;
1158					hysteresis = <1000>;
1159					type = "critical";
1160				};
1161			};
1162		};
1163	};
1164
1165	timer {
1166		compatible = "arm,armv8-timer";
1167		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1168				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1169				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1170				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1171	};
1172
1173	ufs30_clk: ufs30-clk {
1174		compatible = "fixed-clock";
1175		#clock-cells = <0>;
1176		/* This value must be overridden by the board */
1177		clock-frequency = <0>;
1178	};
1179};
1180