1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 dmsc: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x00 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clock-controller { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 mcu_conf: syscon@40f00000 { 38 compatible = "syscon", "simple-mfd"; 39 reg = <0x00 0x40f00000 0x00 0x20000>; 40 #address-cells = <1>; 41 #size-cells = <1>; 42 ranges = <0x00 0x00 0x40f00000 0x20000>; 43 44 phy_gmii_sel: phy@4040 { 45 compatible = "ti,am654-phy-gmii-sel"; 46 reg = <0x4040 0x4>; 47 #phy-cells = <1>; 48 }; 49 }; 50 51 chipid@43000014 { 52 compatible = "ti,am654-chipid"; 53 reg = <0x00 0x43000014 0x00 0x4>; 54 }; 55 56 wkup_pmx0: pinctrl@4301c000 { 57 compatible = "pinctrl-single"; 58 /* Proxy 0 addressing */ 59 reg = <0x00 0x4301c000 0x00 0x34>; 60 #pinctrl-cells = <1>; 61 pinctrl-single,register-width = <32>; 62 pinctrl-single,function-mask = <0xffffffff>; 63 }; 64 65 wkup_pmx1: pinctrl@0x4301c038 { 66 compatible = "pinctrl-single"; 67 /* Proxy 0 addressing */ 68 reg = <0x00 0x4301c038 0x00 0x8>; 69 #pinctrl-cells = <1>; 70 pinctrl-single,register-width = <32>; 71 pinctrl-single,function-mask = <0xffffffff>; 72 }; 73 74 wkup_pmx2: pinctrl@0x4301c068 { 75 compatible = "pinctrl-single"; 76 /* Proxy 0 addressing */ 77 reg = <0x00 0x4301c068 0x00 0xec>; 78 #pinctrl-cells = <1>; 79 pinctrl-single,register-width = <32>; 80 pinctrl-single,function-mask = <0xffffffff>; 81 }; 82 83 wkup_pmx3: pinctrl@0x4301c174 { 84 compatible = "pinctrl-single"; 85 /* Proxy 0 addressing */ 86 reg = <0x00 0x4301c174 0x00 0x20>; 87 #pinctrl-cells = <1>; 88 pinctrl-single,register-width = <32>; 89 pinctrl-single,function-mask = <0xffffffff>; 90 }; 91 92 mcu_ram: sram@41c00000 { 93 compatible = "mmio-sram"; 94 reg = <0x00 0x41c00000 0x00 0x100000>; 95 ranges = <0x00 0x00 0x41c00000 0x100000>; 96 #address-cells = <1>; 97 #size-cells = <1>; 98 }; 99 100 wkup_uart0: serial@42300000 { 101 compatible = "ti,j721e-uart", "ti,am654-uart"; 102 reg = <0x00 0x42300000 0x00 0x100>; 103 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 104 clock-frequency = <48000000>; 105 current-speed = <115200>; 106 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 107 clocks = <&k3_clks 287 2>; 108 clock-names = "fclk"; 109 status = "disabled"; 110 }; 111 112 mcu_uart0: serial@40a00000 { 113 compatible = "ti,j721e-uart", "ti,am654-uart"; 114 reg = <0x00 0x40a00000 0x00 0x100>; 115 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 116 clock-frequency = <96000000>; 117 current-speed = <115200>; 118 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 119 clocks = <&k3_clks 149 2>; 120 clock-names = "fclk"; 121 status = "disabled"; 122 }; 123 124 wkup_gpio_intr: interrupt-controller@42200000 { 125 compatible = "ti,sci-intr"; 126 reg = <0x00 0x42200000 0x00 0x400>; 127 ti,intr-trigger-type = <1>; 128 interrupt-controller; 129 interrupt-parent = <&gic500>; 130 #interrupt-cells = <1>; 131 ti,sci = <&dmsc>; 132 ti,sci-dev-id = <137>; 133 ti,interrupt-ranges = <16 960 16>; 134 }; 135 136 wkup_gpio0: gpio@42110000 { 137 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 138 reg = <0x00 0x42110000 0x00 0x100>; 139 gpio-controller; 140 #gpio-cells = <2>; 141 interrupt-parent = <&wkup_gpio_intr>; 142 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 143 interrupt-controller; 144 #interrupt-cells = <2>; 145 ti,ngpio = <85>; 146 ti,davinci-gpio-unbanked = <0>; 147 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 148 clocks = <&k3_clks 113 0>; 149 clock-names = "gpio"; 150 }; 151 152 wkup_gpio1: gpio@42100000 { 153 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 154 reg = <0x00 0x42100000 0x00 0x100>; 155 gpio-controller; 156 #gpio-cells = <2>; 157 interrupt-parent = <&wkup_gpio_intr>; 158 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 159 interrupt-controller; 160 #interrupt-cells = <2>; 161 ti,ngpio = <85>; 162 ti,davinci-gpio-unbanked = <0>; 163 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 164 clocks = <&k3_clks 114 0>; 165 clock-names = "gpio"; 166 }; 167 168 mcu_navss: bus@28380000 { 169 compatible = "simple-mfd"; 170 #address-cells = <2>; 171 #size-cells = <2>; 172 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 173 dma-coherent; 174 dma-ranges; 175 ti,sci-dev-id = <232>; 176 177 mcu_ringacc: ringacc@2b800000 { 178 compatible = "ti,am654-navss-ringacc"; 179 reg = <0x00 0x2b800000 0x00 0x400000>, 180 <0x00 0x2b000000 0x00 0x400000>, 181 <0x00 0x28590000 0x00 0x100>, 182 <0x00 0x2a500000 0x00 0x40000>; 183 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 184 ti,num-rings = <286>; 185 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 186 ti,sci = <&dmsc>; 187 ti,sci-dev-id = <235>; 188 msi-parent = <&main_udmass_inta>; 189 }; 190 191 mcu_udmap: dma-controller@285c0000 { 192 compatible = "ti,j721e-navss-mcu-udmap"; 193 reg = <0x00 0x285c0000 0x00 0x100>, 194 <0x00 0x2a800000 0x00 0x40000>, 195 <0x00 0x2aa00000 0x00 0x40000>; 196 reg-names = "gcfg", "rchanrt", "tchanrt"; 197 msi-parent = <&main_udmass_inta>; 198 #dma-cells = <1>; 199 200 ti,sci = <&dmsc>; 201 ti,sci-dev-id = <236>; 202 ti,ringacc = <&mcu_ringacc>; 203 204 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 205 <0x0f>; /* TX_HCHAN */ 206 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 207 <0x0b>; /* RX_HCHAN */ 208 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 209 }; 210 }; 211 212 mcu_cpsw: ethernet@46000000 { 213 compatible = "ti,j721e-cpsw-nuss"; 214 #address-cells = <2>; 215 #size-cells = <2>; 216 reg = <0x00 0x46000000 0x00 0x200000>; 217 reg-names = "cpsw_nuss"; 218 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; 219 dma-coherent; 220 clocks = <&k3_clks 18 21>; 221 clock-names = "fck"; 222 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; 223 224 dmas = <&mcu_udmap 0xf000>, 225 <&mcu_udmap 0xf001>, 226 <&mcu_udmap 0xf002>, 227 <&mcu_udmap 0xf003>, 228 <&mcu_udmap 0xf004>, 229 <&mcu_udmap 0xf005>, 230 <&mcu_udmap 0xf006>, 231 <&mcu_udmap 0xf007>, 232 <&mcu_udmap 0x7000>; 233 dma-names = "tx0", "tx1", "tx2", "tx3", 234 "tx4", "tx5", "tx6", "tx7", 235 "rx"; 236 237 ethernet-ports { 238 #address-cells = <1>; 239 #size-cells = <0>; 240 241 cpsw_port1: port@1 { 242 reg = <1>; 243 ti,mac-only; 244 label = "port1"; 245 ti,syscon-efuse = <&mcu_conf 0x200>; 246 phys = <&phy_gmii_sel 1>; 247 }; 248 }; 249 250 davinci_mdio: mdio@f00 { 251 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 252 reg = <0x00 0xf00 0x00 0x100>; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 clocks = <&k3_clks 18 21>; 256 clock-names = "fck"; 257 bus_freq = <1000000>; 258 }; 259 260 cpts@3d000 { 261 compatible = "ti,am65-cpts"; 262 reg = <0x00 0x3d000 0x00 0x400>; 263 clocks = <&k3_clks 18 2>; 264 clock-names = "cpts"; 265 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 266 interrupt-names = "cpts"; 267 ti,cpts-ext-ts-inputs = <4>; 268 ti,cpts-periodic-outputs = <2>; 269 }; 270 }; 271 272 mcu_i2c0: i2c@40b00000 { 273 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 274 reg = <0x00 0x40b00000 0x00 0x100>; 275 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 clock-names = "fck"; 279 clocks = <&k3_clks 194 1>; 280 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 281 status = "disabled"; 282 }; 283 284 mcu_i2c1: i2c@40b10000 { 285 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 286 reg = <0x00 0x40b10000 0x00 0x100>; 287 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 clock-names = "fck"; 291 clocks = <&k3_clks 195 1>; 292 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 293 status = "disabled"; 294 }; 295 296 wkup_i2c0: i2c@42120000 { 297 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 298 reg = <0x00 0x42120000 0x00 0x100>; 299 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 clock-names = "fck"; 303 clocks = <&k3_clks 197 1>; 304 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 305 status = "disabled"; 306 }; 307 308 fss: syscon@47000000 { 309 compatible = "syscon", "simple-mfd"; 310 reg = <0x00 0x47000000 0x00 0x100>; 311 #address-cells = <2>; 312 #size-cells = <2>; 313 ranges; 314 315 hbmc_mux: hbmc-mux { 316 compatible = "mmio-mux"; 317 #mux-control-cells = <1>; 318 mux-reg-masks = <0x4 0x2>; /* HBMC select */ 319 }; 320 321 hbmc: hyperbus@47034000 { 322 compatible = "ti,am654-hbmc"; 323 reg = <0x00 0x47034000 0x00 0x100>, 324 <0x05 0x00000000 0x01 0x0000000>; 325 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 326 clocks = <&k3_clks 102 0>; 327 assigned-clocks = <&k3_clks 102 5>; 328 assigned-clock-rates = <333333333>; 329 #address-cells = <2>; 330 #size-cells = <1>; 331 mux-controls = <&hbmc_mux 0>; 332 }; 333 334 ospi0: spi@47040000 { 335 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 336 reg = <0x0 0x47040000 0x0 0x100>, 337 <0x5 0x00000000 0x1 0x0000000>; 338 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 339 cdns,fifo-depth = <256>; 340 cdns,fifo-width = <4>; 341 cdns,trigger-address = <0x0>; 342 clocks = <&k3_clks 103 0>; 343 assigned-clocks = <&k3_clks 103 0>; 344 assigned-clock-parents = <&k3_clks 103 2>; 345 assigned-clock-rates = <166666666>; 346 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 }; 350 }; 351 352 tscadc0: tscadc@40200000 { 353 compatible = "ti,am3359-tscadc"; 354 reg = <0x00 0x40200000 0x00 0x1000>; 355 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 356 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 357 clocks = <&k3_clks 0 1>; 358 assigned-clocks = <&k3_clks 0 3>; 359 assigned-clock-rates = <60000000>; 360 clock-names = "fck"; 361 dmas = <&main_udmap 0x7400>, 362 <&main_udmap 0x7401>; 363 dma-names = "fifo0", "fifo1"; 364 365 adc { 366 #io-channel-cells = <1>; 367 compatible = "ti,am3359-adc"; 368 }; 369 }; 370 371 mcu_r5fss0: r5fss@41000000 { 372 compatible = "ti,j7200-r5fss"; 373 ti,cluster-mode = <1>; 374 #address-cells = <1>; 375 #size-cells = <1>; 376 ranges = <0x41000000 0x00 0x41000000 0x20000>, 377 <0x41400000 0x00 0x41400000 0x20000>; 378 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 379 380 mcu_r5fss0_core0: r5f@41000000 { 381 compatible = "ti,j7200-r5f"; 382 reg = <0x41000000 0x00010000>, 383 <0x41010000 0x00010000>; 384 reg-names = "atcm", "btcm"; 385 ti,sci = <&dmsc>; 386 ti,sci-dev-id = <250>; 387 ti,sci-proc-ids = <0x01 0xff>; 388 resets = <&k3_reset 250 1>; 389 firmware-name = "j7200-mcu-r5f0_0-fw"; 390 ti,atcm-enable = <1>; 391 ti,btcm-enable = <1>; 392 ti,loczrama = <1>; 393 }; 394 395 mcu_r5fss0_core1: r5f@41400000 { 396 compatible = "ti,j7200-r5f"; 397 reg = <0x41400000 0x00008000>, 398 <0x41410000 0x00008000>; 399 reg-names = "atcm", "btcm"; 400 ti,sci = <&dmsc>; 401 ti,sci-dev-id = <251>; 402 ti,sci-proc-ids = <0x02 0xff>; 403 resets = <&k3_reset 251 1>; 404 firmware-name = "j7200-mcu-r5f0_1-fw"; 405 ti,atcm-enable = <1>; 406 ti,btcm-enable = <1>; 407 ti,loczrama = <1>; 408 }; 409 }; 410 411 mcu_crypto: crypto@40900000 { 412 compatible = "ti,j721e-sa2ul"; 413 reg = <0x00 0x40900000 0x00 0x1200>; 414 power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>; 415 #address-cells = <2>; 416 #size-cells = <2>; 417 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 418 dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>, 419 <&mcu_udmap 0x7503>; 420 dma-names = "tx", "rx1", "rx2"; 421 422 rng: rng@40910000 { 423 compatible = "inside-secure,safexcel-eip76"; 424 reg = <0x00 0x40910000 0x00 0x7d>; 425 interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>; 426 status = "disabled"; /* Used by OP-TEE */ 427 }; 428 }; 429}; 430