1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2017 - Columbia University and Linaro Ltd.
4 * Author: Jintack Lim <jintack.lim@linaro.org>
5 */
6
7 #include <linux/kvm.h>
8 #include <linux/kvm_host.h>
9
10 #include <asm/kvm_emulate.h>
11 #include <asm/kvm_nested.h>
12 #include <asm/sysreg.h>
13
14 #include "sys_regs.h"
15
16 /* Protection against the sysreg repainting madness... */
17 #define NV_FTR(r, f) ID_AA64##r##_EL1_##f
18
19 /*
20 * Our emulated CPU doesn't support all the possible features. For the
21 * sake of simplicity (and probably mental sanity), wipe out a number
22 * of feature bits we don't intend to support for the time being.
23 * This list should get updated as new features get added to the NV
24 * support, and new extension to the architecture.
25 */
access_nested_id_reg(struct kvm_vcpu * v,struct sys_reg_params * p,const struct sys_reg_desc * r)26 void access_nested_id_reg(struct kvm_vcpu *v, struct sys_reg_params *p,
27 const struct sys_reg_desc *r)
28 {
29 u32 id = reg_to_encoding(r);
30 u64 val, tmp;
31
32 val = p->regval;
33
34 switch (id) {
35 case SYS_ID_AA64ISAR0_EL1:
36 /* Support everything but TME, O.S. and Range TLBIs */
37 val &= ~(NV_FTR(ISAR0, TLB) |
38 NV_FTR(ISAR0, TME));
39 break;
40
41 case SYS_ID_AA64ISAR1_EL1:
42 /* Support everything but PtrAuth and Spec Invalidation */
43 val &= ~(GENMASK_ULL(63, 56) |
44 NV_FTR(ISAR1, SPECRES) |
45 NV_FTR(ISAR1, GPI) |
46 NV_FTR(ISAR1, GPA) |
47 NV_FTR(ISAR1, API) |
48 NV_FTR(ISAR1, APA));
49 break;
50
51 case SYS_ID_AA64PFR0_EL1:
52 /* No AMU, MPAM, S-EL2, RAS or SVE */
53 val &= ~(GENMASK_ULL(55, 52) |
54 NV_FTR(PFR0, AMU) |
55 NV_FTR(PFR0, MPAM) |
56 NV_FTR(PFR0, SEL2) |
57 NV_FTR(PFR0, RAS) |
58 NV_FTR(PFR0, SVE) |
59 NV_FTR(PFR0, EL3) |
60 NV_FTR(PFR0, EL2) |
61 NV_FTR(PFR0, EL1));
62 /* 64bit EL1/EL2/EL3 only */
63 val |= FIELD_PREP(NV_FTR(PFR0, EL1), 0b0001);
64 val |= FIELD_PREP(NV_FTR(PFR0, EL2), 0b0001);
65 val |= FIELD_PREP(NV_FTR(PFR0, EL3), 0b0001);
66 break;
67
68 case SYS_ID_AA64PFR1_EL1:
69 /* Only support SSBS */
70 val &= NV_FTR(PFR1, SSBS);
71 break;
72
73 case SYS_ID_AA64MMFR0_EL1:
74 /* Hide ECV, FGT, ExS, Secure Memory */
75 val &= ~(GENMASK_ULL(63, 43) |
76 NV_FTR(MMFR0, TGRAN4_2) |
77 NV_FTR(MMFR0, TGRAN16_2) |
78 NV_FTR(MMFR0, TGRAN64_2) |
79 NV_FTR(MMFR0, SNSMEM));
80
81 /* Disallow unsupported S2 page sizes */
82 switch (PAGE_SIZE) {
83 case SZ_64K:
84 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN16_2), 0b0001);
85 fallthrough;
86 case SZ_16K:
87 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN4_2), 0b0001);
88 fallthrough;
89 case SZ_4K:
90 /* Support everything */
91 break;
92 }
93 /*
94 * Since we can't support a guest S2 page size smaller than
95 * the host's own page size (due to KVM only populating its
96 * own S2 using the kernel's page size), advertise the
97 * limitation using FEAT_GTG.
98 */
99 switch (PAGE_SIZE) {
100 case SZ_4K:
101 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN4_2), 0b0010);
102 fallthrough;
103 case SZ_16K:
104 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN16_2), 0b0010);
105 fallthrough;
106 case SZ_64K:
107 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN64_2), 0b0010);
108 break;
109 }
110 /* Cap PARange to 48bits */
111 tmp = FIELD_GET(NV_FTR(MMFR0, PARANGE), val);
112 if (tmp > 0b0101) {
113 val &= ~NV_FTR(MMFR0, PARANGE);
114 val |= FIELD_PREP(NV_FTR(MMFR0, PARANGE), 0b0101);
115 }
116 break;
117
118 case SYS_ID_AA64MMFR1_EL1:
119 val &= (NV_FTR(MMFR1, PAN) |
120 NV_FTR(MMFR1, LO) |
121 NV_FTR(MMFR1, HPDS) |
122 NV_FTR(MMFR1, VH) |
123 NV_FTR(MMFR1, VMIDBits));
124 break;
125
126 case SYS_ID_AA64MMFR2_EL1:
127 val &= ~(NV_FTR(MMFR2, EVT) |
128 NV_FTR(MMFR2, BBM) |
129 NV_FTR(MMFR2, TTL) |
130 GENMASK_ULL(47, 44) |
131 NV_FTR(MMFR2, ST) |
132 NV_FTR(MMFR2, CCIDX) |
133 NV_FTR(MMFR2, VARange));
134
135 /* Force TTL support */
136 val |= FIELD_PREP(NV_FTR(MMFR2, TTL), 0b0001);
137 break;
138
139 case SYS_ID_AA64DFR0_EL1:
140 /* Only limited support for PMU, Debug, BPs and WPs */
141 val &= (NV_FTR(DFR0, PMUVer) |
142 NV_FTR(DFR0, WRPs) |
143 NV_FTR(DFR0, BRPs) |
144 NV_FTR(DFR0, DebugVer));
145
146 /* Cap Debug to ARMv8.1 */
147 tmp = FIELD_GET(NV_FTR(DFR0, DebugVer), val);
148 if (tmp > 0b0111) {
149 val &= ~NV_FTR(DFR0, DebugVer);
150 val |= FIELD_PREP(NV_FTR(DFR0, DebugVer), 0b0111);
151 }
152 break;
153
154 default:
155 /* Unknown register, just wipe it clean */
156 val = 0;
157 break;
158 }
159
160 p->regval = val;
161 }
162