1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012 ARM Ltd.
4 * Author: Catalin Marinas <catalin.marinas@arm.com>
5 */
6
7 #include <linux/gfp.h>
8 #include <linux/cache.h>
9 #include <linux/dma-map-ops.h>
10 #include <linux/iommu.h>
11 #include <xen/xen.h>
12
13 #include <asm/cacheflush.h>
14 #include <asm/xen/xen-ops.h>
15
arch_sync_dma_for_device(phys_addr_t paddr,size_t size,enum dma_data_direction dir)16 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
17 enum dma_data_direction dir)
18 {
19 unsigned long start = (unsigned long)phys_to_virt(paddr);
20
21 dcache_clean_poc(start, start + size);
22 }
23
arch_sync_dma_for_cpu(phys_addr_t paddr,size_t size,enum dma_data_direction dir)24 void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
25 enum dma_data_direction dir)
26 {
27 unsigned long start = (unsigned long)phys_to_virt(paddr);
28
29 if (dir == DMA_TO_DEVICE)
30 return;
31
32 dcache_inval_poc(start, start + size);
33 }
34
arch_dma_prep_coherent(struct page * page,size_t size)35 void arch_dma_prep_coherent(struct page *page, size_t size)
36 {
37 unsigned long start = (unsigned long)page_address(page);
38
39 /*
40 * The architecture only requires a clean to the PoC here in order to
41 * meet the requirements of the DMA API. However, some vendors (i.e.
42 * Qualcomm) abuse the DMA API for transferring buffers from the
43 * non-secure to the secure world, resetting the system if a non-secure
44 * access shows up after the buffer has been transferred:
45 *
46 * https://lore.kernel.org/r/20221114110329.68413-1-manivannan.sadhasivam@linaro.org
47 *
48 * Using clean+invalidate appears to make this issue less likely, but
49 * the drivers themselves still need fixing as the CPU could issue a
50 * speculative read from the buffer via the linear mapping irrespective
51 * of the cache maintenance we use. Once the drivers are fixed, we can
52 * relax this to a clean operation.
53 */
54 dcache_clean_inval_poc(start, start + size);
55 }
56
57 #ifdef CONFIG_IOMMU_DMA
arch_teardown_dma_ops(struct device * dev)58 void arch_teardown_dma_ops(struct device *dev)
59 {
60 dev->dma_ops = NULL;
61 }
62 #endif
63
arch_setup_dma_ops(struct device * dev,u64 dma_base,u64 size,const struct iommu_ops * iommu,bool coherent)64 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
65 const struct iommu_ops *iommu, bool coherent)
66 {
67 int cls = cache_line_size_of_cpu();
68
69 WARN_TAINT(!coherent && cls > ARCH_DMA_MINALIGN,
70 TAINT_CPU_OUT_OF_SPEC,
71 "%s %s: ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)",
72 dev_driver_string(dev), dev_name(dev),
73 ARCH_DMA_MINALIGN, cls);
74
75 dev->dma_coherent = coherent;
76 if (iommu)
77 iommu_setup_dma_ops(dev, dma_base, dma_base + size - 1);
78
79 xen_setup_dma_ops(dev);
80 }
81