1 /* SPDX-License-Identifier: GPL-2.0 */
2 /****************************************************************************/
3 
4 /*
5  *	mcfpit.h -- ColdFire internal PIT timer support defines.
6  *
7  *	(C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
8  */
9 
10 /****************************************************************************/
11 #ifndef	mcfpit_h
12 #define	mcfpit_h
13 /****************************************************************************/
14 
15 /*
16  *	Define the PIT timer register address offsets.
17  */
18 #define	MCFPIT_PCSR		0x0		/* PIT control register */
19 #define	MCFPIT_PMR		0x2		/* PIT modulus register */
20 #define	MCFPIT_PCNTR		0x4		/* PIT count register */
21 
22 /*
23  *	Bit definitions for the PIT Control and Status register.
24  */
25 #define	MCFPIT_PCSR_CLK1	0x0000		/* System clock divisor */
26 #define	MCFPIT_PCSR_CLK2	0x0100		/* System clock divisor */
27 #define	MCFPIT_PCSR_CLK4	0x0200		/* System clock divisor */
28 #define	MCFPIT_PCSR_CLK8	0x0300		/* System clock divisor */
29 #define	MCFPIT_PCSR_CLK16	0x0400		/* System clock divisor */
30 #define	MCFPIT_PCSR_CLK32	0x0500		/* System clock divisor */
31 #define	MCFPIT_PCSR_CLK64	0x0600		/* System clock divisor */
32 #define	MCFPIT_PCSR_CLK128	0x0700		/* System clock divisor */
33 #define	MCFPIT_PCSR_CLK256	0x0800		/* System clock divisor */
34 #define	MCFPIT_PCSR_CLK512	0x0900		/* System clock divisor */
35 #define	MCFPIT_PCSR_CLK1024	0x0a00		/* System clock divisor */
36 #define	MCFPIT_PCSR_CLK2048	0x0b00		/* System clock divisor */
37 #define	MCFPIT_PCSR_CLK4096	0x0c00		/* System clock divisor */
38 #define	MCFPIT_PCSR_CLK8192	0x0d00		/* System clock divisor */
39 #define	MCFPIT_PCSR_CLK16384	0x0e00		/* System clock divisor */
40 #define	MCFPIT_PCSR_CLK32768	0x0f00		/* System clock divisor */
41 #define	MCFPIT_PCSR_DOZE	0x0040		/* Clock run in doze mode */
42 #define	MCFPIT_PCSR_HALTED	0x0020		/* Clock run in halt mode */
43 #define	MCFPIT_PCSR_OVW		0x0010		/* Overwrite PIT counter now */
44 #define	MCFPIT_PCSR_PIE		0x0008		/* Enable PIT interrupt */
45 #define	MCFPIT_PCSR_PIF		0x0004		/* PIT interrupt flag */
46 #define	MCFPIT_PCSR_RLD		0x0002		/* Reload counter */
47 #define	MCFPIT_PCSR_EN		0x0001		/* Enable PIT */
48 #define	MCFPIT_PCSR_DISABLE	0x0000		/* Disable PIT */
49 
50 /****************************************************************************/
51 #endif	/* mcfpit_h */
52