1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *
4  *  Copyright (C) 2010 John Crispin <john@phrozen.org>
5  *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
6  */
7 
8 #include <linux/export.h>
9 #include <linux/clk.h>
10 #include <asm/bootinfo.h>
11 #include <asm/time.h>
12 
13 #include <lantiq_soc.h>
14 
15 #include "../prom.h"
16 
17 #define SOC_DANUBE	"Danube"
18 #define SOC_TWINPASS	"Twinpass"
19 #define SOC_AMAZON_SE	"Amazon_SE"
20 #define SOC_AR9		"AR9"
21 #define SOC_GR9		"GRX200"
22 #define SOC_VR9		"xRX200"
23 #define SOC_VRX220	"xRX220"
24 #define SOC_AR10	"xRX300"
25 #define SOC_GRX390	"xRX330"
26 
27 #define COMP_DANUBE	"lantiq,danube"
28 #define COMP_TWINPASS	"lantiq,twinpass"
29 #define COMP_AMAZON_SE	"lantiq,ase"
30 #define COMP_AR9	"lantiq,ar9"
31 #define COMP_GR9	"lantiq,gr9"
32 #define COMP_VR9	"lantiq,vr9"
33 #define COMP_AR10	"lantiq,ar10"
34 #define COMP_GRX390	"lantiq,grx390"
35 
36 #define PART_SHIFT	12
37 #define PART_MASK	0x0FFFFFFF
38 #define REV_SHIFT	28
39 #define REV_MASK	0xF0000000
40 
ltq_soc_detect(struct ltq_soc_info * i)41 void __init ltq_soc_detect(struct ltq_soc_info *i)
42 {
43 	i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
44 	i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
45 	sprintf(i->rev_type, "1.%d", i->rev);
46 	switch (i->partnum) {
47 	case SOC_ID_DANUBE1:
48 	case SOC_ID_DANUBE2:
49 		i->name = SOC_DANUBE;
50 		i->type = SOC_TYPE_DANUBE;
51 		i->compatible = COMP_DANUBE;
52 		break;
53 
54 	case SOC_ID_TWINPASS:
55 		i->name = SOC_TWINPASS;
56 		i->type = SOC_TYPE_DANUBE;
57 		i->compatible = COMP_TWINPASS;
58 		break;
59 
60 	case SOC_ID_ARX188:
61 	case SOC_ID_ARX168_1:
62 	case SOC_ID_ARX168_2:
63 	case SOC_ID_ARX182:
64 		i->name = SOC_AR9;
65 		i->type = SOC_TYPE_AR9;
66 		i->compatible = COMP_AR9;
67 		break;
68 
69 	case SOC_ID_GRX188:
70 	case SOC_ID_GRX168:
71 		i->name = SOC_GR9;
72 		i->type = SOC_TYPE_AR9;
73 		i->compatible = COMP_GR9;
74 		break;
75 
76 	case SOC_ID_AMAZON_SE_1:
77 	case SOC_ID_AMAZON_SE_2:
78 #ifdef CONFIG_PCI
79 		panic("ase is only supported for non pci kernels");
80 #endif
81 		i->name = SOC_AMAZON_SE;
82 		i->type = SOC_TYPE_AMAZON_SE;
83 		i->compatible = COMP_AMAZON_SE;
84 		break;
85 
86 	case SOC_ID_VRX282:
87 	case SOC_ID_VRX268:
88 	case SOC_ID_VRX288:
89 		i->name = SOC_VR9;
90 		i->type = SOC_TYPE_VR9;
91 		i->compatible = COMP_VR9;
92 		break;
93 
94 	case SOC_ID_GRX268:
95 	case SOC_ID_GRX288:
96 		i->name = SOC_GR9;
97 		i->type = SOC_TYPE_VR9;
98 		i->compatible = COMP_GR9;
99 		break;
100 
101 	case SOC_ID_VRX268_2:
102 	case SOC_ID_VRX288_2:
103 		i->name = SOC_VR9;
104 		i->type = SOC_TYPE_VR9_2;
105 		i->compatible = COMP_VR9;
106 		break;
107 
108 	case SOC_ID_VRX220:
109 		i->name = SOC_VRX220;
110 		i->type = SOC_TYPE_VRX220;
111 		i->compatible = COMP_VR9;
112 		break;
113 
114 	case SOC_ID_GRX282_2:
115 	case SOC_ID_GRX288_2:
116 		i->name = SOC_GR9;
117 		i->type = SOC_TYPE_VR9_2;
118 		i->compatible = COMP_GR9;
119 		break;
120 
121 	case SOC_ID_ARX362:
122 	case SOC_ID_ARX368:
123 	case SOC_ID_ARX382:
124 	case SOC_ID_ARX388:
125 	case SOC_ID_URX388:
126 		i->name = SOC_AR10;
127 		i->type = SOC_TYPE_AR10;
128 		i->compatible = COMP_AR10;
129 		break;
130 
131 	case SOC_ID_GRX383:
132 	case SOC_ID_GRX369:
133 	case SOC_ID_GRX387:
134 	case SOC_ID_GRX389:
135 		i->name = SOC_GRX390;
136 		i->type = SOC_TYPE_GRX390;
137 		i->compatible = COMP_GRX390;
138 		break;
139 
140 	default:
141 		unreachable();
142 		break;
143 	}
144 }
145