1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * OpenRISC time.c
4  *
5  * Linux architectural port borrowing liberally from similar works of
6  * others.  All original copyrights apply as per the original source
7  * declaration.
8  *
9  * Modifications for the OpenRISC architecture:
10  * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11  */
12 
13 #include <linux/kernel.h>
14 #include <linux/time.h>
15 #include <linux/timex.h>
16 #include <linux/interrupt.h>
17 #include <linux/ftrace.h>
18 
19 #include <linux/clocksource.h>
20 #include <linux/clockchips.h>
21 #include <linux/irq.h>
22 #include <linux/io.h>
23 #include <linux/of_clk.h>
24 
25 #include <asm/cpuinfo.h>
26 #include <asm/time.h>
27 
28 /* Test the timer ticks to count, used in sync routine */
openrisc_timer_set(unsigned long count)29 inline void openrisc_timer_set(unsigned long count)
30 {
31 	mtspr(SPR_TTCR, count);
32 }
33 
34 /* Set the timer to trigger in delta cycles */
openrisc_timer_set_next(unsigned long delta)35 inline void openrisc_timer_set_next(unsigned long delta)
36 {
37 	u32 c;
38 
39 	/* Read 32-bit counter value, add delta, mask off the low 28 bits.
40 	 * We're guaranteed delta won't be bigger than 28 bits because the
41 	 * generic timekeeping code ensures that for us.
42 	 */
43 	c = mfspr(SPR_TTCR);
44 	c += delta;
45 	c &= SPR_TTMR_TP;
46 
47 	/* Set counter and enable interrupt.
48 	 * Keep timer in continuous mode always.
49 	 */
50 	mtspr(SPR_TTMR, SPR_TTMR_CR | SPR_TTMR_IE | c);
51 }
52 
openrisc_timer_set_next_event(unsigned long delta,struct clock_event_device * dev)53 static int openrisc_timer_set_next_event(unsigned long delta,
54 					 struct clock_event_device *dev)
55 {
56 	openrisc_timer_set_next(delta);
57 	return 0;
58 }
59 
60 /* This is the clock event device based on the OR1K tick timer.
61  * As the timer is being used as a continuous clock-source (required for HR
62  * timers) we cannot enable the PERIODIC feature.  The tick timer can run using
63  * one-shot events, so no problem.
64  */
65 static DEFINE_PER_CPU(struct clock_event_device, clockevent_openrisc_timer);
66 
openrisc_clockevent_init(void)67 void openrisc_clockevent_init(void)
68 {
69 	unsigned int cpu = smp_processor_id();
70 	struct clock_event_device *evt =
71 		&per_cpu(clockevent_openrisc_timer, cpu);
72 	struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu];
73 
74 	mtspr(SPR_TTMR, SPR_TTMR_CR);
75 
76 #ifdef CONFIG_SMP
77 	evt->broadcast = tick_broadcast;
78 #endif
79 	evt->name = "openrisc_timer_clockevent",
80 	evt->features = CLOCK_EVT_FEAT_ONESHOT,
81 	evt->rating = 300,
82 	evt->set_next_event = openrisc_timer_set_next_event,
83 
84 	evt->cpumask = cpumask_of(cpu);
85 
86 	/* We only have 28 bits */
87 	clockevents_config_and_register(evt, cpuinfo->clock_frequency,
88 					100, 0x0fffffff);
89 
90 }
91 
timer_ack(void)92 static inline void timer_ack(void)
93 {
94 	/* Clear the IP bit and disable further interrupts */
95 	/* This can be done very simply... we just need to keep the timer
96 	   running, so just maintain the CR bits while clearing the rest
97 	   of the register
98 	 */
99 	mtspr(SPR_TTMR, SPR_TTMR_CR);
100 }
101 
102 /*
103  * The timer interrupt is mostly handled in generic code nowadays... this
104  * function just acknowledges the interrupt and fires the event handler that
105  * has been set on the clockevent device by the generic time management code.
106  *
107  * This function needs to be called by the timer exception handler and that's
108  * all the exception handler needs to do.
109  */
110 
timer_interrupt(struct pt_regs * regs)111 irqreturn_t __irq_entry timer_interrupt(struct pt_regs *regs)
112 {
113 	struct pt_regs *old_regs = set_irq_regs(regs);
114 	unsigned int cpu = smp_processor_id();
115 	struct clock_event_device *evt =
116 		&per_cpu(clockevent_openrisc_timer, cpu);
117 
118 	timer_ack();
119 
120 	/*
121 	 * update_process_times() expects us to have called irq_enter().
122 	 */
123 	irq_enter();
124 	evt->event_handler(evt);
125 	irq_exit();
126 
127 	set_irq_regs(old_regs);
128 
129 	return IRQ_HANDLED;
130 }
131 
132 /*
133  * Clocksource: Based on OpenRISC timer/counter
134  *
135  * This sets up the OpenRISC Tick Timer as a clock source.  The tick timer
136  * is 32 bits wide and runs at the CPU clock frequency.
137  */
openrisc_timer_read(struct clocksource * cs)138 static u64 openrisc_timer_read(struct clocksource *cs)
139 {
140 	return (u64) mfspr(SPR_TTCR);
141 }
142 
143 static struct clocksource openrisc_timer = {
144 	.name = "openrisc_timer",
145 	.rating = 200,
146 	.read = openrisc_timer_read,
147 	.mask = CLOCKSOURCE_MASK(32),
148 	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
149 };
150 
openrisc_timer_init(void)151 static int __init openrisc_timer_init(void)
152 {
153 	struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
154 
155 	if (clocksource_register_hz(&openrisc_timer, cpuinfo->clock_frequency))
156 		panic("failed to register clocksource");
157 
158 	/* Enable the incrementer: 'continuous' mode with interrupt disabled */
159 	mtspr(SPR_TTMR, SPR_TTMR_CR);
160 
161 	return 0;
162 }
163 
time_init(void)164 void __init time_init(void)
165 {
166 	u32 upr;
167 
168 	upr = mfspr(SPR_UPR);
169 	if (!(upr & SPR_UPR_TTP))
170 		panic("Linux not supported on devices without tick timer");
171 
172 	openrisc_timer_init();
173 	openrisc_clockevent_init();
174 
175 	of_clk_init(NULL);
176 	timer_probe();
177 }
178