1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #ifndef _ASM_POWERPC_SIMPLE_SPINLOCK_H
3 #define _ASM_POWERPC_SIMPLE_SPINLOCK_H
4
5 /*
6 * Simple spin lock operations.
7 *
8 * Copyright (C) 2001-2004 Paul Mackerras <paulus@au.ibm.com>, IBM
9 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
10 * Copyright (C) 2002 Dave Engebretsen <engebret@us.ibm.com>, IBM
11 * Rework to support virtual processors
12 *
13 * Type of int is used as a full 64b word is not necessary.
14 *
15 * (the type definitions are in asm/simple_spinlock_types.h)
16 */
17 #include <linux/irqflags.h>
18 #include <asm/paravirt.h>
19 #include <asm/paca.h>
20 #include <asm/synch.h>
21 #include <asm/ppc-opcode.h>
22
23 #ifdef CONFIG_PPC64
24 /* use 0x800000yy when locked, where yy == CPU number */
25 #ifdef __BIG_ENDIAN__
26 #define LOCK_TOKEN (*(u32 *)(&get_paca()->lock_token))
27 #else
28 #define LOCK_TOKEN (*(u32 *)(&get_paca()->paca_index))
29 #endif
30 #else
31 #define LOCK_TOKEN 1
32 #endif
33
arch_spin_value_unlocked(arch_spinlock_t lock)34 static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
35 {
36 return lock.slock == 0;
37 }
38
arch_spin_is_locked(arch_spinlock_t * lock)39 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
40 {
41 return !arch_spin_value_unlocked(READ_ONCE(*lock));
42 }
43
44 /*
45 * This returns the old value in the lock, so we succeeded
46 * in getting the lock if the return value is 0.
47 */
__arch_spin_trylock(arch_spinlock_t * lock)48 static inline unsigned long __arch_spin_trylock(arch_spinlock_t *lock)
49 {
50 unsigned long tmp, token;
51 unsigned int eh = IS_ENABLED(CONFIG_PPC64);
52
53 token = LOCK_TOKEN;
54 __asm__ __volatile__(
55 "1: lwarx %0,0,%2,%[eh]\n\
56 cmpwi 0,%0,0\n\
57 bne- 2f\n\
58 stwcx. %1,0,%2\n\
59 bne- 1b\n"
60 PPC_ACQUIRE_BARRIER
61 "2:"
62 : "=&r" (tmp)
63 : "r" (token), "r" (&lock->slock), [eh] "n" (eh)
64 : "cr0", "memory");
65
66 return tmp;
67 }
68
arch_spin_trylock(arch_spinlock_t * lock)69 static inline int arch_spin_trylock(arch_spinlock_t *lock)
70 {
71 return __arch_spin_trylock(lock) == 0;
72 }
73
74 /*
75 * On a system with shared processors (that is, where a physical
76 * processor is multiplexed between several virtual processors),
77 * there is no point spinning on a lock if the holder of the lock
78 * isn't currently scheduled on a physical processor. Instead
79 * we detect this situation and ask the hypervisor to give the
80 * rest of our timeslice to the lock holder.
81 *
82 * So that we can tell which virtual processor is holding a lock,
83 * we put 0x80000000 | smp_processor_id() in the lock when it is
84 * held. Conveniently, we have a word in the paca that holds this
85 * value.
86 */
87
88 #if defined(CONFIG_PPC_SPLPAR)
89 /* We only yield to the hypervisor if we are in shared processor mode */
90 void splpar_spin_yield(arch_spinlock_t *lock);
91 void splpar_rw_yield(arch_rwlock_t *lock);
92 #else /* SPLPAR */
splpar_spin_yield(arch_spinlock_t * lock)93 static inline void splpar_spin_yield(arch_spinlock_t *lock) {}
splpar_rw_yield(arch_rwlock_t * lock)94 static inline void splpar_rw_yield(arch_rwlock_t *lock) {}
95 #endif
96
spin_yield(arch_spinlock_t * lock)97 static inline void spin_yield(arch_spinlock_t *lock)
98 {
99 if (is_shared_processor())
100 splpar_spin_yield(lock);
101 else
102 barrier();
103 }
104
rw_yield(arch_rwlock_t * lock)105 static inline void rw_yield(arch_rwlock_t *lock)
106 {
107 if (is_shared_processor())
108 splpar_rw_yield(lock);
109 else
110 barrier();
111 }
112
arch_spin_lock(arch_spinlock_t * lock)113 static inline void arch_spin_lock(arch_spinlock_t *lock)
114 {
115 while (1) {
116 if (likely(__arch_spin_trylock(lock) == 0))
117 break;
118 do {
119 HMT_low();
120 if (is_shared_processor())
121 splpar_spin_yield(lock);
122 } while (unlikely(lock->slock != 0));
123 HMT_medium();
124 }
125 }
126
arch_spin_unlock(arch_spinlock_t * lock)127 static inline void arch_spin_unlock(arch_spinlock_t *lock)
128 {
129 __asm__ __volatile__("# arch_spin_unlock\n\t"
130 PPC_RELEASE_BARRIER: : :"memory");
131 lock->slock = 0;
132 }
133
134 /*
135 * Read-write spinlocks, allowing multiple readers
136 * but only one writer.
137 *
138 * NOTE! it is quite common to have readers in interrupts
139 * but no interrupt writers. For those circumstances we
140 * can "mix" irq-safe locks - any writer needs to get a
141 * irq-safe write-lock, but readers can get non-irqsafe
142 * read-locks.
143 */
144
145 #ifdef CONFIG_PPC64
146 #define __DO_SIGN_EXTEND "extsw %0,%0\n"
147 #define WRLOCK_TOKEN LOCK_TOKEN /* it's negative */
148 #else
149 #define __DO_SIGN_EXTEND
150 #define WRLOCK_TOKEN (-1)
151 #endif
152
153 /*
154 * This returns the old value in the lock + 1,
155 * so we got a read lock if the return value is > 0.
156 */
__arch_read_trylock(arch_rwlock_t * rw)157 static inline long __arch_read_trylock(arch_rwlock_t *rw)
158 {
159 long tmp;
160 unsigned int eh = IS_ENABLED(CONFIG_PPC64);
161
162 __asm__ __volatile__(
163 "1: lwarx %0,0,%1,%[eh]\n"
164 __DO_SIGN_EXTEND
165 " addic. %0,%0,1\n\
166 ble- 2f\n"
167 " stwcx. %0,0,%1\n\
168 bne- 1b\n"
169 PPC_ACQUIRE_BARRIER
170 "2:" : "=&r" (tmp)
171 : "r" (&rw->lock), [eh] "n" (eh)
172 : "cr0", "xer", "memory");
173
174 return tmp;
175 }
176
177 /*
178 * This returns the old value in the lock,
179 * so we got the write lock if the return value is 0.
180 */
__arch_write_trylock(arch_rwlock_t * rw)181 static inline long __arch_write_trylock(arch_rwlock_t *rw)
182 {
183 long tmp, token;
184 unsigned int eh = IS_ENABLED(CONFIG_PPC64);
185
186 token = WRLOCK_TOKEN;
187 __asm__ __volatile__(
188 "1: lwarx %0,0,%2,%[eh]\n\
189 cmpwi 0,%0,0\n\
190 bne- 2f\n"
191 " stwcx. %1,0,%2\n\
192 bne- 1b\n"
193 PPC_ACQUIRE_BARRIER
194 "2:" : "=&r" (tmp)
195 : "r" (token), "r" (&rw->lock), [eh] "n" (eh)
196 : "cr0", "memory");
197
198 return tmp;
199 }
200
arch_read_lock(arch_rwlock_t * rw)201 static inline void arch_read_lock(arch_rwlock_t *rw)
202 {
203 while (1) {
204 if (likely(__arch_read_trylock(rw) > 0))
205 break;
206 do {
207 HMT_low();
208 if (is_shared_processor())
209 splpar_rw_yield(rw);
210 } while (unlikely(rw->lock < 0));
211 HMT_medium();
212 }
213 }
214
arch_write_lock(arch_rwlock_t * rw)215 static inline void arch_write_lock(arch_rwlock_t *rw)
216 {
217 while (1) {
218 if (likely(__arch_write_trylock(rw) == 0))
219 break;
220 do {
221 HMT_low();
222 if (is_shared_processor())
223 splpar_rw_yield(rw);
224 } while (unlikely(rw->lock != 0));
225 HMT_medium();
226 }
227 }
228
arch_read_trylock(arch_rwlock_t * rw)229 static inline int arch_read_trylock(arch_rwlock_t *rw)
230 {
231 return __arch_read_trylock(rw) > 0;
232 }
233
arch_write_trylock(arch_rwlock_t * rw)234 static inline int arch_write_trylock(arch_rwlock_t *rw)
235 {
236 return __arch_write_trylock(rw) == 0;
237 }
238
arch_read_unlock(arch_rwlock_t * rw)239 static inline void arch_read_unlock(arch_rwlock_t *rw)
240 {
241 long tmp;
242
243 __asm__ __volatile__(
244 "# read_unlock\n\t"
245 PPC_RELEASE_BARRIER
246 "1: lwarx %0,0,%1\n\
247 addic %0,%0,-1\n"
248 " stwcx. %0,0,%1\n\
249 bne- 1b"
250 : "=&r"(tmp)
251 : "r"(&rw->lock)
252 : "cr0", "xer", "memory");
253 }
254
arch_write_unlock(arch_rwlock_t * rw)255 static inline void arch_write_unlock(arch_rwlock_t *rw)
256 {
257 __asm__ __volatile__("# write_unlock\n\t"
258 PPC_RELEASE_BARRIER: : :"memory");
259 rw->lock = 0;
260 }
261
262 #define arch_spin_relax(lock) spin_yield(lock)
263 #define arch_read_relax(lock) rw_yield(lock)
264 #define arch_write_relax(lock) rw_yield(lock)
265
266 #endif /* _ASM_POWERPC_SIMPLE_SPINLOCK_H */
267