1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * arch/powerpc/sysdev/uic.c
4 *
5 * IBM PowerPC 4xx Universal Interrupt Controller
6 *
7 * Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
8 */
9 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/errno.h>
12 #include <linux/reboot.h>
13 #include <linux/slab.h>
14 #include <linux/stddef.h>
15 #include <linux/sched.h>
16 #include <linux/signal.h>
17 #include <linux/device.h>
18 #include <linux/spinlock.h>
19 #include <linux/irq.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/of.h>
23 #include <linux/of_irq.h>
24 #include <asm/irq.h>
25 #include <asm/io.h>
26 #include <asm/dcr.h>
27
28 #define NR_UIC_INTS 32
29
30 #define UIC_SR 0x0
31 #define UIC_ER 0x2
32 #define UIC_CR 0x3
33 #define UIC_PR 0x4
34 #define UIC_TR 0x5
35 #define UIC_MSR 0x6
36 #define UIC_VR 0x7
37 #define UIC_VCR 0x8
38
39 struct uic *primary_uic;
40
41 struct uic {
42 int index;
43 int dcrbase;
44
45 raw_spinlock_t lock;
46
47 /* The remapper for this UIC */
48 struct irq_domain *irqhost;
49 };
50
uic_unmask_irq(struct irq_data * d)51 static void uic_unmask_irq(struct irq_data *d)
52 {
53 struct uic *uic = irq_data_get_irq_chip_data(d);
54 unsigned int src = irqd_to_hwirq(d);
55 unsigned long flags;
56 u32 er, sr;
57
58 sr = 1 << (31-src);
59 raw_spin_lock_irqsave(&uic->lock, flags);
60 /* ack level-triggered interrupts here */
61 if (irqd_is_level_type(d))
62 mtdcr(uic->dcrbase + UIC_SR, sr);
63 er = mfdcr(uic->dcrbase + UIC_ER);
64 er |= sr;
65 mtdcr(uic->dcrbase + UIC_ER, er);
66 raw_spin_unlock_irqrestore(&uic->lock, flags);
67 }
68
uic_mask_irq(struct irq_data * d)69 static void uic_mask_irq(struct irq_data *d)
70 {
71 struct uic *uic = irq_data_get_irq_chip_data(d);
72 unsigned int src = irqd_to_hwirq(d);
73 unsigned long flags;
74 u32 er;
75
76 raw_spin_lock_irqsave(&uic->lock, flags);
77 er = mfdcr(uic->dcrbase + UIC_ER);
78 er &= ~(1 << (31 - src));
79 mtdcr(uic->dcrbase + UIC_ER, er);
80 raw_spin_unlock_irqrestore(&uic->lock, flags);
81 }
82
uic_ack_irq(struct irq_data * d)83 static void uic_ack_irq(struct irq_data *d)
84 {
85 struct uic *uic = irq_data_get_irq_chip_data(d);
86 unsigned int src = irqd_to_hwirq(d);
87 unsigned long flags;
88
89 raw_spin_lock_irqsave(&uic->lock, flags);
90 mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src));
91 raw_spin_unlock_irqrestore(&uic->lock, flags);
92 }
93
uic_mask_ack_irq(struct irq_data * d)94 static void uic_mask_ack_irq(struct irq_data *d)
95 {
96 struct uic *uic = irq_data_get_irq_chip_data(d);
97 unsigned int src = irqd_to_hwirq(d);
98 unsigned long flags;
99 u32 er, sr;
100
101 sr = 1 << (31-src);
102 raw_spin_lock_irqsave(&uic->lock, flags);
103 er = mfdcr(uic->dcrbase + UIC_ER);
104 er &= ~sr;
105 mtdcr(uic->dcrbase + UIC_ER, er);
106 /* On the UIC, acking (i.e. clearing the SR bit)
107 * a level irq will have no effect if the interrupt
108 * is still asserted by the device, even if
109 * the interrupt is already masked. Therefore
110 * we only ack the egde interrupts here, while
111 * level interrupts are ack'ed after the actual
112 * isr call in the uic_unmask_irq()
113 */
114 if (!irqd_is_level_type(d))
115 mtdcr(uic->dcrbase + UIC_SR, sr);
116 raw_spin_unlock_irqrestore(&uic->lock, flags);
117 }
118
uic_set_irq_type(struct irq_data * d,unsigned int flow_type)119 static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type)
120 {
121 struct uic *uic = irq_data_get_irq_chip_data(d);
122 unsigned int src = irqd_to_hwirq(d);
123 unsigned long flags;
124 int trigger, polarity;
125 u32 tr, pr, mask;
126
127 switch (flow_type & IRQ_TYPE_SENSE_MASK) {
128 case IRQ_TYPE_NONE:
129 uic_mask_irq(d);
130 return 0;
131
132 case IRQ_TYPE_EDGE_RISING:
133 trigger = 1; polarity = 1;
134 break;
135 case IRQ_TYPE_EDGE_FALLING:
136 trigger = 1; polarity = 0;
137 break;
138 case IRQ_TYPE_LEVEL_HIGH:
139 trigger = 0; polarity = 1;
140 break;
141 case IRQ_TYPE_LEVEL_LOW:
142 trigger = 0; polarity = 0;
143 break;
144 default:
145 return -EINVAL;
146 }
147
148 mask = ~(1 << (31 - src));
149
150 raw_spin_lock_irqsave(&uic->lock, flags);
151 tr = mfdcr(uic->dcrbase + UIC_TR);
152 pr = mfdcr(uic->dcrbase + UIC_PR);
153 tr = (tr & mask) | (trigger << (31-src));
154 pr = (pr & mask) | (polarity << (31-src));
155
156 mtdcr(uic->dcrbase + UIC_PR, pr);
157 mtdcr(uic->dcrbase + UIC_TR, tr);
158 mtdcr(uic->dcrbase + UIC_SR, ~mask);
159
160 raw_spin_unlock_irqrestore(&uic->lock, flags);
161
162 return 0;
163 }
164
165 static struct irq_chip uic_irq_chip = {
166 .name = "UIC",
167 .irq_unmask = uic_unmask_irq,
168 .irq_mask = uic_mask_irq,
169 .irq_mask_ack = uic_mask_ack_irq,
170 .irq_ack = uic_ack_irq,
171 .irq_set_type = uic_set_irq_type,
172 };
173
uic_host_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)174 static int uic_host_map(struct irq_domain *h, unsigned int virq,
175 irq_hw_number_t hw)
176 {
177 struct uic *uic = h->host_data;
178
179 irq_set_chip_data(virq, uic);
180 /* Despite the name, handle_level_irq() works for both level
181 * and edge irqs on UIC. FIXME: check this is correct */
182 irq_set_chip_and_handler(virq, &uic_irq_chip, handle_level_irq);
183
184 /* Set default irq type */
185 irq_set_irq_type(virq, IRQ_TYPE_NONE);
186
187 return 0;
188 }
189
190 static const struct irq_domain_ops uic_host_ops = {
191 .map = uic_host_map,
192 .xlate = irq_domain_xlate_twocell,
193 };
194
uic_irq_cascade(struct irq_desc * desc)195 static void uic_irq_cascade(struct irq_desc *desc)
196 {
197 struct irq_chip *chip = irq_desc_get_chip(desc);
198 struct irq_data *idata = irq_desc_get_irq_data(desc);
199 struct uic *uic = irq_desc_get_handler_data(desc);
200 u32 msr;
201 int src;
202
203 raw_spin_lock(&desc->lock);
204 if (irqd_is_level_type(idata))
205 chip->irq_mask(idata);
206 else
207 chip->irq_mask_ack(idata);
208 raw_spin_unlock(&desc->lock);
209
210 msr = mfdcr(uic->dcrbase + UIC_MSR);
211 if (!msr) /* spurious interrupt */
212 goto uic_irq_ret;
213
214 src = 32 - ffs(msr);
215
216 generic_handle_domain_irq(uic->irqhost, src);
217
218 uic_irq_ret:
219 raw_spin_lock(&desc->lock);
220 if (irqd_is_level_type(idata))
221 chip->irq_ack(idata);
222 if (!irqd_irq_disabled(idata) && chip->irq_unmask)
223 chip->irq_unmask(idata);
224 raw_spin_unlock(&desc->lock);
225 }
226
uic_init_one(struct device_node * node)227 static struct uic * __init uic_init_one(struct device_node *node)
228 {
229 struct uic *uic;
230 const u32 *indexp, *dcrreg;
231 int len;
232
233 BUG_ON(! of_device_is_compatible(node, "ibm,uic"));
234
235 uic = kzalloc(sizeof(*uic), GFP_KERNEL);
236 if (! uic)
237 return NULL; /* FIXME: panic? */
238
239 raw_spin_lock_init(&uic->lock);
240 indexp = of_get_property(node, "cell-index", &len);
241 if (!indexp || (len != sizeof(u32))) {
242 printk(KERN_ERR "uic: Device node %pOF has missing or invalid "
243 "cell-index property\n", node);
244 return NULL;
245 }
246 uic->index = *indexp;
247
248 dcrreg = of_get_property(node, "dcr-reg", &len);
249 if (!dcrreg || (len != 2*sizeof(u32))) {
250 printk(KERN_ERR "uic: Device node %pOF has missing or invalid "
251 "dcr-reg property\n", node);
252 return NULL;
253 }
254 uic->dcrbase = *dcrreg;
255
256 uic->irqhost = irq_domain_add_linear(node, NR_UIC_INTS, &uic_host_ops,
257 uic);
258 if (! uic->irqhost)
259 return NULL; /* FIXME: panic? */
260
261 /* Start with all interrupts disabled, level and non-critical */
262 mtdcr(uic->dcrbase + UIC_ER, 0);
263 mtdcr(uic->dcrbase + UIC_CR, 0);
264 mtdcr(uic->dcrbase + UIC_TR, 0);
265 /* Clear any pending interrupts, in case the firmware left some */
266 mtdcr(uic->dcrbase + UIC_SR, 0xffffffff);
267
268 printk ("UIC%d (%d IRQ sources) at DCR 0x%x\n", uic->index,
269 NR_UIC_INTS, uic->dcrbase);
270
271 return uic;
272 }
273
uic_init_tree(void)274 void __init uic_init_tree(void)
275 {
276 struct device_node *np;
277 struct uic *uic;
278 const u32 *interrupts;
279
280 /* First locate and initialize the top-level UIC */
281 for_each_compatible_node(np, NULL, "ibm,uic") {
282 interrupts = of_get_property(np, "interrupts", NULL);
283 if (!interrupts)
284 break;
285 }
286
287 BUG_ON(!np); /* uic_init_tree() assumes there's a UIC as the
288 * top-level interrupt controller */
289 primary_uic = uic_init_one(np);
290 if (!primary_uic)
291 panic("Unable to initialize primary UIC %pOF\n", np);
292
293 irq_set_default_host(primary_uic->irqhost);
294 of_node_put(np);
295
296 /* The scan again for cascaded UICs */
297 for_each_compatible_node(np, NULL, "ibm,uic") {
298 interrupts = of_get_property(np, "interrupts", NULL);
299 if (interrupts) {
300 /* Secondary UIC */
301 int cascade_virq;
302
303 uic = uic_init_one(np);
304 if (! uic)
305 panic("Unable to initialize a secondary UIC %pOF\n",
306 np);
307
308 cascade_virq = irq_of_parse_and_map(np, 0);
309
310 irq_set_handler_data(cascade_virq, uic);
311 irq_set_chained_handler(cascade_virq, uic_irq_cascade);
312
313 /* FIXME: setup critical cascade?? */
314 }
315 }
316 }
317
318 /* Return an interrupt vector or 0 if no interrupt is pending. */
uic_get_irq(void)319 unsigned int uic_get_irq(void)
320 {
321 u32 msr;
322 int src;
323
324 BUG_ON(! primary_uic);
325
326 msr = mfdcr(primary_uic->dcrbase + UIC_MSR);
327 src = 32 - ffs(msr);
328
329 return irq_linear_revmap(primary_uic->irqhost, src);
330 }
331