1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2006 Freescale Semiconductor, Inc. All rights reserved.
4 *
5 * Author: Li Yang <LeoLi@freescale.com>
6 * Yin Olivia <Hong-hua.Yin@freescale.com>
7 *
8 * Description:
9 * MPC8360E MDS board specific routines.
10 *
11 * Changelog:
12 * Jun 21, 2006 Initial version
13 */
14
15 #include <linux/stddef.h>
16 #include <linux/kernel.h>
17 #include <linux/compiler.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/reboot.h>
21 #include <linux/pci.h>
22 #include <linux/kdev_t.h>
23 #include <linux/major.h>
24 #include <linux/console.h>
25 #include <linux/delay.h>
26 #include <linux/seq_file.h>
27 #include <linux/root_dev.h>
28 #include <linux/initrd.h>
29 #include <linux/of_platform.h>
30 #include <linux/of_device.h>
31
32 #include <linux/atomic.h>
33 #include <asm/time.h>
34 #include <asm/io.h>
35 #include <asm/machdep.h>
36 #include <asm/ipic.h>
37 #include <asm/irq.h>
38 #include <asm/udbg.h>
39 #include <sysdev/fsl_soc.h>
40 #include <sysdev/fsl_pci.h>
41 #include <soc/fsl/qe/qe.h>
42
43 #include "mpc83xx.h"
44
45 #undef DEBUG
46 #ifdef DEBUG
47 #define DBG(fmt...) udbg_printf(fmt)
48 #else
49 #define DBG(fmt...)
50 #endif
51
52 /* ************************************************************************
53 *
54 * Setup the architecture
55 *
56 */
mpc836x_mds_setup_arch(void)57 static void __init mpc836x_mds_setup_arch(void)
58 {
59 struct device_node *np;
60 u8 __iomem *bcsr_regs = NULL;
61
62 mpc83xx_setup_arch();
63
64 /* Map BCSR area */
65 np = of_find_node_by_name(NULL, "bcsr");
66 if (np) {
67 struct resource res;
68
69 of_address_to_resource(np, 0, &res);
70 bcsr_regs = ioremap(res.start, resource_size(&res));
71 of_node_put(np);
72 }
73
74 #ifdef CONFIG_QUICC_ENGINE
75 if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
76 par_io_init(np);
77 of_node_put(np);
78
79 for_each_node_by_name(np, "ucc")
80 par_io_of_config(np);
81 #ifdef CONFIG_QE_USB
82 /* Must fixup Par IO before QE GPIO chips are registered. */
83 par_io_config_pin(1, 2, 1, 0, 3, 0); /* USBOE */
84 par_io_config_pin(1, 3, 1, 0, 3, 0); /* USBTP */
85 par_io_config_pin(1, 8, 1, 0, 1, 0); /* USBTN */
86 par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */
87 par_io_config_pin(1, 9, 2, 1, 3, 0); /* USBRP */
88 par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN */
89 par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21 */
90 #endif /* CONFIG_QE_USB */
91 }
92
93 if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
94 != NULL){
95 uint svid;
96
97 /* Reset the Ethernet PHY */
98 #define BCSR9_GETHRST 0x20
99 clrbits8(&bcsr_regs[9], BCSR9_GETHRST);
100 udelay(1000);
101 setbits8(&bcsr_regs[9], BCSR9_GETHRST);
102
103 /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
104 svid = mfspr(SPRN_SVR);
105 if (svid == 0x80480021) {
106 void __iomem *immap;
107
108 immap = ioremap(get_immrbase() + 0x14a8, 8);
109
110 /*
111 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
112 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
113 */
114 setbits32(immap, 0x0c003000);
115
116 /*
117 * IMMR + 0x14AC[20:27] = 10101010
118 * (data delay for both UCC's)
119 */
120 clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
121
122 iounmap(immap);
123 }
124
125 iounmap(bcsr_regs);
126 of_node_put(np);
127 }
128 #endif /* CONFIG_QUICC_ENGINE */
129 }
130
131 machine_device_initcall(mpc836x_mds, mpc83xx_declare_of_platform_devices);
132
133 #ifdef CONFIG_QE_USB
mpc836x_usb_cfg(void)134 static int __init mpc836x_usb_cfg(void)
135 {
136 u8 __iomem *bcsr;
137 struct device_node *np;
138 const char *mode;
139 int ret = 0;
140
141 np = of_find_compatible_node(NULL, NULL, "fsl,mpc8360mds-bcsr");
142 if (!np)
143 return -ENODEV;
144
145 bcsr = of_iomap(np, 0);
146 of_node_put(np);
147 if (!bcsr)
148 return -ENOMEM;
149
150 np = of_find_compatible_node(NULL, NULL, "fsl,mpc8323-qe-usb");
151 if (!np) {
152 ret = -ENODEV;
153 goto err;
154 }
155
156 #define BCSR8_TSEC1M_MASK (0x3 << 6)
157 #define BCSR8_TSEC1M_RGMII (0x0 << 6)
158 #define BCSR8_TSEC2M_MASK (0x3 << 4)
159 #define BCSR8_TSEC2M_RGMII (0x0 << 4)
160 /*
161 * Default is GMII (2), but we should set it to RGMII (0) if we use
162 * USB (Eth PHY is in RGMII mode anyway).
163 */
164 clrsetbits_8(&bcsr[8], BCSR8_TSEC1M_MASK | BCSR8_TSEC2M_MASK,
165 BCSR8_TSEC1M_RGMII | BCSR8_TSEC2M_RGMII);
166
167 #define BCSR13_USBMASK 0x0f
168 #define BCSR13_nUSBEN 0x08 /* 1 - Disable, 0 - Enable */
169 #define BCSR13_USBSPEED 0x04 /* 1 - Full, 0 - Low */
170 #define BCSR13_USBMODE 0x02 /* 1 - Host, 0 - Function */
171 #define BCSR13_nUSBVCC 0x01 /* 1 - gets VBUS, 0 - supplies VBUS */
172
173 clrsetbits_8(&bcsr[13], BCSR13_USBMASK, BCSR13_USBSPEED);
174
175 mode = of_get_property(np, "mode", NULL);
176 if (mode && !strcmp(mode, "peripheral")) {
177 setbits8(&bcsr[13], BCSR13_nUSBVCC);
178 qe_usb_clock_set(QE_CLK21, 48000000);
179 } else {
180 setbits8(&bcsr[13], BCSR13_USBMODE);
181 }
182
183 of_node_put(np);
184 err:
185 iounmap(bcsr);
186 return ret;
187 }
188 machine_arch_initcall(mpc836x_mds, mpc836x_usb_cfg);
189 #endif /* CONFIG_QE_USB */
190
191 /*
192 * Called very early, MMU is off, device-tree isn't unflattened
193 */
mpc836x_mds_probe(void)194 static int __init mpc836x_mds_probe(void)
195 {
196 return of_machine_is_compatible("MPC836xMDS");
197 }
198
define_machine(mpc836x_mds)199 define_machine(mpc836x_mds) {
200 .name = "MPC836x MDS",
201 .probe = mpc836x_mds_probe,
202 .setup_arch = mpc836x_mds_setup_arch,
203 .discover_phbs = mpc83xx_setup_pci,
204 .init_IRQ = mpc83xx_ipic_init_IRQ,
205 .get_irq = ipic_get_irq,
206 .restart = mpc83xx_restart,
207 .time_init = mpc83xx_time_init,
208 .calibrate_decr = generic_calibrate_decr,
209 .progress = udbg_progress,
210 };
211