1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2006-2010, 2012-2013 Freescale Semiconductor, Inc.
4 * All rights reserved.
5 *
6 * Author: Andy Fleming <afleming@freescale.com>
7 *
8 * Based on 83xx/mpc8360e_pb.c by:
9 * Li Yang <LeoLi@freescale.com>
10 * Yin Olivia <Hong-hua.Yin@freescale.com>
11 *
12 * Description:
13 * MPC85xx MDS board specific routines.
14 */
15
16 #include <linux/stddef.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/reboot.h>
21 #include <linux/pci.h>
22 #include <linux/kdev_t.h>
23 #include <linux/major.h>
24 #include <linux/console.h>
25 #include <linux/delay.h>
26 #include <linux/seq_file.h>
27 #include <linux/initrd.h>
28 #include <linux/fsl_devices.h>
29 #include <linux/of_platform.h>
30 #include <linux/of_device.h>
31 #include <linux/phy.h>
32 #include <linux/memblock.h>
33 #include <linux/fsl/guts.h>
34
35 #include <linux/atomic.h>
36 #include <asm/time.h>
37 #include <asm/io.h>
38 #include <asm/machdep.h>
39 #include <asm/pci-bridge.h>
40 #include <asm/irq.h>
41 #include <mm/mmu_decl.h>
42 #include <asm/udbg.h>
43 #include <sysdev/fsl_soc.h>
44 #include <sysdev/fsl_pci.h>
45 #include <soc/fsl/qe/qe.h>
46 #include <asm/mpic.h>
47 #include <asm/swiotlb.h>
48 #include "smp.h"
49
50 #include "mpc85xx.h"
51
52 #undef DEBUG
53 #ifdef DEBUG
54 #define DBG(fmt...) udbg_printf(fmt)
55 #else
56 #define DBG(fmt...)
57 #endif
58
59 #if IS_BUILTIN(CONFIG_PHYLIB)
60
61 #define MV88E1111_SCR 0x10
62 #define MV88E1111_SCR_125CLK 0x0010
mpc8568_fixup_125_clock(struct phy_device * phydev)63 static int mpc8568_fixup_125_clock(struct phy_device *phydev)
64 {
65 int scr;
66 int err;
67
68 /* Workaround for the 125 CLK Toggle */
69 scr = phy_read(phydev, MV88E1111_SCR);
70
71 if (scr < 0)
72 return scr;
73
74 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
75
76 if (err)
77 return err;
78
79 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
80
81 if (err)
82 return err;
83
84 scr = phy_read(phydev, MV88E1111_SCR);
85
86 if (scr < 0)
87 return scr;
88
89 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
90
91 return err;
92 }
93
mpc8568_mds_phy_fixups(struct phy_device * phydev)94 static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
95 {
96 int temp;
97 int err;
98
99 /* Errata */
100 err = phy_write(phydev,29, 0x0006);
101
102 if (err)
103 return err;
104
105 temp = phy_read(phydev, 30);
106
107 if (temp < 0)
108 return temp;
109
110 temp = (temp & (~0x8000)) | 0x4000;
111 err = phy_write(phydev,30, temp);
112
113 if (err)
114 return err;
115
116 err = phy_write(phydev,29, 0x000a);
117
118 if (err)
119 return err;
120
121 temp = phy_read(phydev, 30);
122
123 if (temp < 0)
124 return temp;
125
126 temp = phy_read(phydev, 30);
127
128 if (temp < 0)
129 return temp;
130
131 temp &= ~0x0020;
132
133 err = phy_write(phydev,30,temp);
134
135 if (err)
136 return err;
137
138 /* Disable automatic MDI/MDIX selection */
139 temp = phy_read(phydev, 16);
140
141 if (temp < 0)
142 return temp;
143
144 temp &= ~0x0060;
145 err = phy_write(phydev,16,temp);
146
147 return err;
148 }
149
150 #endif
151
152 /* ************************************************************************
153 *
154 * Setup the architecture
155 *
156 */
157 #ifdef CONFIG_QUICC_ENGINE
mpc85xx_mds_reset_ucc_phys(void)158 static void __init mpc85xx_mds_reset_ucc_phys(void)
159 {
160 struct device_node *np;
161 static u8 __iomem *bcsr_regs;
162
163 /* Map BCSR area */
164 np = of_find_node_by_name(NULL, "bcsr");
165 if (!np)
166 return;
167
168 bcsr_regs = of_iomap(np, 0);
169 of_node_put(np);
170 if (!bcsr_regs)
171 return;
172
173 if (machine_is(mpc8568_mds)) {
174 #define BCSR_UCC1_GETH_EN (0x1 << 7)
175 #define BCSR_UCC2_GETH_EN (0x1 << 7)
176 #define BCSR_UCC1_MODE_MSK (0x3 << 4)
177 #define BCSR_UCC2_MODE_MSK (0x3 << 0)
178
179 /* Turn off UCC1 & UCC2 */
180 clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
181 clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
182
183 /* Mode is RGMII, all bits clear */
184 clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
185 BCSR_UCC2_MODE_MSK);
186
187 /* Turn UCC1 & UCC2 on */
188 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
189 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
190 } else if (machine_is(mpc8569_mds)) {
191 #define BCSR7_UCC12_GETHnRST (0x1 << 2)
192 #define BCSR8_UEM_MARVELL_RST (0x1 << 1)
193 #define BCSR_UCC_RGMII (0x1 << 6)
194 #define BCSR_UCC_RTBI (0x1 << 5)
195 /*
196 * U-Boot mangles interrupt polarity for Marvell PHYs,
197 * so reset built-in and UEM Marvell PHYs, this puts
198 * the PHYs into their normal state.
199 */
200 clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
201 setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
202
203 setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
204 clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
205
206 for_each_compatible_node(np, "network", "ucc_geth") {
207 const unsigned int *prop;
208 int ucc_num;
209
210 prop = of_get_property(np, "cell-index", NULL);
211 if (prop == NULL)
212 continue;
213
214 ucc_num = *prop - 1;
215
216 prop = of_get_property(np, "phy-connection-type", NULL);
217 if (prop == NULL)
218 continue;
219
220 if (strcmp("rtbi", (const char *)prop) == 0)
221 clrsetbits_8(&bcsr_regs[7 + ucc_num],
222 BCSR_UCC_RGMII, BCSR_UCC_RTBI);
223 }
224 } else if (machine_is(p1021_mds)) {
225 #define BCSR11_ENET_MICRST (0x1 << 5)
226 /* Reset Micrel PHY */
227 clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
228 setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
229 }
230
231 iounmap(bcsr_regs);
232 }
233
mpc85xx_mds_qe_init(void)234 static void __init mpc85xx_mds_qe_init(void)
235 {
236 struct device_node *np;
237
238 mpc85xx_qe_par_io_init();
239 mpc85xx_mds_reset_ucc_phys();
240
241 if (machine_is(p1021_mds)) {
242
243 struct ccsr_guts __iomem *guts;
244
245 np = of_find_node_by_name(NULL, "global-utilities");
246 if (np) {
247 guts = of_iomap(np, 0);
248 if (!guts)
249 pr_err("mpc85xx-rdb: could not map global utilities register\n");
250 else{
251 /* P1021 has pins muxed for QE and other functions. To
252 * enable QE UEC mode, we need to set bit QE0 for UCC1
253 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
254 * and QE12 for QE MII management signals in PMUXCR
255 * register.
256 */
257 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
258 MPC85xx_PMUXCR_QE(3) |
259 MPC85xx_PMUXCR_QE(9) |
260 MPC85xx_PMUXCR_QE(12));
261 iounmap(guts);
262 }
263 of_node_put(np);
264 }
265
266 }
267 }
268
269 #else
mpc85xx_mds_qe_init(void)270 static void __init mpc85xx_mds_qe_init(void) { }
271 #endif /* CONFIG_QUICC_ENGINE */
272
mpc85xx_mds_setup_arch(void)273 static void __init mpc85xx_mds_setup_arch(void)
274 {
275 if (ppc_md.progress)
276 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
277
278 mpc85xx_smp_init();
279
280 mpc85xx_mds_qe_init();
281
282 fsl_pci_assign_primary();
283
284 swiotlb_detect_4g();
285 }
286
287 #if IS_BUILTIN(CONFIG_PHYLIB)
288
board_fixups(void)289 static int __init board_fixups(void)
290 {
291 char phy_id[20];
292 char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
293 struct device_node *mdio;
294 struct resource res;
295 int i;
296
297 for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
298 mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
299
300 of_address_to_resource(mdio, 0, &res);
301 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
302 (unsigned long long)res.start, 1);
303
304 phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
305 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
306
307 /* Register a workaround for errata */
308 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
309 (unsigned long long)res.start, 7);
310 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
311
312 of_node_put(mdio);
313 }
314
315 return 0;
316 }
317
318 machine_arch_initcall(mpc8568_mds, board_fixups);
319 machine_arch_initcall(mpc8569_mds, board_fixups);
320
321 #endif
322
mpc85xx_publish_devices(void)323 static int __init mpc85xx_publish_devices(void)
324 {
325 return mpc85xx_common_publish_devices();
326 }
327
328 machine_arch_initcall(mpc8568_mds, mpc85xx_publish_devices);
329 machine_arch_initcall(mpc8569_mds, mpc85xx_publish_devices);
330 machine_arch_initcall(p1021_mds, mpc85xx_common_publish_devices);
331
mpc85xx_mds_pic_init(void)332 static void __init mpc85xx_mds_pic_init(void)
333 {
334 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
335 MPIC_SINGLE_DEST_CPU,
336 0, 256, " OpenPIC ");
337 BUG_ON(mpic == NULL);
338
339 mpic_init(mpic);
340 }
341
mpc85xx_mds_probe(void)342 static int __init mpc85xx_mds_probe(void)
343 {
344 return of_machine_is_compatible("MPC85xxMDS");
345 }
346
define_machine(mpc8568_mds)347 define_machine(mpc8568_mds) {
348 .name = "MPC8568 MDS",
349 .probe = mpc85xx_mds_probe,
350 .setup_arch = mpc85xx_mds_setup_arch,
351 .init_IRQ = mpc85xx_mds_pic_init,
352 .get_irq = mpic_get_irq,
353 .calibrate_decr = generic_calibrate_decr,
354 .progress = udbg_progress,
355 #ifdef CONFIG_PCI
356 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
357 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
358 #endif
359 };
360
mpc8569_mds_probe(void)361 static int __init mpc8569_mds_probe(void)
362 {
363 return of_machine_is_compatible("fsl,MPC8569EMDS");
364 }
365
define_machine(mpc8569_mds)366 define_machine(mpc8569_mds) {
367 .name = "MPC8569 MDS",
368 .probe = mpc8569_mds_probe,
369 .setup_arch = mpc85xx_mds_setup_arch,
370 .init_IRQ = mpc85xx_mds_pic_init,
371 .get_irq = mpic_get_irq,
372 .calibrate_decr = generic_calibrate_decr,
373 .progress = udbg_progress,
374 #ifdef CONFIG_PCI
375 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
376 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
377 #endif
378 };
379
p1021_mds_probe(void)380 static int __init p1021_mds_probe(void)
381 {
382 return of_machine_is_compatible("fsl,P1021MDS");
383
384 }
385
define_machine(p1021_mds)386 define_machine(p1021_mds) {
387 .name = "P1021 MDS",
388 .probe = p1021_mds_probe,
389 .setup_arch = mpc85xx_mds_setup_arch,
390 .init_IRQ = mpc85xx_mds_pic_init,
391 .get_irq = mpic_get_irq,
392 .calibrate_decr = generic_calibrate_decr,
393 .progress = udbg_progress,
394 #ifdef CONFIG_PCI
395 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
396 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
397 #endif
398 };
399