1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Common CPM code
4  *
5  * Author: Scott Wood <scottwood@freescale.com>
6  *
7  * Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
8  *
9  * Some parts derived from commproc.c/cpm2_common.c, which is:
10  * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
11  * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
12  * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
13  * 2006 (c) MontaVista Software, Inc.
14  * Vitaly Bordug <vbordug@ru.mvista.com>
15  */
16 
17 #include <linux/init.h>
18 #include <linux/of_device.h>
19 #include <linux/spinlock.h>
20 #include <linux/export.h>
21 #include <linux/of.h>
22 #include <linux/of_address.h>
23 #include <linux/slab.h>
24 
25 #include <asm/udbg.h>
26 #include <asm/io.h>
27 #include <asm/cpm.h>
28 #include <asm/fixmap.h>
29 #include <soc/fsl/qe/qe.h>
30 
31 #include <mm/mmu_decl.h>
32 
33 #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
34 #include <linux/of_gpio.h>
35 #endif
36 
cpm_init(void)37 static int __init cpm_init(void)
38 {
39 	struct device_node *np;
40 
41 	np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
42 	if (!np)
43 		np = of_find_compatible_node(NULL, NULL, "fsl,cpm2");
44 	if (!np)
45 		return -ENODEV;
46 	cpm_muram_init();
47 	of_node_put(np);
48 	return 0;
49 }
50 subsys_initcall(cpm_init);
51 
52 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
53 static u32 __iomem *cpm_udbg_txdesc;
54 static u8 __iomem *cpm_udbg_txbuf;
55 
udbg_putc_cpm(char c)56 static void udbg_putc_cpm(char c)
57 {
58 	if (c == '\n')
59 		udbg_putc_cpm('\r');
60 
61 	while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000)
62 		;
63 
64 	out_8(cpm_udbg_txbuf, c);
65 	out_be32(&cpm_udbg_txdesc[0], 0xa0000001);
66 }
67 
udbg_init_cpm(void)68 void __init udbg_init_cpm(void)
69 {
70 #ifdef CONFIG_PPC_8xx
71 	mmu_mapin_immr();
72 
73 	cpm_udbg_txdesc = (u32 __iomem __force *)
74 			  (CONFIG_PPC_EARLY_DEBUG_CPM_ADDR - PHYS_IMMR_BASE +
75 			   VIRT_IMMR_BASE);
76 	cpm_udbg_txbuf = (u8 __iomem __force *)
77 			 (in_be32(&cpm_udbg_txdesc[1]) - PHYS_IMMR_BASE +
78 			  VIRT_IMMR_BASE);
79 #else
80 	cpm_udbg_txdesc = (u32 __iomem __force *)
81 			  CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;
82 	cpm_udbg_txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]);
83 #endif
84 
85 	if (cpm_udbg_txdesc) {
86 #ifdef CONFIG_CPM2
87 		setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG);
88 #endif
89 		udbg_putc = udbg_putc_cpm;
90 	}
91 }
92 #endif
93 
94 #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
95 
96 struct cpm2_ioports {
97 	u32 dir, par, sor, odr, dat;
98 	u32 res[3];
99 };
100 
101 struct cpm2_gpio32_chip {
102 	struct of_mm_gpio_chip mm_gc;
103 	spinlock_t lock;
104 
105 	/* shadowed data register to clear/set bits safely */
106 	u32 cpdata;
107 };
108 
cpm2_gpio32_save_regs(struct of_mm_gpio_chip * mm_gc)109 static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
110 {
111 	struct cpm2_gpio32_chip *cpm2_gc =
112 		container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc);
113 	struct cpm2_ioports __iomem *iop = mm_gc->regs;
114 
115 	cpm2_gc->cpdata = in_be32(&iop->dat);
116 }
117 
cpm2_gpio32_get(struct gpio_chip * gc,unsigned int gpio)118 static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
119 {
120 	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
121 	struct cpm2_ioports __iomem *iop = mm_gc->regs;
122 	u32 pin_mask;
123 
124 	pin_mask = 1 << (31 - gpio);
125 
126 	return !!(in_be32(&iop->dat) & pin_mask);
127 }
128 
__cpm2_gpio32_set(struct of_mm_gpio_chip * mm_gc,u32 pin_mask,int value)129 static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
130 	int value)
131 {
132 	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(&mm_gc->gc);
133 	struct cpm2_ioports __iomem *iop = mm_gc->regs;
134 
135 	if (value)
136 		cpm2_gc->cpdata |= pin_mask;
137 	else
138 		cpm2_gc->cpdata &= ~pin_mask;
139 
140 	out_be32(&iop->dat, cpm2_gc->cpdata);
141 }
142 
cpm2_gpio32_set(struct gpio_chip * gc,unsigned int gpio,int value)143 static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
144 {
145 	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
146 	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
147 	unsigned long flags;
148 	u32 pin_mask = 1 << (31 - gpio);
149 
150 	spin_lock_irqsave(&cpm2_gc->lock, flags);
151 
152 	__cpm2_gpio32_set(mm_gc, pin_mask, value);
153 
154 	spin_unlock_irqrestore(&cpm2_gc->lock, flags);
155 }
156 
cpm2_gpio32_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)157 static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
158 {
159 	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
160 	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
161 	struct cpm2_ioports __iomem *iop = mm_gc->regs;
162 	unsigned long flags;
163 	u32 pin_mask = 1 << (31 - gpio);
164 
165 	spin_lock_irqsave(&cpm2_gc->lock, flags);
166 
167 	setbits32(&iop->dir, pin_mask);
168 	__cpm2_gpio32_set(mm_gc, pin_mask, val);
169 
170 	spin_unlock_irqrestore(&cpm2_gc->lock, flags);
171 
172 	return 0;
173 }
174 
cpm2_gpio32_dir_in(struct gpio_chip * gc,unsigned int gpio)175 static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
176 {
177 	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
178 	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
179 	struct cpm2_ioports __iomem *iop = mm_gc->regs;
180 	unsigned long flags;
181 	u32 pin_mask = 1 << (31 - gpio);
182 
183 	spin_lock_irqsave(&cpm2_gc->lock, flags);
184 
185 	clrbits32(&iop->dir, pin_mask);
186 
187 	spin_unlock_irqrestore(&cpm2_gc->lock, flags);
188 
189 	return 0;
190 }
191 
cpm2_gpiochip_add32(struct device * dev)192 int cpm2_gpiochip_add32(struct device *dev)
193 {
194 	struct device_node *np = dev->of_node;
195 	struct cpm2_gpio32_chip *cpm2_gc;
196 	struct of_mm_gpio_chip *mm_gc;
197 	struct gpio_chip *gc;
198 
199 	cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL);
200 	if (!cpm2_gc)
201 		return -ENOMEM;
202 
203 	spin_lock_init(&cpm2_gc->lock);
204 
205 	mm_gc = &cpm2_gc->mm_gc;
206 	gc = &mm_gc->gc;
207 
208 	mm_gc->save_regs = cpm2_gpio32_save_regs;
209 	gc->ngpio = 32;
210 	gc->direction_input = cpm2_gpio32_dir_in;
211 	gc->direction_output = cpm2_gpio32_dir_out;
212 	gc->get = cpm2_gpio32_get;
213 	gc->set = cpm2_gpio32_set;
214 	gc->parent = dev;
215 	gc->owner = THIS_MODULE;
216 
217 	return of_mm_gpiochip_add_data(np, mm_gc, cpm2_gc);
218 }
219 #endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */
220