1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * S390 version
4 * Copyright IBM Corp. 1999
5 * Author(s): Hartmut Penner (hp@de.ibm.com),
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/processor.h"
9 * Copyright (C) 1994, Linus Torvalds
10 */
11
12 #ifndef __ASM_S390_PROCESSOR_H
13 #define __ASM_S390_PROCESSOR_H
14
15 #include <linux/bits.h>
16
17 #define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */
18 #define CIF_FPU 3 /* restore FPU registers */
19 #define CIF_ENABLED_WAIT 5 /* in enabled wait state */
20 #define CIF_MCCK_GUEST 6 /* machine check happening in guest */
21 #define CIF_DEDICATED_CPU 7 /* this CPU is dedicated */
22
23 #define _CIF_NOHZ_DELAY BIT(CIF_NOHZ_DELAY)
24 #define _CIF_FPU BIT(CIF_FPU)
25 #define _CIF_ENABLED_WAIT BIT(CIF_ENABLED_WAIT)
26 #define _CIF_MCCK_GUEST BIT(CIF_MCCK_GUEST)
27 #define _CIF_DEDICATED_CPU BIT(CIF_DEDICATED_CPU)
28
29 #define RESTART_FLAG_CTLREGS _AC(1 << 0, U)
30
31 #ifndef __ASSEMBLY__
32
33 #include <linux/cpumask.h>
34 #include <linux/linkage.h>
35 #include <linux/irqflags.h>
36 #include <asm/cpu.h>
37 #include <asm/page.h>
38 #include <asm/ptrace.h>
39 #include <asm/setup.h>
40 #include <asm/runtime_instr.h>
41 #include <asm/fpu/types.h>
42 #include <asm/fpu/internal.h>
43 #include <asm/irqflags.h>
44
45 typedef long (*sys_call_ptr_t)(struct pt_regs *regs);
46
set_cpu_flag(int flag)47 static __always_inline void set_cpu_flag(int flag)
48 {
49 S390_lowcore.cpu_flags |= (1UL << flag);
50 }
51
clear_cpu_flag(int flag)52 static __always_inline void clear_cpu_flag(int flag)
53 {
54 S390_lowcore.cpu_flags &= ~(1UL << flag);
55 }
56
test_cpu_flag(int flag)57 static __always_inline bool test_cpu_flag(int flag)
58 {
59 return S390_lowcore.cpu_flags & (1UL << flag);
60 }
61
test_and_set_cpu_flag(int flag)62 static __always_inline bool test_and_set_cpu_flag(int flag)
63 {
64 if (test_cpu_flag(flag))
65 return true;
66 set_cpu_flag(flag);
67 return false;
68 }
69
test_and_clear_cpu_flag(int flag)70 static __always_inline bool test_and_clear_cpu_flag(int flag)
71 {
72 if (!test_cpu_flag(flag))
73 return false;
74 clear_cpu_flag(flag);
75 return true;
76 }
77
78 /*
79 * Test CIF flag of another CPU. The caller needs to ensure that
80 * CPU hotplug can not happen, e.g. by disabling preemption.
81 */
test_cpu_flag_of(int flag,int cpu)82 static __always_inline bool test_cpu_flag_of(int flag, int cpu)
83 {
84 struct lowcore *lc = lowcore_ptr[cpu];
85
86 return lc->cpu_flags & (1UL << flag);
87 }
88
89 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
90
get_cpu_id(struct cpuid * ptr)91 static inline void get_cpu_id(struct cpuid *ptr)
92 {
93 asm volatile("stidp %0" : "=Q" (*ptr));
94 }
95
96 void s390_adjust_jiffies(void);
97 void s390_update_cpu_mhz(void);
98 void cpu_detect_mhz_feature(void);
99
100 extern const struct seq_operations cpuinfo_op;
101 extern void execve_tail(void);
102 extern void __bpon(void);
103 unsigned long vdso_size(void);
104
105 /*
106 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
107 */
108
109 #define TASK_SIZE (test_thread_flag(TIF_31BIT) ? \
110 _REGION3_SIZE : TASK_SIZE_MAX)
111 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
112 (_REGION3_SIZE >> 1) : (_REGION2_SIZE >> 1))
113 #define TASK_SIZE_MAX (-PAGE_SIZE)
114
115 #define VDSO_BASE (STACK_TOP + PAGE_SIZE)
116 #define VDSO_LIMIT (test_thread_flag(TIF_31BIT) ? _REGION3_SIZE : _REGION2_SIZE)
117 #define STACK_TOP (VDSO_LIMIT - vdso_size() - PAGE_SIZE)
118 #define STACK_TOP_MAX (_REGION2_SIZE - vdso_size() - PAGE_SIZE)
119
120 #define HAVE_ARCH_PICK_MMAP_LAYOUT
121
122 /*
123 * Thread structure
124 */
125 struct thread_struct {
126 unsigned int acrs[NUM_ACRS];
127 unsigned long ksp; /* kernel stack pointer */
128 unsigned long user_timer; /* task cputime in user space */
129 unsigned long guest_timer; /* task cputime in kvm guest */
130 unsigned long system_timer; /* task cputime in kernel space */
131 unsigned long hardirq_timer; /* task cputime in hardirq context */
132 unsigned long softirq_timer; /* task cputime in softirq context */
133 const sys_call_ptr_t *sys_call_table; /* system call table address */
134 unsigned long gmap_addr; /* address of last gmap fault. */
135 unsigned int gmap_write_flag; /* gmap fault write indication */
136 unsigned int gmap_int_code; /* int code of last gmap fault */
137 unsigned int gmap_pfault; /* signal of a pending guest pfault */
138
139 /* Per-thread information related to debugging */
140 struct per_regs per_user; /* User specified PER registers */
141 struct per_event per_event; /* Cause of the last PER trap */
142 unsigned long per_flags; /* Flags to control debug behavior */
143 unsigned int system_call; /* system call number in signal */
144 unsigned long last_break; /* last breaking-event-address. */
145 /* pfault_wait is used to block the process on a pfault event */
146 unsigned long pfault_wait;
147 struct list_head list;
148 /* cpu runtime instrumentation */
149 struct runtime_instr_cb *ri_cb;
150 struct gs_cb *gs_cb; /* Current guarded storage cb */
151 struct gs_cb *gs_bc_cb; /* Broadcast guarded storage cb */
152 struct pgm_tdb trap_tdb; /* Transaction abort diagnose block */
153 /*
154 * Warning: 'fpu' is dynamically-sized. It *MUST* be at
155 * the end.
156 */
157 struct fpu fpu; /* FP and VX register save area */
158 };
159
160 /* Flag to disable transactions. */
161 #define PER_FLAG_NO_TE 1UL
162 /* Flag to enable random transaction aborts. */
163 #define PER_FLAG_TE_ABORT_RAND 2UL
164 /* Flag to specify random transaction abort mode:
165 * - abort each transaction at a random instruction before TEND if set.
166 * - abort random transactions at a random instruction if cleared.
167 */
168 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL
169
170 typedef struct thread_struct thread_struct;
171
172 #define ARCH_MIN_TASKALIGN 8
173
174 #define INIT_THREAD { \
175 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
176 .fpu.regs = (void *) init_task.thread.fpu.fprs, \
177 .last_break = 1, \
178 }
179
180 /*
181 * Do necessary setup to start up a new thread.
182 */
183 #define start_thread(regs, new_psw, new_stackp) do { \
184 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \
185 regs->psw.addr = new_psw; \
186 regs->gprs[15] = new_stackp; \
187 execve_tail(); \
188 } while (0)
189
190 #define start_thread31(regs, new_psw, new_stackp) do { \
191 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \
192 regs->psw.addr = new_psw; \
193 regs->gprs[15] = new_stackp; \
194 execve_tail(); \
195 } while (0)
196
197 /* Forward declaration, a strange C thing */
198 struct task_struct;
199 struct mm_struct;
200 struct seq_file;
201 struct pt_regs;
202
203 void show_registers(struct pt_regs *regs);
204 void show_cacheinfo(struct seq_file *m);
205
206 /* Free guarded storage control block */
207 void guarded_storage_release(struct task_struct *tsk);
208 void gs_load_bc_cb(struct pt_regs *regs);
209
210 unsigned long __get_wchan(struct task_struct *p);
211 #define task_pt_regs(tsk) ((struct pt_regs *) \
212 (task_stack_page(tsk) + THREAD_SIZE) - 1)
213 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
214 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
215
216 /* Has task runtime instrumentation enabled ? */
217 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
218
219 /* avoid using global register due to gcc bug in versions < 8.4 */
220 #define current_stack_pointer (__current_stack_pointer())
221
__current_stack_pointer(void)222 static __always_inline unsigned long __current_stack_pointer(void)
223 {
224 unsigned long sp;
225
226 asm volatile("lgr %0,15" : "=d" (sp));
227 return sp;
228 }
229
stap(void)230 static __always_inline unsigned short stap(void)
231 {
232 unsigned short cpu_address;
233
234 asm volatile("stap %0" : "=Q" (cpu_address));
235 return cpu_address;
236 }
237
238 #define cpu_relax() barrier()
239
240 #define ECAG_CACHE_ATTRIBUTE 0
241 #define ECAG_CPU_ATTRIBUTE 1
242
__ecag(unsigned int asi,unsigned char parm)243 static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
244 {
245 unsigned long val;
246
247 asm volatile("ecag %0,0,0(%1)" : "=d" (val) : "a" (asi << 8 | parm));
248 return val;
249 }
250
psw_set_key(unsigned int key)251 static inline void psw_set_key(unsigned int key)
252 {
253 asm volatile("spka 0(%0)" : : "d" (key));
254 }
255
256 /*
257 * Set PSW to specified value.
258 */
__load_psw(psw_t psw)259 static inline void __load_psw(psw_t psw)
260 {
261 asm volatile("lpswe %0" : : "Q" (psw) : "cc");
262 }
263
264 /*
265 * Set PSW mask to specified value, while leaving the
266 * PSW addr pointing to the next instruction.
267 */
__load_psw_mask(unsigned long mask)268 static __always_inline void __load_psw_mask(unsigned long mask)
269 {
270 unsigned long addr;
271 psw_t psw;
272
273 psw.mask = mask;
274
275 asm volatile(
276 " larl %0,1f\n"
277 " stg %0,%1\n"
278 " lpswe %2\n"
279 "1:"
280 : "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc");
281 }
282
283 /*
284 * Extract current PSW mask
285 */
__extract_psw(void)286 static inline unsigned long __extract_psw(void)
287 {
288 unsigned int reg1, reg2;
289
290 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
291 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
292 }
293
local_mcck_enable(void)294 static inline void local_mcck_enable(void)
295 {
296 __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
297 }
298
local_mcck_disable(void)299 static inline void local_mcck_disable(void)
300 {
301 __load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK);
302 }
303
304 /*
305 * Rewind PSW instruction address by specified number of bytes.
306 */
__rewind_psw(psw_t psw,unsigned long ilc)307 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
308 {
309 unsigned long mask;
310
311 mask = (psw.mask & PSW_MASK_EA) ? -1UL :
312 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
313 (1UL << 24) - 1;
314 return (psw.addr - ilc) & mask;
315 }
316
317 /*
318 * Function to drop a processor into disabled wait state
319 */
disabled_wait(void)320 static __always_inline void __noreturn disabled_wait(void)
321 {
322 psw_t psw;
323
324 psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
325 psw.addr = _THIS_IP_;
326 __load_psw(psw);
327 while (1);
328 }
329
330 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
331
332 extern int s390_isolate_bp(void);
333 extern int s390_isolate_bp_guest(void);
334
regs_irqs_disabled(struct pt_regs * regs)335 static __always_inline bool regs_irqs_disabled(struct pt_regs *regs)
336 {
337 return arch_irqs_disabled_flags(regs->psw.mask);
338 }
339
340 #endif /* __ASSEMBLY__ */
341
342 #endif /* __ASM_S390_PROCESSOR_H */
343