1 /*
2  * sh7724 MMCIF loader
3  *
4  * Copyright (C) 2010 Magnus Damm
5  *
6  * This file is subject to the terms and conditions of the GNU General Public
7  * License.  See the file "COPYING" in the main directory of this archive
8  * for more details.
9  */
10 
11 #include <linux/platform_data/sh_mmcif.h>
12 #include <mach/romimage.h>
13 
14 #define MMCIF_BASE      (void __iomem *)0xa4ca0000
15 
16 #define MSTPCR2		0xa4150038
17 #define PTWCR		0xa4050146
18 #define PTXCR		0xa4050148
19 #define PSELA		0xa405014e
20 #define PSELE		0xa4050156
21 #define HIZCRC		0xa405015c
22 #define DRVCRA		0xa405018a
23 
24 enum {
25 	MMCIF_PROGRESS_ENTER,
26 	MMCIF_PROGRESS_INIT,
27 	MMCIF_PROGRESS_LOAD,
28 	MMCIF_PROGRESS_DONE
29 };
30 
31 /* SH7724 specific MMCIF loader
32  *
33  * loads the romImage from an MMC card starting from block 512
34  * use the following line to write the romImage to an MMC card
35  * # dd if=arch/sh/boot/romImage of=/dev/sdx bs=512 seek=512
36  */
mmcif_loader(unsigned char * buf,unsigned long no_bytes)37 asmlinkage void mmcif_loader(unsigned char *buf, unsigned long no_bytes)
38 {
39 	mmcif_update_progress(MMCIF_PROGRESS_ENTER);
40 
41 	/* enable clock to the MMCIF hardware block */
42 	__raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2);
43 
44 	/* setup pins D7-D0 */
45 	__raw_writew(0x0000, PTWCR);
46 
47 	/* setup pins MMC_CLK, MMC_CMD */
48 	__raw_writew(__raw_readw(PTXCR) & ~0x000f, PTXCR);
49 
50 	/* select D3-D0 pin function */
51 	__raw_writew(__raw_readw(PSELA) & ~0x2000, PSELA);
52 
53 	/* select D7-D4 pin function */
54 	__raw_writew(__raw_readw(PSELE) & ~0x3000, PSELE);
55 
56 	/* disable Hi-Z for the MMC pins */
57 	__raw_writew(__raw_readw(HIZCRC) & ~0x0620, HIZCRC);
58 
59 	/* high drive capability for MMC pins */
60 	__raw_writew(__raw_readw(DRVCRA) | 0x3000, DRVCRA);
61 
62 	mmcif_update_progress(MMCIF_PROGRESS_INIT);
63 
64 	/* setup MMCIF hardware */
65 	sh_mmcif_boot_init(MMCIF_BASE);
66 
67 	mmcif_update_progress(MMCIF_PROGRESS_LOAD);
68 
69 	/* load kernel via MMCIF interface */
70 	sh_mmcif_boot_do_read(MMCIF_BASE, 512,
71 	                      (no_bytes + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS,
72 			      buf);
73 
74 	/* disable clock to the MMCIF hardware block */
75 	__raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2);
76 
77 	mmcif_update_progress(MMCIF_PROGRESS_DONE);
78 }
79