1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2019~2020 NXP
4  */
5 
6 #include <dt-bindings/firmware/imx/rsrc.h>
7 
8 #include "clk-scu.h"
9 
10 /* Keep sorted in the ascending order */
11 static u32 imx8dxl_clk_scu_rsrc_table[] = {
12 	IMX_SC_R_SPI_0,
13 	IMX_SC_R_SPI_1,
14 	IMX_SC_R_SPI_2,
15 	IMX_SC_R_SPI_3,
16 	IMX_SC_R_UART_0,
17 	IMX_SC_R_UART_1,
18 	IMX_SC_R_UART_2,
19 	IMX_SC_R_UART_3,
20 	IMX_SC_R_I2C_0,
21 	IMX_SC_R_I2C_1,
22 	IMX_SC_R_I2C_2,
23 	IMX_SC_R_I2C_3,
24 	IMX_SC_R_ADC_0,
25 	IMX_SC_R_FTM_0,
26 	IMX_SC_R_FTM_1,
27 	IMX_SC_R_CAN_0,
28 	IMX_SC_R_LCD_0,
29 	IMX_SC_R_LCD_0_PWM_0,
30 	IMX_SC_R_PWM_0,
31 	IMX_SC_R_PWM_1,
32 	IMX_SC_R_PWM_2,
33 	IMX_SC_R_PWM_3,
34 	IMX_SC_R_PWM_4,
35 	IMX_SC_R_PWM_5,
36 	IMX_SC_R_PWM_6,
37 	IMX_SC_R_PWM_7,
38 	IMX_SC_R_GPT_0,
39 	IMX_SC_R_GPT_1,
40 	IMX_SC_R_GPT_2,
41 	IMX_SC_R_GPT_3,
42 	IMX_SC_R_GPT_4,
43 	IMX_SC_R_FSPI_0,
44 	IMX_SC_R_FSPI_1,
45 	IMX_SC_R_SDHC_0,
46 	IMX_SC_R_SDHC_1,
47 	IMX_SC_R_SDHC_2,
48 	IMX_SC_R_ENET_0,
49 	IMX_SC_R_ENET_1,
50 	IMX_SC_R_MLB_0,
51 	IMX_SC_R_USB_1,
52 	IMX_SC_R_NAND,
53 	IMX_SC_R_M4_0_I2C,
54 	IMX_SC_R_M4_0_UART,
55 	IMX_SC_R_ELCDIF_PLL,
56 	IMX_SC_R_AUDIO_PLL_0,
57 	IMX_SC_R_AUDIO_PLL_1,
58 	IMX_SC_R_AUDIO_CLK_0,
59 	IMX_SC_R_AUDIO_CLK_1,
60 	IMX_SC_R_A35
61 };
62 
63 const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8dxl = {
64 	.rsrc = imx8dxl_clk_scu_rsrc_table,
65 	.num = ARRAY_SIZE(imx8dxl_clk_scu_rsrc_table),
66 };
67