1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
6 * Author: Jianhui Zhao <zhaojh329@gmail.com>
7 * Author: Daniel Golle <daniel@makrotopia.org>
8 */
9
10 #include <linux/clk-provider.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15
16 #include "clk-gate.h"
17 #include "clk-mtk.h"
18 #include "clk-mux.h"
19 #include "clk-pll.h"
20
21 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
22 #include <linux/clk.h>
23
24 #define MT7981_PLL_FMAX (2500UL * MHZ)
25 #define CON0_MT7981_RST_BAR BIT(27)
26
27 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
28 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
29 _div_table, _parent_name) \
30 { \
31 .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
32 .en_mask = _en_mask, .flags = _flags, \
33 .rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX, \
34 .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
35 .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \
36 .pcw_shift = _pcw_shift, .div_table = _div_table, \
37 .parent_name = _parent_name, \
38 }
39
40 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
41 _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \
42 PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
43 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \
44 "clkxtal")
45
46 static const struct mtk_pll_data plls[] = {
47 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
48 32, 0x0200, 4, 0, 0x0204, 0),
49 PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
50 0x0210, 4, 0, 0x0214, 0),
51 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
52 0x0220, 4, 0, 0x0224, 0),
53 PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,
54 0x0230, 4, 0, 0x0234, 0),
55 PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,
56 0x0240, 4, 0, 0x0244, 0),
57 PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32,
58 0x0250, 4, 0, 0x0254, 0),
59 PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32,
60 0x0260, 4, 0, 0x0264, 0),
61 PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
62 0x0278, 4, 0, 0x027C, 0),
63 };
64
65 static const struct of_device_id of_match_clk_mt7981_apmixed[] = {
66 { .compatible = "mediatek,mt7981-apmixedsys", },
67 { /* sentinel */ }
68 };
69
clk_mt7981_apmixed_probe(struct platform_device * pdev)70 static int clk_mt7981_apmixed_probe(struct platform_device *pdev)
71 {
72 struct clk_hw_onecell_data *clk_data;
73 struct device_node *node = pdev->dev.of_node;
74 int r;
75
76 clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
77 if (!clk_data)
78 return -ENOMEM;
79
80 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
81
82 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
83 if (r) {
84 pr_err("%s(): could not register clock provider: %d\n",
85 __func__, r);
86 goto free_apmixed_data;
87 }
88 return r;
89
90 free_apmixed_data:
91 mtk_free_clk_data(clk_data);
92 return r;
93 }
94
95 static struct platform_driver clk_mt7981_apmixed_drv = {
96 .probe = clk_mt7981_apmixed_probe,
97 .driver = {
98 .name = "clk-mt7981-apmixed",
99 .of_match_table = of_match_clk_mt7981_apmixed,
100 },
101 };
102 builtin_platform_driver(clk_mt7981_apmixed_drv);
103