1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2021 MediaTek Inc.
4  * Author: Sam Shih <sam.shih@mediatek.com>
5  * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
6  */
7 
8 #include <linux/clk-provider.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include "clk-mtk.h"
14 #include "clk-gate.h"
15 #include "clk-mux.h"
16 
17 #include <dt-bindings/clock/mt7986-clk.h>
18 #include <linux/clk.h>
19 
20 static DEFINE_SPINLOCK(mt7986_clk_lock);
21 
22 static const struct mtk_fixed_factor infra_divs[] = {
23 	FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", "sysaxi_sel", 1, 2),
24 };
25 
26 static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
27 							     "uart_sel" };
28 
29 static const char *const infra_spi_parents[] __initconst = { "i2c_sel",
30 							     "spi_sel" };
31 
32 static const char *const infra_pwm_bsel_parents[] __initconst = {
33 	"top_rtc_32p7k", "csw_f26m_sel", "infra_sysaxi_d2", "pwm_sel"
34 };
35 
36 static const char *const infra_pcie_parents[] __initconst = {
37 	"top_rtc_32p7k", "csw_f26m_sel", "top_xtal", "pextp_tl_ck_sel"
38 };
39 
40 static const struct mtk_mux infra_muxes[] = {
41 	/* MODULE_CLK_SEL_0 */
42 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
43 			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
44 			     -1, -1, -1),
45 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
46 			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
47 			     -1, -1, -1),
48 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
49 			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
50 			     -1, -1, -1),
51 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
52 			     infra_spi_parents, 0x0018, 0x0010, 0x0014, 4, 1,
53 			     -1, -1, -1),
54 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
55 			     infra_spi_parents, 0x0018, 0x0010, 0x0014, 5, 1,
56 			     -1, -1, -1),
57 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
58 			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 9,
59 			     2, -1, -1, -1),
60 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
61 			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 11,
62 			     2, -1, -1, -1),
63 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
64 			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
65 			     2, -1, -1, -1),
66 	/* MODULE_CLK_SEL_1 */
67 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
68 			     infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
69 			     -1, -1, -1),
70 };
71 
72 static const struct mtk_gate_regs infra0_cg_regs = {
73 	.set_ofs = 0x40,
74 	.clr_ofs = 0x44,
75 	.sta_ofs = 0x48,
76 };
77 
78 static const struct mtk_gate_regs infra1_cg_regs = {
79 	.set_ofs = 0x50,
80 	.clr_ofs = 0x54,
81 	.sta_ofs = 0x58,
82 };
83 
84 static const struct mtk_gate_regs infra2_cg_regs = {
85 	.set_ofs = 0x60,
86 	.clr_ofs = 0x64,
87 	.sta_ofs = 0x68,
88 };
89 
90 #define GATE_INFRA0(_id, _name, _parent, _shift)                               \
91 	{                                                                      \
92 		.id = _id, .name = _name, .parent_name = _parent,              \
93 		.regs = &infra0_cg_regs, .shift = _shift,                      \
94 		.ops = &mtk_clk_gate_ops_setclr,                               \
95 	}
96 
97 #define GATE_INFRA1(_id, _name, _parent, _shift)                               \
98 	{                                                                      \
99 		.id = _id, .name = _name, .parent_name = _parent,              \
100 		.regs = &infra1_cg_regs, .shift = _shift,                      \
101 		.ops = &mtk_clk_gate_ops_setclr,                               \
102 	}
103 
104 #define GATE_INFRA2(_id, _name, _parent, _shift)                               \
105 	{                                                                      \
106 		.id = _id, .name = _name, .parent_name = _parent,              \
107 		.regs = &infra2_cg_regs, .shift = _shift,                      \
108 		.ops = &mtk_clk_gate_ops_setclr,                               \
109 	}
110 
111 static const struct mtk_gate infra_clks[] = {
112 	/* INFRA0 */
113 	GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_sysaxi_d2", 0),
114 	GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_sysaxi_d2", 1),
115 	GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
116 	GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
117 	GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
118 	GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi_sel", 6),
119 	GATE_INFRA0(CLK_INFRA_EIP97_CK, "infra_eip97", "eip_b_sel", 7),
120 	GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi_sel", 8),
121 	GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
122 	GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l_sel", 10),
123 	GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys_sel", 11),
124 	GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner_sel", 13),
125 	GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
126 		    14),
127 	GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_sysaxi_d2", 15),
128 	GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_sysaxi_d2", 16),
129 	GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_sysaxi_d2", 24),
130 	GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
131 	GATE_INFRA0(CLK_INFRA_TRNG_CK, "infra_trng", "sysaxi_sel", 26),
132 	/* INFRA1 */
133 	GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
134 	GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_sel", 1),
135 	GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
136 	GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
137 	GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
138 	GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x_sel", 8),
139 	GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_sel", 9),
140 	GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_sysaxi_d2",
141 		    10),
142 	GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
143 	GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
144 	GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_sysaxi_d2",
145 		    13),
146 	GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_sysaxi_d2",
147 		    14),
148 	GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "top_rtc_32k", 15),
149 	GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_416m_sel", 16),
150 	GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_250m_sel",
151 		    17),
152 	GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi_sel",
153 		    18),
154 	GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_sysaxi_d2",
155 		    19),
156 	GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
157 	GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m_sel", 21),
158 	GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x_sel", 23),
159 	/* INFRA2 */
160 	GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi_sel", 0),
161 	GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "infra_sysaxi_d2",
162 		    1),
163 	GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys_sel", 2),
164 	GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_sel", 3),
165 	GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl_ck_sel", 12),
166 	GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "top_xtal",
167 		    13),
168 	GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m_sel", 14),
169 	GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi_sel", 15),
170 };
171 
clk_mt7986_infracfg_probe(struct platform_device * pdev)172 static int clk_mt7986_infracfg_probe(struct platform_device *pdev)
173 {
174 	struct clk_hw_onecell_data *clk_data;
175 	struct device_node *node = pdev->dev.of_node;
176 	int r;
177 	void __iomem *base;
178 	int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) +
179 		 ARRAY_SIZE(infra_clks);
180 
181 	base = of_iomap(node, 0);
182 	if (!base) {
183 		pr_err("%s(): ioremap failed\n", __func__);
184 		return -ENOMEM;
185 	}
186 
187 	clk_data = mtk_alloc_clk_data(nr);
188 
189 	if (!clk_data)
190 		return -ENOMEM;
191 
192 	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
193 	mtk_clk_register_muxes(&pdev->dev, infra_muxes,
194 			       ARRAY_SIZE(infra_muxes), node,
195 			       &mt7986_clk_lock, clk_data);
196 	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
197 			       ARRAY_SIZE(infra_clks), clk_data);
198 
199 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
200 	if (r) {
201 		pr_err("%s(): could not register clock provider: %d\n",
202 		       __func__, r);
203 		goto free_infracfg_data;
204 	}
205 	return r;
206 
207 free_infracfg_data:
208 	mtk_free_clk_data(clk_data);
209 	return r;
210 
211 }
212 
213 static const struct of_device_id of_match_clk_mt7986_infracfg[] = {
214 	{ .compatible = "mediatek,mt7986-infracfg", },
215 	{}
216 };
217 
218 static struct platform_driver clk_mt7986_infracfg_drv = {
219 	.probe = clk_mt7986_infracfg_probe,
220 	.driver = {
221 		.name = "clk-mt7986-infracfg",
222 		.of_match_table = of_match_clk_mt7986_infracfg,
223 	},
224 };
225 builtin_platform_driver(clk_mt7986_infracfg_drv);
226