1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // Copyright (c) 2022 MediaTek Inc.
4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
5
6 #include <linux/clk-provider.h>
7 #include <linux/platform_device.h>
8 #include <dt-bindings/clock/mt8186-clk.h>
9
10 #include "clk-mtk.h"
11
12 static const char * const mcu_armpll_ll_parents[] = {
13 "clk26m",
14 "armpll_ll",
15 "mainpll",
16 "univpll_d2"
17 };
18
19 static const char * const mcu_armpll_bl_parents[] = {
20 "clk26m",
21 "armpll_bl",
22 "mainpll",
23 "univpll_d2"
24 };
25
26 static const char * const mcu_armpll_bus_parents[] = {
27 "clk26m",
28 "ccipll",
29 "mainpll",
30 "univpll_d2"
31 };
32
33 /*
34 * We only configure the CPU muxes when adjust CPU frequency in MediaTek CPUFreq Driver.
35 * Other fields like divider always keep the same value. (set once in bootloader)
36 */
37 static struct mtk_composite mcu_muxes[] = {
38 /* CPU_PLLDIV_CFG0 */
39 MUX(CLK_MCU_ARMPLL_LL_SEL, "mcu_armpll_ll_sel", mcu_armpll_ll_parents, 0x2A0, 9, 2),
40 /* CPU_PLLDIV_CFG1 */
41 MUX(CLK_MCU_ARMPLL_BL_SEL, "mcu_armpll_bl_sel", mcu_armpll_bl_parents, 0x2A4, 9, 2),
42 /* BUS_PLLDIV_CFG */
43 MUX(CLK_MCU_ARMPLL_BUS_SEL, "mcu_armpll_bus_sel", mcu_armpll_bus_parents, 0x2E0, 9, 2),
44 };
45
46 static const struct of_device_id of_match_clk_mt8186_mcu[] = {
47 { .compatible = "mediatek,mt8186-mcusys", },
48 {}
49 };
50
clk_mt8186_mcu_probe(struct platform_device * pdev)51 static int clk_mt8186_mcu_probe(struct platform_device *pdev)
52 {
53 struct clk_hw_onecell_data *clk_data;
54 struct device_node *node = pdev->dev.of_node;
55 int r;
56 void __iomem *base;
57
58 clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
59 if (!clk_data)
60 return -ENOMEM;
61
62 base = devm_platform_ioremap_resource(pdev, 0);
63 if (IS_ERR(base)) {
64 r = PTR_ERR(base);
65 goto free_mcu_data;
66 }
67
68 r = mtk_clk_register_composites(&pdev->dev, mcu_muxes,
69 ARRAY_SIZE(mcu_muxes), base,
70 NULL, clk_data);
71 if (r)
72 goto free_mcu_data;
73
74 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
75 if (r)
76 goto unregister_composite_muxes;
77
78 platform_set_drvdata(pdev, clk_data);
79
80 return r;
81
82 unregister_composite_muxes:
83 mtk_clk_unregister_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), clk_data);
84 free_mcu_data:
85 mtk_free_clk_data(clk_data);
86 return r;
87 }
88
clk_mt8186_mcu_remove(struct platform_device * pdev)89 static int clk_mt8186_mcu_remove(struct platform_device *pdev)
90 {
91 struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
92 struct device_node *node = pdev->dev.of_node;
93
94 of_clk_del_provider(node);
95 mtk_clk_unregister_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), clk_data);
96 mtk_free_clk_data(clk_data);
97
98 return 0;
99 }
100
101 static struct platform_driver clk_mt8186_mcu_drv = {
102 .probe = clk_mt8186_mcu_probe,
103 .remove = clk_mt8186_mcu_remove,
104 .driver = {
105 .name = "clk-mt8186-mcu",
106 .of_match_table = of_match_clk_mt8186_mcu,
107 },
108 };
109 builtin_platform_driver(clk_mt8186_mcu_drv);
110