1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *  Copyright 2011-2012 Calxeda, Inc.
4  *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
5  *
6  * Based from clk-highbank.c
7  */
8 #include <linux/slab.h>
9 #include <linux/clk-provider.h>
10 #include <linux/io.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/of.h>
13 #include <linux/regmap.h>
14 
15 #include "clk.h"
16 
17 #define SOCFPGA_L4_MP_CLK		"l4_mp_clk"
18 #define SOCFPGA_L4_SP_CLK		"l4_sp_clk"
19 #define SOCFPGA_NAND_CLK		"nand_clk"
20 #define SOCFPGA_NAND_X_CLK		"nand_x_clk"
21 #define SOCFPGA_MMC_CLK			"sdmmc_clk"
22 #define SOCFPGA_GPIO_DB_CLK_OFFSET	0xA8
23 
24 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
25 
26 /* SDMMC Group for System Manager defines */
27 #define SYSMGR_SDMMCGRP_CTRL_OFFSET    0x108
28 
socfpga_clk_get_parent(struct clk_hw * hwclk)29 static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
30 {
31 	u32 l4_src;
32 	u32 perpll_src;
33 	const char *name = clk_hw_get_name(hwclk);
34 
35 	if (streq(name, SOCFPGA_L4_MP_CLK)) {
36 		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
37 		return l4_src & 0x1;
38 	}
39 	if (streq(name, SOCFPGA_L4_SP_CLK)) {
40 		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
41 		return !!(l4_src & 2);
42 	}
43 
44 	perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
45 	if (streq(name, SOCFPGA_MMC_CLK))
46 		return perpll_src & 0x3;
47 	if (streq(name, SOCFPGA_NAND_CLK) ||
48 	    streq(name, SOCFPGA_NAND_X_CLK))
49 		return (perpll_src >> 2) & 3;
50 
51 	/* QSPI clock */
52 	return (perpll_src >> 4) & 3;
53 
54 }
55 
socfpga_clk_set_parent(struct clk_hw * hwclk,u8 parent)56 static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
57 {
58 	u32 src_reg;
59 	const char *name = clk_hw_get_name(hwclk);
60 
61 	if (streq(name, SOCFPGA_L4_MP_CLK)) {
62 		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
63 		src_reg &= ~0x1;
64 		src_reg |= parent;
65 		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
66 	} else if (streq(name, SOCFPGA_L4_SP_CLK)) {
67 		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
68 		src_reg &= ~0x2;
69 		src_reg |= (parent << 1);
70 		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
71 	} else {
72 		src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
73 		if (streq(name, SOCFPGA_MMC_CLK)) {
74 			src_reg &= ~0x3;
75 			src_reg |= parent;
76 		} else if (streq(name, SOCFPGA_NAND_CLK) ||
77 			streq(name, SOCFPGA_NAND_X_CLK)) {
78 			src_reg &= ~0xC;
79 			src_reg |= (parent << 2);
80 		} else {/* QSPI clock */
81 			src_reg &= ~0x30;
82 			src_reg |= (parent << 4);
83 		}
84 		writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
85 	}
86 
87 	return 0;
88 }
89 
socfpga_clk_recalc_rate(struct clk_hw * hwclk,unsigned long parent_rate)90 static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
91 	unsigned long parent_rate)
92 {
93 	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
94 	u32 div = 1, val;
95 
96 	if (socfpgaclk->fixed_div)
97 		div = socfpgaclk->fixed_div;
98 	else if (socfpgaclk->div_reg) {
99 		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
100 		val &= GENMASK(socfpgaclk->width - 1, 0);
101 		/* Check for GPIO_DB_CLK by its offset */
102 		if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
103 			div = val + 1;
104 		else
105 			div = (1 << val);
106 	}
107 
108 	return parent_rate / div;
109 }
110 
111 static struct clk_ops gateclk_ops = {
112 	.recalc_rate = socfpga_clk_recalc_rate,
113 	.get_parent = socfpga_clk_get_parent,
114 	.set_parent = socfpga_clk_set_parent,
115 };
116 
socfpga_gate_init(struct device_node * node)117 void __init socfpga_gate_init(struct device_node *node)
118 {
119 	u32 clk_gate[2];
120 	u32 div_reg[3];
121 	u32 fixed_div;
122 	struct clk_hw *hw_clk;
123 	struct socfpga_gate_clk *socfpga_clk;
124 	const char *clk_name = node->name;
125 	const char *parent_name[SOCFPGA_MAX_PARENTS];
126 	struct clk_init_data init;
127 	struct clk_ops *ops;
128 	int rc;
129 	int err;
130 
131 	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
132 	if (WARN_ON(!socfpga_clk))
133 		return;
134 
135 	ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL);
136 	if (WARN_ON(!ops)) {
137 		kfree(socfpga_clk);
138 		return;
139 	}
140 
141 	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
142 	if (rc)
143 		clk_gate[0] = 0;
144 
145 	if (clk_gate[0]) {
146 		socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
147 		socfpga_clk->hw.bit_idx = clk_gate[1];
148 
149 		ops->enable = clk_gate_ops.enable;
150 		ops->disable = clk_gate_ops.disable;
151 	}
152 
153 	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
154 	if (rc)
155 		socfpga_clk->fixed_div = 0;
156 	else
157 		socfpga_clk->fixed_div = fixed_div;
158 
159 	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
160 	if (!rc) {
161 		socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
162 		socfpga_clk->shift = div_reg[1];
163 		socfpga_clk->width = div_reg[2];
164 	} else {
165 		socfpga_clk->div_reg = NULL;
166 	}
167 
168 	of_property_read_string(node, "clock-output-names", &clk_name);
169 
170 	init.name = clk_name;
171 	init.ops = ops;
172 	init.flags = 0;
173 
174 	init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
175 	if (init.num_parents < 2) {
176 		ops->get_parent = NULL;
177 		ops->set_parent = NULL;
178 	}
179 
180 	init.parent_names = parent_name;
181 	socfpga_clk->hw.hw.init = &init;
182 
183 	hw_clk = &socfpga_clk->hw.hw;
184 
185 	err = clk_hw_register(NULL, hw_clk);
186 	if (err) {
187 		kfree(ops);
188 		kfree(socfpga_clk);
189 		return;
190 	}
191 	rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
192 	if (WARN_ON(rc))
193 		return;
194 }
195