1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Freescale MPC85xx Memory Controller kernel module
4  * Author: Dave Jiang <djiang@mvista.com>
5  *
6  * 2006-2007 (c) MontaVista Software, Inc.
7  */
8 #ifndef _MPC85XX_EDAC_H_
9 #define _MPC85XX_EDAC_H_
10 
11 #define MPC85XX_REVISION " Ver: 2.0.0"
12 #define EDAC_MOD_STR	"MPC85xx_edac"
13 
14 #define mpc85xx_printk(level, fmt, arg...) \
15 	edac_printk(level, "MPC85xx", fmt, ##arg)
16 
17 /*
18  * L2 Err defines
19  */
20 #define MPC85XX_L2_ERRINJHI	0x0000
21 #define MPC85XX_L2_ERRINJLO	0x0004
22 #define MPC85XX_L2_ERRINJCTL	0x0008
23 #define MPC85XX_L2_CAPTDATAHI	0x0020
24 #define MPC85XX_L2_CAPTDATALO	0x0024
25 #define MPC85XX_L2_CAPTECC	0x0028
26 #define MPC85XX_L2_ERRDET	0x0040
27 #define MPC85XX_L2_ERRDIS	0x0044
28 #define MPC85XX_L2_ERRINTEN	0x0048
29 #define MPC85XX_L2_ERRATTR	0x004c
30 #define MPC85XX_L2_ERRADDR	0x0050
31 #define MPC85XX_L2_ERRCTL	0x0058
32 
33 /* Error Interrupt Enable */
34 #define L2_EIE_L2CFGINTEN	0x1
35 #define L2_EIE_SBECCINTEN	0x4
36 #define L2_EIE_MBECCINTEN	0x8
37 #define L2_EIE_TPARINTEN	0x10
38 #define L2_EIE_MASK	(L2_EIE_L2CFGINTEN | L2_EIE_SBECCINTEN | \
39 			L2_EIE_MBECCINTEN | L2_EIE_TPARINTEN)
40 
41 /* Error Detect */
42 #define L2_EDE_L2CFGERR		0x1
43 #define L2_EDE_SBECCERR		0x4
44 #define L2_EDE_MBECCERR		0x8
45 #define L2_EDE_TPARERR		0x10
46 #define L2_EDE_MULL2ERR		0x80000000
47 
48 #define L2_EDE_CE_MASK	L2_EDE_SBECCERR
49 #define L2_EDE_UE_MASK	(L2_EDE_L2CFGERR | L2_EDE_MBECCERR | \
50 			L2_EDE_TPARERR)
51 #define L2_EDE_MASK	(L2_EDE_L2CFGERR | L2_EDE_SBECCERR | \
52 			L2_EDE_MBECCERR | L2_EDE_TPARERR | L2_EDE_MULL2ERR)
53 
54 /*
55  * PCI Err defines
56  */
57 #define PCI_EDE_TOE			0x00000001
58 #define PCI_EDE_SCM			0x00000002
59 #define PCI_EDE_IRMSV			0x00000004
60 #define PCI_EDE_ORMSV			0x00000008
61 #define PCI_EDE_OWMSV			0x00000010
62 #define PCI_EDE_TGT_ABRT		0x00000020
63 #define PCI_EDE_MST_ABRT		0x00000040
64 #define PCI_EDE_TGT_PERR		0x00000080
65 #define PCI_EDE_MST_PERR		0x00000100
66 #define PCI_EDE_RCVD_SERR		0x00000200
67 #define PCI_EDE_ADDR_PERR		0x00000400
68 #define PCI_EDE_MULTI_ERR		0x80000000
69 
70 #define PCI_EDE_PERR_MASK	(PCI_EDE_TGT_PERR | PCI_EDE_MST_PERR | \
71 				PCI_EDE_ADDR_PERR)
72 
73 #define MPC85XX_PCI_ERR_DR		0x0000
74 #define MPC85XX_PCI_ERR_CAP_DR		0x0004
75 #define MPC85XX_PCI_ERR_EN		0x0008
76 #define   PEX_ERR_ICCAIE_EN_BIT		0x00020000
77 #define MPC85XX_PCI_ERR_ATTRIB		0x000c
78 #define MPC85XX_PCI_ERR_ADDR		0x0010
79 #define   PEX_ERR_ICCAD_DISR_BIT	0x00020000
80 #define MPC85XX_PCI_ERR_EXT_ADDR	0x0014
81 #define MPC85XX_PCI_ERR_DL		0x0018
82 #define MPC85XX_PCI_ERR_DH		0x001c
83 #define MPC85XX_PCI_GAS_TIMR		0x0020
84 #define MPC85XX_PCI_PCIX_TIMR		0x0024
85 #define MPC85XX_PCIE_ERR_CAP_R0		0x0028
86 #define MPC85XX_PCIE_ERR_CAP_R1		0x002c
87 #define MPC85XX_PCIE_ERR_CAP_R2		0x0030
88 #define MPC85XX_PCIE_ERR_CAP_R3		0x0034
89 
90 struct mpc85xx_l2_pdata {
91 	char *name;
92 	int edac_idx;
93 	void __iomem *l2_vbase;
94 	int irq;
95 };
96 
97 struct mpc85xx_pci_pdata {
98 	char *name;
99 	bool is_pcie;
100 	int edac_idx;
101 	void __iomem *pci_vbase;
102 	int irq;
103 };
104 
105 #endif
106