1 /*
2  * Copyright 2021 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef DAL_DC_316_SMU_H_
27 #define DAL_DC_316_SMU_H_
28 #include "os_types.h"
29 
30 #define PMFW_DRIVER_IF_VERSION 4
31 
32 #define NUM_DCFCLK_DPM_LEVELS   8
33 #define NUM_DISPCLK_DPM_LEVELS  8
34 #define NUM_DPPCLK_DPM_LEVELS   8
35 #define NUM_SOCCLK_DPM_LEVELS   8
36 #define NUM_VCN_DPM_LEVELS      8
37 #define NUM_SOC_VOLTAGE_LEVELS  8
38 #define NUM_DF_PSTATE_LEVELS    4
39 
40 typedef struct {
41   uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
42   uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
43   uint16_t MinMclk;
44   uint16_t MaxMclk;
45   uint8_t  WmSetting;
46   uint8_t  WmType;  // Used for normal pstate change or memory retraining
47   uint8_t  Padding[2];
48 } WatermarkRowGeneric_t;
49 
50 #define NUM_WM_RANGES 4
51 #define WM_PSTATE_CHG 0
52 #define WM_RETRAINING 1
53 
54 typedef enum {
55   WM_SOCCLK = 0,
56   WM_DCFCLK,
57   WM_COUNT,
58 } WM_CLOCK_e;
59 
60 typedef enum{
61   WCK_RATIO_1_1 = 0,  // DDR5, Wck:ck is always 1:1;
62   WCK_RATIO_1_2,
63   WCK_RATIO_1_4,
64   WCK_RATIO_MAX
65 } WCK_RATIO_e;
66 
67 typedef struct {
68   uint32_t FClk;
69   uint32_t MemClk;
70   uint32_t Voltage;
71   uint8_t  WckRatio;
72   uint8_t  Spare[3];
73 } DfPstateTable_t;
74 
75 //Freq in MHz
76 //Voltage in milli volts with 2 fractional bits
77 typedef struct {
78   uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
79   uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
80   uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
81   uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
82   uint32_t VClocks[NUM_VCN_DPM_LEVELS];
83   uint32_t DClocks[NUM_VCN_DPM_LEVELS];
84   uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
85   DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
86   uint8_t  NumDcfClkLevelsEnabled;
87   uint8_t  NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
88   uint8_t  NumSocClkLevelsEnabled;
89   uint8_t  VcnClkLevelsEnabled;     //Applies to both Vclk and Dclk
90   uint8_t  NumDfPstatesEnabled;
91   uint8_t  spare[3];
92   uint32_t MinGfxClk;
93   uint32_t MaxGfxClk;
94 } DpmClocks_316_t;
95 
96 struct dcn316_watermarks {
97   // Watermarks
98   WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
99   uint32_t MmHubPadding[7]; // SMU internal use
100 };
101 
102 struct dcn316_smu_dpm_clks {
103 	DpmClocks_316_t *dpm_clks;
104 	union large_integer mc_address;
105 };
106 
107 #define TABLE_WATERMARKS         1 // Called by DAL through VBIOS
108 #define TABLE_DPMCLOCKS          4 // Called by Driver and VBIOS
109 
110 struct display_idle_optimization {
111 	unsigned int df_request_disabled : 1;
112 	unsigned int phy_ref_clk_off     : 1;
113 	unsigned int s0i2_rdy            : 1;
114 	unsigned int reserved            : 29;
115 };
116 
117 union display_idle_optimization_u {
118 	struct display_idle_optimization idle_info;
119 	uint32_t data;
120 };
121 
122 int dcn316_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
123 int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
124 int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
125 int dcn316_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
126 int dcn316_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
127 void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
128 void dcn316_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
129 void dcn316_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
130 void dcn316_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
131 void dcn316_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
132 void dcn316_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
133 void dcn316_smu_request_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
134 void dcn316_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
135 void dcn316_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
136 int dcn316_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr);
137 int dcn316_smu_get_smu_fclk(struct clk_mgr_internal *clk_mgr);
138 
139 #endif /* DAL_DC_316_SMU_H_ */
140