1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2014 Traphandler
4  * Copyright (C) 2014 Free Electrons
5  *
6  * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
7  * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
8  */
9 
10 #include <linux/clk.h>
11 #include <linux/media-bus-format.h>
12 #include <linux/mfd/atmel-hlcdc.h>
13 #include <linux/pinctrl/consumer.h>
14 #include <linux/pm.h>
15 #include <linux/pm_runtime.h>
16 
17 #include <video/videomode.h>
18 
19 #include <drm/drm_atomic.h>
20 #include <drm/drm_atomic_helper.h>
21 #include <drm/drm_crtc.h>
22 #include <drm/drm_modeset_helper_vtables.h>
23 #include <drm/drm_probe_helper.h>
24 #include <drm/drm_vblank.h>
25 
26 #include "atmel_hlcdc_dc.h"
27 
28 /**
29  * struct atmel_hlcdc_crtc_state - Atmel HLCDC CRTC state structure
30  *
31  * @base: base CRTC state
32  * @output_mode: RGBXXX output mode
33  */
34 struct atmel_hlcdc_crtc_state {
35 	struct drm_crtc_state base;
36 	unsigned int output_mode;
37 };
38 
39 static inline struct atmel_hlcdc_crtc_state *
drm_crtc_state_to_atmel_hlcdc_crtc_state(struct drm_crtc_state * state)40 drm_crtc_state_to_atmel_hlcdc_crtc_state(struct drm_crtc_state *state)
41 {
42 	return container_of(state, struct atmel_hlcdc_crtc_state, base);
43 }
44 
45 /**
46  * struct atmel_hlcdc_crtc - Atmel HLCDC CRTC structure
47  *
48  * @base: base DRM CRTC structure
49  * @dc: pointer to the atmel_hlcdc structure provided by the MFD device
50  * @event: pointer to the current page flip event
51  * @id: CRTC id (returned by drm_crtc_index)
52  */
53 struct atmel_hlcdc_crtc {
54 	struct drm_crtc base;
55 	struct atmel_hlcdc_dc *dc;
56 	struct drm_pending_vblank_event *event;
57 	int id;
58 };
59 
60 static inline struct atmel_hlcdc_crtc *
drm_crtc_to_atmel_hlcdc_crtc(struct drm_crtc * crtc)61 drm_crtc_to_atmel_hlcdc_crtc(struct drm_crtc *crtc)
62 {
63 	return container_of(crtc, struct atmel_hlcdc_crtc, base);
64 }
65 
atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc * c)66 static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c)
67 {
68 	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
69 	struct regmap *regmap = crtc->dc->hlcdc->regmap;
70 	struct drm_display_mode *adj = &c->state->adjusted_mode;
71 	struct atmel_hlcdc_crtc_state *state;
72 	unsigned long mode_rate;
73 	struct videomode vm;
74 	unsigned long prate;
75 	unsigned int mask = ATMEL_HLCDC_CLKDIV_MASK | ATMEL_HLCDC_CLKPOL;
76 	unsigned int cfg = 0;
77 	int div, ret;
78 
79 	ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
80 	if (ret)
81 		return;
82 
83 	vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay;
84 	vm.vback_porch = adj->crtc_vtotal - adj->crtc_vsync_end;
85 	vm.vsync_len = adj->crtc_vsync_end - adj->crtc_vsync_start;
86 	vm.hfront_porch = adj->crtc_hsync_start - adj->crtc_hdisplay;
87 	vm.hback_porch = adj->crtc_htotal - adj->crtc_hsync_end;
88 	vm.hsync_len = adj->crtc_hsync_end - adj->crtc_hsync_start;
89 
90 	regmap_write(regmap, ATMEL_HLCDC_CFG(1),
91 		     (vm.hsync_len - 1) | ((vm.vsync_len - 1) << 16));
92 
93 	regmap_write(regmap, ATMEL_HLCDC_CFG(2),
94 		     (vm.vfront_porch - 1) | (vm.vback_porch << 16));
95 
96 	regmap_write(regmap, ATMEL_HLCDC_CFG(3),
97 		     (vm.hfront_porch - 1) | ((vm.hback_porch - 1) << 16));
98 
99 	regmap_write(regmap, ATMEL_HLCDC_CFG(4),
100 		     (adj->crtc_hdisplay - 1) |
101 		     ((adj->crtc_vdisplay - 1) << 16));
102 
103 	prate = clk_get_rate(crtc->dc->hlcdc->sys_clk);
104 	mode_rate = adj->crtc_clock * 1000;
105 	if (!crtc->dc->desc->fixed_clksrc) {
106 		prate *= 2;
107 		cfg |= ATMEL_HLCDC_CLKSEL;
108 		mask |= ATMEL_HLCDC_CLKSEL;
109 	}
110 
111 	div = DIV_ROUND_UP(prate, mode_rate);
112 	if (div < 2) {
113 		div = 2;
114 	} else if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK) {
115 		/* The divider ended up too big, try a lower base rate. */
116 		cfg &= ~ATMEL_HLCDC_CLKSEL;
117 		prate /= 2;
118 		div = DIV_ROUND_UP(prate, mode_rate);
119 		if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK)
120 			div = ATMEL_HLCDC_CLKDIV_MASK;
121 	} else {
122 		int div_low = prate / mode_rate;
123 
124 		if (div_low >= 2 &&
125 		    (10 * (prate / div_low - mode_rate) <
126 		     (mode_rate - prate / div)))
127 			/*
128 			 * At least 10 times better when using a higher
129 			 * frequency than requested, instead of a lower.
130 			 * So, go with that.
131 			 */
132 			div = div_low;
133 	}
134 
135 	cfg |= ATMEL_HLCDC_CLKDIV(div);
136 
137 	regmap_update_bits(regmap, ATMEL_HLCDC_CFG(0), mask, cfg);
138 
139 	state = drm_crtc_state_to_atmel_hlcdc_crtc_state(c->state);
140 	cfg = state->output_mode << 8;
141 
142 	if (adj->flags & DRM_MODE_FLAG_NVSYNC)
143 		cfg |= ATMEL_HLCDC_VSPOL;
144 
145 	if (adj->flags & DRM_MODE_FLAG_NHSYNC)
146 		cfg |= ATMEL_HLCDC_HSPOL;
147 
148 	regmap_update_bits(regmap, ATMEL_HLCDC_CFG(5),
149 			   ATMEL_HLCDC_HSPOL | ATMEL_HLCDC_VSPOL |
150 			   ATMEL_HLCDC_VSPDLYS | ATMEL_HLCDC_VSPDLYE |
151 			   ATMEL_HLCDC_DISPPOL | ATMEL_HLCDC_DISPDLY |
152 			   ATMEL_HLCDC_VSPSU | ATMEL_HLCDC_VSPHO |
153 			   ATMEL_HLCDC_GUARDTIME_MASK | ATMEL_HLCDC_MODE_MASK,
154 			   cfg);
155 
156 	clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
157 }
158 
159 static enum drm_mode_status
atmel_hlcdc_crtc_mode_valid(struct drm_crtc * c,const struct drm_display_mode * mode)160 atmel_hlcdc_crtc_mode_valid(struct drm_crtc *c,
161 			    const struct drm_display_mode *mode)
162 {
163 	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
164 
165 	return atmel_hlcdc_dc_mode_valid(crtc->dc, mode);
166 }
167 
atmel_hlcdc_crtc_atomic_disable(struct drm_crtc * c,struct drm_atomic_state * state)168 static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c,
169 					    struct drm_atomic_state *state)
170 {
171 	struct drm_device *dev = c->dev;
172 	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
173 	struct regmap *regmap = crtc->dc->hlcdc->regmap;
174 	unsigned int status;
175 
176 	drm_crtc_vblank_off(c);
177 
178 	pm_runtime_get_sync(dev->dev);
179 
180 	regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_DISP);
181 	while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
182 	       (status & ATMEL_HLCDC_DISP))
183 		cpu_relax();
184 
185 	regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_SYNC);
186 	while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
187 	       (status & ATMEL_HLCDC_SYNC))
188 		cpu_relax();
189 
190 	regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PIXEL_CLK);
191 	while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
192 	       (status & ATMEL_HLCDC_PIXEL_CLK))
193 		cpu_relax();
194 
195 	clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
196 	pinctrl_pm_select_sleep_state(dev->dev);
197 
198 	pm_runtime_allow(dev->dev);
199 
200 	pm_runtime_put_sync(dev->dev);
201 }
202 
atmel_hlcdc_crtc_atomic_enable(struct drm_crtc * c,struct drm_atomic_state * state)203 static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c,
204 					   struct drm_atomic_state *state)
205 {
206 	struct drm_device *dev = c->dev;
207 	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
208 	struct regmap *regmap = crtc->dc->hlcdc->regmap;
209 	unsigned int status;
210 
211 	pm_runtime_get_sync(dev->dev);
212 
213 	pm_runtime_forbid(dev->dev);
214 
215 	pinctrl_pm_select_default_state(dev->dev);
216 	clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
217 
218 	regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK);
219 	while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
220 	       !(status & ATMEL_HLCDC_PIXEL_CLK))
221 		cpu_relax();
222 
223 
224 	regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_SYNC);
225 	while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
226 	       !(status & ATMEL_HLCDC_SYNC))
227 		cpu_relax();
228 
229 	regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_DISP);
230 	while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
231 	       !(status & ATMEL_HLCDC_DISP))
232 		cpu_relax();
233 
234 	pm_runtime_put_sync(dev->dev);
235 
236 }
237 
238 #define ATMEL_HLCDC_RGB444_OUTPUT	BIT(0)
239 #define ATMEL_HLCDC_RGB565_OUTPUT	BIT(1)
240 #define ATMEL_HLCDC_RGB666_OUTPUT	BIT(2)
241 #define ATMEL_HLCDC_RGB888_OUTPUT	BIT(3)
242 #define ATMEL_HLCDC_OUTPUT_MODE_MASK	GENMASK(3, 0)
243 
atmel_hlcdc_connector_output_mode(struct drm_connector_state * state)244 static int atmel_hlcdc_connector_output_mode(struct drm_connector_state *state)
245 {
246 	struct drm_connector *connector = state->connector;
247 	struct drm_display_info *info = &connector->display_info;
248 	struct drm_encoder *encoder;
249 	unsigned int supported_fmts = 0;
250 	int j;
251 
252 	encoder = state->best_encoder;
253 	if (!encoder)
254 		encoder = connector->encoder;
255 
256 	switch (atmel_hlcdc_encoder_get_bus_fmt(encoder)) {
257 	case 0:
258 		break;
259 	case MEDIA_BUS_FMT_RGB444_1X12:
260 		return ATMEL_HLCDC_RGB444_OUTPUT;
261 	case MEDIA_BUS_FMT_RGB565_1X16:
262 		return ATMEL_HLCDC_RGB565_OUTPUT;
263 	case MEDIA_BUS_FMT_RGB666_1X18:
264 		return ATMEL_HLCDC_RGB666_OUTPUT;
265 	case MEDIA_BUS_FMT_RGB888_1X24:
266 		return ATMEL_HLCDC_RGB888_OUTPUT;
267 	default:
268 		return -EINVAL;
269 	}
270 
271 	for (j = 0; j < info->num_bus_formats; j++) {
272 		switch (info->bus_formats[j]) {
273 		case MEDIA_BUS_FMT_RGB444_1X12:
274 			supported_fmts |= ATMEL_HLCDC_RGB444_OUTPUT;
275 			break;
276 		case MEDIA_BUS_FMT_RGB565_1X16:
277 			supported_fmts |= ATMEL_HLCDC_RGB565_OUTPUT;
278 			break;
279 		case MEDIA_BUS_FMT_RGB666_1X18:
280 			supported_fmts |= ATMEL_HLCDC_RGB666_OUTPUT;
281 			break;
282 		case MEDIA_BUS_FMT_RGB888_1X24:
283 			supported_fmts |= ATMEL_HLCDC_RGB888_OUTPUT;
284 			break;
285 		default:
286 			break;
287 		}
288 	}
289 
290 	return supported_fmts;
291 }
292 
atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state * state)293 static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state)
294 {
295 	unsigned int output_fmts = ATMEL_HLCDC_OUTPUT_MODE_MASK;
296 	struct atmel_hlcdc_crtc_state *hstate;
297 	struct drm_connector_state *cstate;
298 	struct drm_connector *connector;
299 	struct atmel_hlcdc_crtc *crtc;
300 	int i;
301 
302 	crtc = drm_crtc_to_atmel_hlcdc_crtc(state->crtc);
303 
304 	for_each_new_connector_in_state(state->state, connector, cstate, i) {
305 		unsigned int supported_fmts = 0;
306 
307 		if (!cstate->crtc)
308 			continue;
309 
310 		supported_fmts = atmel_hlcdc_connector_output_mode(cstate);
311 
312 		if (crtc->dc->desc->conflicting_output_formats)
313 			output_fmts &= supported_fmts;
314 		else
315 			output_fmts |= supported_fmts;
316 	}
317 
318 	if (!output_fmts)
319 		return -EINVAL;
320 
321 	hstate = drm_crtc_state_to_atmel_hlcdc_crtc_state(state);
322 	hstate->output_mode = fls(output_fmts) - 1;
323 
324 	return 0;
325 }
326 
atmel_hlcdc_crtc_atomic_check(struct drm_crtc * c,struct drm_atomic_state * state)327 static int atmel_hlcdc_crtc_atomic_check(struct drm_crtc *c,
328 					 struct drm_atomic_state *state)
329 {
330 	struct drm_crtc_state *s = drm_atomic_get_new_crtc_state(state, c);
331 	int ret;
332 
333 	ret = atmel_hlcdc_crtc_select_output_mode(s);
334 	if (ret)
335 		return ret;
336 
337 	ret = atmel_hlcdc_plane_prepare_disc_area(s);
338 	if (ret)
339 		return ret;
340 
341 	return atmel_hlcdc_plane_prepare_ahb_routing(s);
342 }
343 
atmel_hlcdc_crtc_atomic_begin(struct drm_crtc * c,struct drm_atomic_state * state)344 static void atmel_hlcdc_crtc_atomic_begin(struct drm_crtc *c,
345 					  struct drm_atomic_state *state)
346 {
347 	drm_crtc_vblank_on(c);
348 }
349 
atmel_hlcdc_crtc_atomic_flush(struct drm_crtc * c,struct drm_atomic_state * state)350 static void atmel_hlcdc_crtc_atomic_flush(struct drm_crtc *c,
351 					  struct drm_atomic_state *state)
352 {
353 	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
354 	unsigned long flags;
355 
356 	spin_lock_irqsave(&c->dev->event_lock, flags);
357 
358 	if (c->state->event) {
359 		c->state->event->pipe = drm_crtc_index(c);
360 
361 		WARN_ON(drm_crtc_vblank_get(c) != 0);
362 
363 		crtc->event = c->state->event;
364 		c->state->event = NULL;
365 	}
366 	spin_unlock_irqrestore(&c->dev->event_lock, flags);
367 }
368 
369 static const struct drm_crtc_helper_funcs lcdc_crtc_helper_funcs = {
370 	.mode_valid = atmel_hlcdc_crtc_mode_valid,
371 	.mode_set_nofb = atmel_hlcdc_crtc_mode_set_nofb,
372 	.atomic_check = atmel_hlcdc_crtc_atomic_check,
373 	.atomic_begin = atmel_hlcdc_crtc_atomic_begin,
374 	.atomic_flush = atmel_hlcdc_crtc_atomic_flush,
375 	.atomic_enable = atmel_hlcdc_crtc_atomic_enable,
376 	.atomic_disable = atmel_hlcdc_crtc_atomic_disable,
377 };
378 
atmel_hlcdc_crtc_destroy(struct drm_crtc * c)379 static void atmel_hlcdc_crtc_destroy(struct drm_crtc *c)
380 {
381 	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
382 
383 	drm_crtc_cleanup(c);
384 	kfree(crtc);
385 }
386 
atmel_hlcdc_crtc_finish_page_flip(struct atmel_hlcdc_crtc * crtc)387 static void atmel_hlcdc_crtc_finish_page_flip(struct atmel_hlcdc_crtc *crtc)
388 {
389 	struct drm_device *dev = crtc->base.dev;
390 	unsigned long flags;
391 
392 	spin_lock_irqsave(&dev->event_lock, flags);
393 	if (crtc->event) {
394 		drm_crtc_send_vblank_event(&crtc->base, crtc->event);
395 		drm_crtc_vblank_put(&crtc->base);
396 		crtc->event = NULL;
397 	}
398 	spin_unlock_irqrestore(&dev->event_lock, flags);
399 }
400 
atmel_hlcdc_crtc_irq(struct drm_crtc * c)401 void atmel_hlcdc_crtc_irq(struct drm_crtc *c)
402 {
403 	drm_crtc_handle_vblank(c);
404 	atmel_hlcdc_crtc_finish_page_flip(drm_crtc_to_atmel_hlcdc_crtc(c));
405 }
406 
atmel_hlcdc_crtc_reset(struct drm_crtc * crtc)407 static void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc)
408 {
409 	struct atmel_hlcdc_crtc_state *state;
410 
411 	if (crtc->state) {
412 		__drm_atomic_helper_crtc_destroy_state(crtc->state);
413 		state = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state);
414 		kfree(state);
415 		crtc->state = NULL;
416 	}
417 
418 	state = kzalloc(sizeof(*state), GFP_KERNEL);
419 	if (state)
420 		__drm_atomic_helper_crtc_reset(crtc, &state->base);
421 }
422 
423 static struct drm_crtc_state *
atmel_hlcdc_crtc_duplicate_state(struct drm_crtc * crtc)424 atmel_hlcdc_crtc_duplicate_state(struct drm_crtc *crtc)
425 {
426 	struct atmel_hlcdc_crtc_state *state, *cur;
427 
428 	if (WARN_ON(!crtc->state))
429 		return NULL;
430 
431 	state = kmalloc(sizeof(*state), GFP_KERNEL);
432 	if (!state)
433 		return NULL;
434 	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
435 
436 	cur = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state);
437 	state->output_mode = cur->output_mode;
438 
439 	return &state->base;
440 }
441 
atmel_hlcdc_crtc_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * s)442 static void atmel_hlcdc_crtc_destroy_state(struct drm_crtc *crtc,
443 					   struct drm_crtc_state *s)
444 {
445 	struct atmel_hlcdc_crtc_state *state;
446 
447 	state = drm_crtc_state_to_atmel_hlcdc_crtc_state(s);
448 	__drm_atomic_helper_crtc_destroy_state(s);
449 	kfree(state);
450 }
451 
atmel_hlcdc_crtc_enable_vblank(struct drm_crtc * c)452 static int atmel_hlcdc_crtc_enable_vblank(struct drm_crtc *c)
453 {
454 	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
455 	struct regmap *regmap = crtc->dc->hlcdc->regmap;
456 
457 	/* Enable SOF (Start Of Frame) interrupt for vblank counting */
458 	regmap_write(regmap, ATMEL_HLCDC_IER, ATMEL_HLCDC_SOF);
459 
460 	return 0;
461 }
462 
atmel_hlcdc_crtc_disable_vblank(struct drm_crtc * c)463 static void atmel_hlcdc_crtc_disable_vblank(struct drm_crtc *c)
464 {
465 	struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
466 	struct regmap *regmap = crtc->dc->hlcdc->regmap;
467 
468 	regmap_write(regmap, ATMEL_HLCDC_IDR, ATMEL_HLCDC_SOF);
469 }
470 
471 static const struct drm_crtc_funcs atmel_hlcdc_crtc_funcs = {
472 	.page_flip = drm_atomic_helper_page_flip,
473 	.set_config = drm_atomic_helper_set_config,
474 	.destroy = atmel_hlcdc_crtc_destroy,
475 	.reset = atmel_hlcdc_crtc_reset,
476 	.atomic_duplicate_state =  atmel_hlcdc_crtc_duplicate_state,
477 	.atomic_destroy_state = atmel_hlcdc_crtc_destroy_state,
478 	.enable_vblank = atmel_hlcdc_crtc_enable_vblank,
479 	.disable_vblank = atmel_hlcdc_crtc_disable_vblank,
480 };
481 
atmel_hlcdc_crtc_create(struct drm_device * dev)482 int atmel_hlcdc_crtc_create(struct drm_device *dev)
483 {
484 	struct atmel_hlcdc_plane *primary = NULL, *cursor = NULL;
485 	struct atmel_hlcdc_dc *dc = dev->dev_private;
486 	struct atmel_hlcdc_crtc *crtc;
487 	int ret;
488 	int i;
489 
490 	crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
491 	if (!crtc)
492 		return -ENOMEM;
493 
494 	crtc->dc = dc;
495 
496 	for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
497 		if (!dc->layers[i])
498 			continue;
499 
500 		switch (dc->layers[i]->desc->type) {
501 		case ATMEL_HLCDC_BASE_LAYER:
502 			primary = atmel_hlcdc_layer_to_plane(dc->layers[i]);
503 			break;
504 
505 		case ATMEL_HLCDC_CURSOR_LAYER:
506 			cursor = atmel_hlcdc_layer_to_plane(dc->layers[i]);
507 			break;
508 
509 		default:
510 			break;
511 		}
512 	}
513 
514 	ret = drm_crtc_init_with_planes(dev, &crtc->base, &primary->base,
515 					&cursor->base, &atmel_hlcdc_crtc_funcs,
516 					NULL);
517 	if (ret < 0)
518 		goto fail;
519 
520 	crtc->id = drm_crtc_index(&crtc->base);
521 
522 	for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
523 		struct atmel_hlcdc_plane *overlay;
524 
525 		if (dc->layers[i] &&
526 		    dc->layers[i]->desc->type == ATMEL_HLCDC_OVERLAY_LAYER) {
527 			overlay = atmel_hlcdc_layer_to_plane(dc->layers[i]);
528 			overlay->base.possible_crtcs = 1 << crtc->id;
529 		}
530 	}
531 
532 	drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs);
533 
534 	drm_mode_crtc_set_gamma_size(&crtc->base, ATMEL_HLCDC_CLUT_SIZE);
535 	drm_crtc_enable_color_mgmt(&crtc->base, 0, false,
536 				   ATMEL_HLCDC_CLUT_SIZE);
537 
538 	dc->crtc = &crtc->base;
539 
540 	return 0;
541 
542 fail:
543 	atmel_hlcdc_crtc_destroy(&crtc->base);
544 	return ret;
545 }
546