1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #ifndef __INTEL_DISPLAY_POWER_H__
7 #define __INTEL_DISPLAY_POWER_H__
8 
9 #include "intel_wakeref.h"
10 
11 enum aux_ch;
12 enum dpio_channel;
13 enum dpio_phy;
14 enum i915_drm_suspend_mode;
15 enum port;
16 struct drm_i915_private;
17 struct i915_power_well;
18 struct intel_encoder;
19 
20 /*
21  * Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances
22  * consecutive, so that the pipe,transcoder,port -> power domain macros
23  * work correctly.
24  */
25 enum intel_display_power_domain {
26 	POWER_DOMAIN_DISPLAY_CORE,
27 	POWER_DOMAIN_PIPE_A,
28 	POWER_DOMAIN_PIPE_B,
29 	POWER_DOMAIN_PIPE_C,
30 	POWER_DOMAIN_PIPE_D,
31 	POWER_DOMAIN_PIPE_PANEL_FITTER_A,
32 	POWER_DOMAIN_PIPE_PANEL_FITTER_B,
33 	POWER_DOMAIN_PIPE_PANEL_FITTER_C,
34 	POWER_DOMAIN_PIPE_PANEL_FITTER_D,
35 	POWER_DOMAIN_TRANSCODER_A,
36 	POWER_DOMAIN_TRANSCODER_B,
37 	POWER_DOMAIN_TRANSCODER_C,
38 	POWER_DOMAIN_TRANSCODER_D,
39 	POWER_DOMAIN_TRANSCODER_EDP,
40 	POWER_DOMAIN_TRANSCODER_DSI_A,
41 	POWER_DOMAIN_TRANSCODER_DSI_C,
42 
43 	/* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
44 	POWER_DOMAIN_TRANSCODER_VDSC_PW2,
45 
46 	POWER_DOMAIN_PORT_DDI_LANES_A,
47 	POWER_DOMAIN_PORT_DDI_LANES_B,
48 	POWER_DOMAIN_PORT_DDI_LANES_C,
49 	POWER_DOMAIN_PORT_DDI_LANES_D,
50 	POWER_DOMAIN_PORT_DDI_LANES_E,
51 	POWER_DOMAIN_PORT_DDI_LANES_F,
52 
53 	POWER_DOMAIN_PORT_DDI_LANES_TC1,
54 	POWER_DOMAIN_PORT_DDI_LANES_TC2,
55 	POWER_DOMAIN_PORT_DDI_LANES_TC3,
56 	POWER_DOMAIN_PORT_DDI_LANES_TC4,
57 	POWER_DOMAIN_PORT_DDI_LANES_TC5,
58 	POWER_DOMAIN_PORT_DDI_LANES_TC6,
59 
60 	POWER_DOMAIN_PORT_DDI_IO_A,
61 	POWER_DOMAIN_PORT_DDI_IO_B,
62 	POWER_DOMAIN_PORT_DDI_IO_C,
63 	POWER_DOMAIN_PORT_DDI_IO_D,
64 	POWER_DOMAIN_PORT_DDI_IO_E,
65 	POWER_DOMAIN_PORT_DDI_IO_F,
66 
67 	POWER_DOMAIN_PORT_DDI_IO_TC1,
68 	POWER_DOMAIN_PORT_DDI_IO_TC2,
69 	POWER_DOMAIN_PORT_DDI_IO_TC3,
70 	POWER_DOMAIN_PORT_DDI_IO_TC4,
71 	POWER_DOMAIN_PORT_DDI_IO_TC5,
72 	POWER_DOMAIN_PORT_DDI_IO_TC6,
73 
74 	POWER_DOMAIN_PORT_DSI,
75 	POWER_DOMAIN_PORT_CRT,
76 	POWER_DOMAIN_PORT_OTHER,
77 	POWER_DOMAIN_VGA,
78 	POWER_DOMAIN_AUDIO_MMIO,
79 	POWER_DOMAIN_AUDIO_PLAYBACK,
80 
81 	POWER_DOMAIN_AUX_IO_A,
82 	POWER_DOMAIN_AUX_IO_B,
83 	POWER_DOMAIN_AUX_IO_C,
84 	POWER_DOMAIN_AUX_IO_D,
85 	POWER_DOMAIN_AUX_IO_E,
86 	POWER_DOMAIN_AUX_IO_F,
87 
88 	POWER_DOMAIN_AUX_A,
89 	POWER_DOMAIN_AUX_B,
90 	POWER_DOMAIN_AUX_C,
91 	POWER_DOMAIN_AUX_D,
92 	POWER_DOMAIN_AUX_E,
93 	POWER_DOMAIN_AUX_F,
94 
95 	POWER_DOMAIN_AUX_USBC1,
96 	POWER_DOMAIN_AUX_USBC2,
97 	POWER_DOMAIN_AUX_USBC3,
98 	POWER_DOMAIN_AUX_USBC4,
99 	POWER_DOMAIN_AUX_USBC5,
100 	POWER_DOMAIN_AUX_USBC6,
101 
102 	POWER_DOMAIN_AUX_TBT1,
103 	POWER_DOMAIN_AUX_TBT2,
104 	POWER_DOMAIN_AUX_TBT3,
105 	POWER_DOMAIN_AUX_TBT4,
106 	POWER_DOMAIN_AUX_TBT5,
107 	POWER_DOMAIN_AUX_TBT6,
108 
109 	POWER_DOMAIN_GMBUS,
110 	POWER_DOMAIN_MODESET,
111 	POWER_DOMAIN_GT_IRQ,
112 	POWER_DOMAIN_DC_OFF,
113 	POWER_DOMAIN_TC_COLD_OFF,
114 	POWER_DOMAIN_INIT,
115 
116 	POWER_DOMAIN_NUM,
117 	POWER_DOMAIN_INVALID = POWER_DOMAIN_NUM,
118 };
119 
120 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
121 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
122 		((pipe) + POWER_DOMAIN_PIPE_PANEL_FITTER_A)
123 #define POWER_DOMAIN_TRANSCODER(tran) \
124 	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
125 	 (tran) + POWER_DOMAIN_TRANSCODER_A)
126 
127 struct intel_power_domain_mask {
128 	DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
129 };
130 
131 struct i915_power_domains {
132 	/*
133 	 * Power wells needed for initialization at driver init and suspend
134 	 * time are on. They are kept on until after the first modeset.
135 	 */
136 	bool initializing;
137 	bool display_core_suspended;
138 	int power_well_count;
139 
140 	intel_wakeref_t init_wakeref;
141 	intel_wakeref_t disable_wakeref;
142 
143 	struct mutex lock;
144 	int domain_use_count[POWER_DOMAIN_NUM];
145 
146 	struct delayed_work async_put_work;
147 	intel_wakeref_t async_put_wakeref;
148 	struct intel_power_domain_mask async_put_domains[2];
149 
150 	struct i915_power_well *power_wells;
151 };
152 
153 struct intel_display_power_domain_set {
154 	struct intel_power_domain_mask mask;
155 #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
156 	intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
157 #endif
158 };
159 
160 #define for_each_power_domain(__domain, __mask)				\
161 	for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++)	\
162 		for_each_if(test_bit((__domain), (__mask)->bits))
163 
164 int intel_power_domains_init(struct drm_i915_private *dev_priv);
165 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
166 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
167 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
168 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
169 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
170 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
171 				 enum i915_drm_suspend_mode);
172 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
173 void intel_power_domains_sanitize_state(struct drm_i915_private *dev_priv);
174 
175 void intel_display_power_suspend_late(struct drm_i915_private *i915);
176 void intel_display_power_resume_early(struct drm_i915_private *i915);
177 void intel_display_power_suspend(struct drm_i915_private *i915);
178 void intel_display_power_resume(struct drm_i915_private *i915);
179 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
180 					     u32 state);
181 
182 const char *
183 intel_display_power_domain_str(enum intel_display_power_domain domain);
184 
185 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
186 				    enum intel_display_power_domain domain);
187 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
188 				      enum intel_display_power_domain domain);
189 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
190 					enum intel_display_power_domain domain);
191 intel_wakeref_t
192 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
193 				   enum intel_display_power_domain domain);
194 void __intel_display_power_put_async(struct drm_i915_private *i915,
195 				     enum intel_display_power_domain domain,
196 				     intel_wakeref_t wakeref);
197 void intel_display_power_flush_work(struct drm_i915_private *i915);
198 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
199 void intel_display_power_put(struct drm_i915_private *dev_priv,
200 			     enum intel_display_power_domain domain,
201 			     intel_wakeref_t wakeref);
202 static inline void
intel_display_power_put_async(struct drm_i915_private * i915,enum intel_display_power_domain domain,intel_wakeref_t wakeref)203 intel_display_power_put_async(struct drm_i915_private *i915,
204 			      enum intel_display_power_domain domain,
205 			      intel_wakeref_t wakeref)
206 {
207 	__intel_display_power_put_async(i915, domain, wakeref);
208 }
209 #else
210 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
211 				       enum intel_display_power_domain domain);
212 
213 static inline void
intel_display_power_put(struct drm_i915_private * i915,enum intel_display_power_domain domain,intel_wakeref_t wakeref)214 intel_display_power_put(struct drm_i915_private *i915,
215 			enum intel_display_power_domain domain,
216 			intel_wakeref_t wakeref)
217 {
218 	intel_display_power_put_unchecked(i915, domain);
219 }
220 
221 static inline void
intel_display_power_put_async(struct drm_i915_private * i915,enum intel_display_power_domain domain,intel_wakeref_t wakeref)222 intel_display_power_put_async(struct drm_i915_private *i915,
223 			      enum intel_display_power_domain domain,
224 			      intel_wakeref_t wakeref)
225 {
226 	__intel_display_power_put_async(i915, domain, -1);
227 }
228 #endif
229 
230 void
231 intel_display_power_get_in_set(struct drm_i915_private *i915,
232 			       struct intel_display_power_domain_set *power_domain_set,
233 			       enum intel_display_power_domain domain);
234 
235 bool
236 intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
237 					  struct intel_display_power_domain_set *power_domain_set,
238 					  enum intel_display_power_domain domain);
239 
240 void
241 intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
242 				    struct intel_display_power_domain_set *power_domain_set,
243 				    struct intel_power_domain_mask *mask);
244 
245 static inline void
intel_display_power_put_all_in_set(struct drm_i915_private * i915,struct intel_display_power_domain_set * power_domain_set)246 intel_display_power_put_all_in_set(struct drm_i915_private *i915,
247 				   struct intel_display_power_domain_set *power_domain_set)
248 {
249 	intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask);
250 }
251 
252 void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m);
253 
254 enum intel_display_power_domain
255 intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port);
256 enum intel_display_power_domain
257 intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port);
258 enum intel_display_power_domain
259 intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
260 enum intel_display_power_domain
261 intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
262 enum intel_display_power_domain
263 intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
264 
265 /*
266  * FIXME: We should probably switch this to a 0-based scheme to be consistent
267  * with how we now name/number DBUF_CTL instances.
268  */
269 enum dbuf_slice {
270 	DBUF_S1,
271 	DBUF_S2,
272 	DBUF_S3,
273 	DBUF_S4,
274 	I915_MAX_DBUF_SLICES
275 };
276 
277 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
278 			     u8 req_slices);
279 
280 #define with_intel_display_power(i915, domain, wf) \
281 	for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
282 	     intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
283 
284 #define with_intel_display_power_if_enabled(i915, domain, wf) \
285 	for ((wf) = intel_display_power_get_if_enabled((i915), (domain)); (wf); \
286 	     intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
287 
288 #endif /* __INTEL_DISPLAY_POWER_H__ */
289