1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __VLV_DSI_REGS_H__ 7 #define __VLV_DSI_REGS_H__ 8 9 #include "intel_display_reg_defs.h" 10 11 #define VLV_MIPI_BASE VLV_DISPLAY_BASE 12 #define BXT_MIPI_BASE 0x60000 13 14 #define _MIPI_MMIO_BASE(__i915) ((__i915)->display.dsi.mmio_base) 15 16 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ 17 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) 18 19 /* BXT MIPI mode configure */ 20 #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 21 #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 22 #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \ 23 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) 24 25 #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC 26 #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC 27 #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \ 28 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) 29 30 #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 31 #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 32 #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \ 33 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) 34 35 #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) 36 #define STAP_SELECT (1 << 0) 37 38 #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054) 39 #define HS_IO_CTRL_SELECT (1 << 0) 40 41 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) 42 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) 43 #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) 44 45 /* BXT port control */ 46 #define _BXT_MIPIA_PORT_CTRL 0x6B0C0 47 #define _BXT_MIPIC_PORT_CTRL 0x6B8C0 48 #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) 49 50 #define DPI_ENABLE (1 << 31) /* A + C */ 51 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 52 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) 53 #define DUAL_LINK_MODE_SHIFT 26 54 #define DUAL_LINK_MODE_MASK (1 << 26) 55 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) 56 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) 57 #define DITHERING_ENABLE (1 << 25) /* A + C */ 58 #define FLOPPED_HSTX (1 << 23) 59 #define DE_INVERT (1 << 19) /* XXX */ 60 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 61 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) 62 #define AFE_LATCHOUT (1 << 17) 63 #define LP_OUTPUT_HOLD (1 << 16) 64 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 65 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) 66 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 67 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) 68 #define CSB_SHIFT 9 69 #define CSB_MASK (3 << 9) 70 #define CSB_20MHZ (0 << 9) 71 #define CSB_10MHZ (1 << 9) 72 #define CSB_40MHZ (2 << 9) 73 #define BANDGAP_MASK (1 << 8) 74 #define BANDGAP_PNW_CIRCUIT (0 << 8) 75 #define BANDGAP_LNC_CIRCUIT (1 << 8) 76 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 77 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) 78 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ 79 #define TEARING_EFFECT_SHIFT 2 /* A + C */ 80 #define TEARING_EFFECT_MASK (3 << 2) 81 #define TEARING_EFFECT_OFF (0 << 2) 82 #define TEARING_EFFECT_DSI (1 << 2) 83 #define TEARING_EFFECT_GPIO (2 << 2) 84 #define LANE_CONFIGURATION_SHIFT 0 85 #define LANE_CONFIGURATION_MASK (3 << 0) 86 #define LANE_CONFIGURATION_4LANE (0 << 0) 87 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) 88 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) 89 90 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) 91 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) 92 #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) 93 #define TEARING_EFFECT_DELAY_SHIFT 0 94 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) 95 96 /* XXX: all bits reserved */ 97 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) 98 99 /* MIPI DSI Controller and D-PHY registers */ 100 101 #define _MIPIA_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb000) 102 #define _MIPIC_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb800) 103 #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) 104 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ 105 #define ULPS_STATE_MASK (3 << 1) 106 #define ULPS_STATE_ENTER (2 << 1) 107 #define ULPS_STATE_EXIT (1 << 1) 108 #define ULPS_STATE_NORMAL_OPERATION (0 << 1) 109 #define DEVICE_READY (1 << 0) 110 111 #define _MIPIA_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb004) 112 #define _MIPIC_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb804) 113 #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) 114 #define _MIPIA_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb008) 115 #define _MIPIC_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb808) 116 #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) 117 #define TEARING_EFFECT (1 << 31) 118 #define SPL_PKT_SENT_INTERRUPT (1 << 30) 119 #define GEN_READ_DATA_AVAIL (1 << 29) 120 #define LP_GENERIC_WR_FIFO_FULL (1 << 28) 121 #define HS_GENERIC_WR_FIFO_FULL (1 << 27) 122 #define RX_PROT_VIOLATION (1 << 26) 123 #define RX_INVALID_TX_LENGTH (1 << 25) 124 #define ACK_WITH_NO_ERROR (1 << 24) 125 #define TURN_AROUND_ACK_TIMEOUT (1 << 23) 126 #define LP_RX_TIMEOUT (1 << 22) 127 #define HS_TX_TIMEOUT (1 << 21) 128 #define DPI_FIFO_UNDERRUN (1 << 20) 129 #define LOW_CONTENTION (1 << 19) 130 #define HIGH_CONTENTION (1 << 18) 131 #define TXDSI_VC_ID_INVALID (1 << 17) 132 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) 133 #define TXCHECKSUM_ERROR (1 << 15) 134 #define TXECC_MULTIBIT_ERROR (1 << 14) 135 #define TXECC_SINGLE_BIT_ERROR (1 << 13) 136 #define TXFALSE_CONTROL_ERROR (1 << 12) 137 #define RXDSI_VC_ID_INVALID (1 << 11) 138 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) 139 #define RXCHECKSUM_ERROR (1 << 9) 140 #define RXECC_MULTIBIT_ERROR (1 << 8) 141 #define RXECC_SINGLE_BIT_ERROR (1 << 7) 142 #define RXFALSE_CONTROL_ERROR (1 << 6) 143 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) 144 #define RX_LP_TX_SYNC_ERROR (1 << 4) 145 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) 146 #define RXEOT_SYNC_ERROR (1 << 2) 147 #define RXSOT_SYNC_ERROR (1 << 1) 148 #define RXSOT_ERROR (1 << 0) 149 150 #define _MIPIA_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb00c) 151 #define _MIPIC_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb80c) 152 #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) 153 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) 154 #define CMD_MODE_NOT_SUPPORTED (0 << 13) 155 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) 156 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) 157 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) 158 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) 159 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) 160 #define VID_MODE_FORMAT_MASK (0xf << 7) 161 #define VID_MODE_NOT_SUPPORTED (0 << 7) 162 #define VID_MODE_FORMAT_RGB565 (1 << 7) 163 #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7) 164 #define VID_MODE_FORMAT_RGB666 (3 << 7) 165 #define VID_MODE_FORMAT_RGB888 (4 << 7) 166 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 167 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) 168 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 169 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) 170 #define DATA_LANES_PRG_REG_SHIFT 0 171 #define DATA_LANES_PRG_REG_MASK (7 << 0) 172 173 #define _MIPIA_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb010) 174 #define _MIPIC_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb810) 175 #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) 176 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff 177 178 #define _MIPIA_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb014) 179 #define _MIPIC_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb814) 180 #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) 181 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff 182 183 #define _MIPIA_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb018) 184 #define _MIPIC_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb818) 185 #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) 186 #define TURN_AROUND_TIMEOUT_MASK 0x3f 187 188 #define _MIPIA_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb01c) 189 #define _MIPIC_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb81c) 190 #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) 191 #define DEVICE_RESET_TIMER_MASK 0xffff 192 193 #define _MIPIA_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb020) 194 #define _MIPIC_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb820) 195 #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) 196 #define VERTICAL_ADDRESS_SHIFT 16 197 #define VERTICAL_ADDRESS_MASK (0xffff << 16) 198 #define HORIZONTAL_ADDRESS_SHIFT 0 199 #define HORIZONTAL_ADDRESS_MASK 0xffff 200 201 #define _MIPIA_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb024) 202 #define _MIPIC_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb824) 203 #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) 204 #define DBI_FIFO_EMPTY_HALF (0 << 0) 205 #define DBI_FIFO_EMPTY_QUARTER (1 << 0) 206 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) 207 208 /* regs below are bits 15:0 */ 209 #define _MIPIA_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb028) 210 #define _MIPIC_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb828) 211 #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) 212 213 #define _MIPIA_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb02c) 214 #define _MIPIC_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb82c) 215 #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) 216 217 #define _MIPIA_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb030) 218 #define _MIPIC_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb830) 219 #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) 220 221 #define _MIPIA_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb034) 222 #define _MIPIC_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb834) 223 #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) 224 225 #define _MIPIA_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb038) 226 #define _MIPIC_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb838) 227 #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) 228 229 #define _MIPIA_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb03c) 230 #define _MIPIC_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb83c) 231 #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) 232 233 #define _MIPIA_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb040) 234 #define _MIPIC_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb840) 235 #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) 236 237 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb044) 238 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb844) 239 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) 240 241 #define _MIPIA_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb048) 242 #define _MIPIC_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb848) 243 #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) 244 #define DPI_LP_MODE (1 << 6) 245 #define BACKLIGHT_OFF (1 << 5) 246 #define BACKLIGHT_ON (1 << 4) 247 #define COLOR_MODE_OFF (1 << 3) 248 #define COLOR_MODE_ON (1 << 2) 249 #define TURN_ON (1 << 1) 250 #define SHUTDOWN (1 << 0) 251 252 #define _MIPIA_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb04c) 253 #define _MIPIC_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb84c) 254 #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) 255 #define COMMAND_BYTE_SHIFT 0 256 #define COMMAND_BYTE_MASK (0x3f << 0) 257 258 #define _MIPIA_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb050) 259 #define _MIPIC_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb850) 260 #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) 261 #define MASTER_INIT_TIMER_SHIFT 0 262 #define MASTER_INIT_TIMER_MASK (0xffff << 0) 263 264 #define _MIPIA_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb054) 265 #define _MIPIC_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb854) 266 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \ 267 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) 268 #define MAX_RETURN_PKT_SIZE_SHIFT 0 269 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) 270 271 #define _MIPIA_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb058) 272 #define _MIPIC_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb858) 273 #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) 274 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) 275 #define DISABLE_VIDEO_BTA (1 << 3) 276 #define IP_TG_CONFIG (1 << 2) 277 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) 278 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) 279 #define VIDEO_MODE_BURST (3 << 0) 280 281 #define _MIPIA_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb05c) 282 #define _MIPIC_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb85c) 283 #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) 284 #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9) 285 #define BXT_DPHY_DEFEATURE_EN (1 << 8) 286 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) 287 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) 288 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) 289 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) 290 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) 291 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) 292 #define CLOCKSTOP (1 << 1) 293 #define EOT_DISABLE (1 << 0) 294 295 #define _MIPIA_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb060) 296 #define _MIPIC_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb860) 297 #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) 298 #define LP_BYTECLK_SHIFT 0 299 #define LP_BYTECLK_MASK (0xffff << 0) 300 301 #define _MIPIA_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb0a4) 302 #define _MIPIC_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb8a4) 303 #define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) 304 305 #define _MIPIA_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb098) 306 #define _MIPIC_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb898) 307 #define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) 308 309 /* bits 31:0 */ 310 #define _MIPIA_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb064) 311 #define _MIPIC_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb864) 312 #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) 313 314 /* bits 31:0 */ 315 #define _MIPIA_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb068) 316 #define _MIPIC_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb868) 317 #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) 318 319 #define _MIPIA_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb06c) 320 #define _MIPIC_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb86c) 321 #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) 322 #define _MIPIA_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb070) 323 #define _MIPIC_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb870) 324 #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) 325 #define LONG_PACKET_WORD_COUNT_SHIFT 8 326 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) 327 #define SHORT_PACKET_PARAM_SHIFT 8 328 #define SHORT_PACKET_PARAM_MASK (0xffff << 8) 329 #define VIRTUAL_CHANNEL_SHIFT 6 330 #define VIRTUAL_CHANNEL_MASK (3 << 6) 331 #define DATA_TYPE_SHIFT 0 332 #define DATA_TYPE_MASK (0x3f << 0) 333 /* data type values, see include/video/mipi_display.h */ 334 335 #define _MIPIA_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb074) 336 #define _MIPIC_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb874) 337 #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) 338 #define DPI_FIFO_EMPTY (1 << 28) 339 #define DBI_FIFO_EMPTY (1 << 27) 340 #define LP_CTRL_FIFO_EMPTY (1 << 26) 341 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 342 #define LP_CTRL_FIFO_FULL (1 << 24) 343 #define HS_CTRL_FIFO_EMPTY (1 << 18) 344 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 345 #define HS_CTRL_FIFO_FULL (1 << 16) 346 #define LP_DATA_FIFO_EMPTY (1 << 10) 347 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 348 #define LP_DATA_FIFO_FULL (1 << 8) 349 #define HS_DATA_FIFO_EMPTY (1 << 2) 350 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 351 #define HS_DATA_FIFO_FULL (1 << 0) 352 353 #define _MIPIA_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb078) 354 #define _MIPIC_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb878) 355 #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) 356 #define DBI_HS_LP_MODE_MASK (1 << 0) 357 #define DBI_LP_MODE (1 << 0) 358 #define DBI_HS_MODE (0 << 0) 359 360 #define _MIPIA_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb080) 361 #define _MIPIC_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb880) 362 #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) 363 #define EXIT_ZERO_COUNT_SHIFT 24 364 #define EXIT_ZERO_COUNT_MASK (0x3f << 24) 365 #define TRAIL_COUNT_SHIFT 16 366 #define TRAIL_COUNT_MASK (0x1f << 16) 367 #define CLK_ZERO_COUNT_SHIFT 8 368 #define CLK_ZERO_COUNT_MASK (0xff << 8) 369 #define PREPARE_COUNT_SHIFT 0 370 #define PREPARE_COUNT_MASK (0x3f << 0) 371 372 #define _MIPIA_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb084) 373 #define _MIPIC_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb884) 374 #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) 375 376 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb088) 377 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb888) 378 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) 379 #define LP_HS_SSW_CNT_SHIFT 16 380 #define LP_HS_SSW_CNT_MASK (0xffff << 16) 381 #define HS_LP_PWR_SW_CNT_SHIFT 0 382 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) 383 384 #define _MIPIA_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb08c) 385 #define _MIPIC_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb88c) 386 #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) 387 #define STOP_STATE_STALL_COUNTER_SHIFT 0 388 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) 389 390 #define _MIPIA_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb090) 391 #define _MIPIC_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb890) 392 #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) 393 #define _MIPIA_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb094) 394 #define _MIPIC_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb894) 395 #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) 396 #define RX_CONTENTION_DETECTED (1 << 0) 397 398 /* XXX: only pipe A ?!? */ 399 #define MIPIA_DBI_TYPEC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb100) 400 #define DBI_TYPEC_ENABLE (1 << 31) 401 #define DBI_TYPEC_WIP (1 << 30) 402 #define DBI_TYPEC_OPTION_SHIFT 28 403 #define DBI_TYPEC_OPTION_MASK (3 << 28) 404 #define DBI_TYPEC_FREQ_SHIFT 24 405 #define DBI_TYPEC_FREQ_MASK (0xf << 24) 406 #define DBI_TYPEC_OVERRIDE (1 << 8) 407 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 408 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) 409 410 /* MIPI adapter registers */ 411 412 #define _MIPIA_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb104) 413 #define _MIPIC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb904) 414 #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL) 415 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ 416 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) 417 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) 418 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) 419 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) 420 #define READ_REQUEST_PRIORITY_SHIFT 3 421 #define READ_REQUEST_PRIORITY_MASK (3 << 3) 422 #define READ_REQUEST_PRIORITY_LOW (0 << 3) 423 #define READ_REQUEST_PRIORITY_HIGH (3 << 3) 424 #define RGB_FLIP_TO_BGR (1 << 2) 425 426 #define BXT_PIPE_SELECT_SHIFT 7 427 #define BXT_PIPE_SELECT_MASK (7 << 7) 428 #define BXT_PIPE_SELECT(pipe) ((pipe) << 7) 429 #define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */ 430 #define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */ 431 #define GLK_MIPIIO_RESET_RELEASED (1 << 28) 432 #define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */ 433 #define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */ 434 #define GLK_LP_WAKE (1 << 22) 435 #define GLK_LP11_LOW_PWR_MODE (1 << 21) 436 #define GLK_LP00_LOW_PWR_MODE (1 << 20) 437 #define GLK_FIREWALL_ENABLE (1 << 16) 438 #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10) 439 #define BXT_PIXEL_OVERLAP_CNT_SHIFT 10 440 #define BXT_DSC_ENABLE (1 << 3) 441 #define BXT_RGB_FLIP (1 << 2) 442 #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */ 443 #define GLK_MIPIIO_ENABLE (1 << 0) 444 445 #define _MIPIA_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb108) 446 #define _MIPIC_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb908) 447 #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) 448 #define DATA_MEM_ADDRESS_SHIFT 5 449 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) 450 #define DATA_VALID (1 << 0) 451 452 #define _MIPIA_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb10c) 453 #define _MIPIC_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb90c) 454 #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) 455 #define DATA_LENGTH_SHIFT 0 456 #define DATA_LENGTH_MASK (0xfffff << 0) 457 458 #define _MIPIA_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb110) 459 #define _MIPIC_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb910) 460 #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) 461 #define COMMAND_MEM_ADDRESS_SHIFT 5 462 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) 463 #define AUTO_PWG_ENABLE (1 << 2) 464 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) 465 #define COMMAND_VALID (1 << 0) 466 467 #define _MIPIA_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb114) 468 #define _MIPIC_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb914) 469 #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) 470 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ 471 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) 472 473 #define _MIPIA_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb118) 474 #define _MIPIC_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb918) 475 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ 476 477 #define _MIPIA_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb138) 478 #define _MIPIC_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb938) 479 #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) 480 #define READ_DATA_VALID(n) (1 << (n)) 481 482 #endif /* __VLV_DSI_REGS_H__ */ 483