1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright © 2014 Intel Corporation
4 */
5
6 #ifndef __GEN8_ENGINE_CS_H__
7 #define __GEN8_ENGINE_CS_H__
8
9 #include <linux/string.h>
10 #include <linux/types.h>
11
12 #include "i915_gem.h" /* GEM_BUG_ON */
13 #include "intel_gt_regs.h"
14 #include "intel_gpu_commands.h"
15
16 struct intel_gt;
17 struct i915_request;
18
19 int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode);
20 int gen11_emit_flush_rcs(struct i915_request *rq, u32 mode);
21 int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode);
22
23 int gen8_emit_flush_xcs(struct i915_request *rq, u32 mode);
24 int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode);
25
26 int gen8_emit_init_breadcrumb(struct i915_request *rq);
27
28 int gen8_emit_bb_start_noarb(struct i915_request *rq,
29 u64 offset, u32 len,
30 const unsigned int flags);
31 int gen8_emit_bb_start(struct i915_request *rq,
32 u64 offset, u32 len,
33 const unsigned int flags);
34
35 int xehp_emit_bb_start_noarb(struct i915_request *rq,
36 u64 offset, u32 len,
37 const unsigned int flags);
38 int xehp_emit_bb_start(struct i915_request *rq,
39 u64 offset, u32 len,
40 const unsigned int flags);
41
42 u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
43 u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
44
45 u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
46 u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
47 u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
48
49 u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv_reg);
50
51 static inline u32 *
__gen8_emit_pipe_control(u32 * batch,u32 flags0,u32 flags1,u32 offset)52 __gen8_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
53 {
54 memset(batch, 0, 6 * sizeof(u32));
55
56 batch[0] = GFX_OP_PIPE_CONTROL(6) | flags0;
57 batch[1] = flags1;
58 batch[2] = offset;
59
60 return batch + 6;
61 }
62
gen8_emit_pipe_control(u32 * batch,u32 flags,u32 offset)63 static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
64 {
65 return __gen8_emit_pipe_control(batch, 0, flags, offset);
66 }
67
gen12_emit_pipe_control(u32 * batch,u32 flags0,u32 flags1,u32 offset)68 static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
69 {
70 return __gen8_emit_pipe_control(batch, flags0, flags1, offset);
71 }
72
73 static inline u32 *
__gen8_emit_write_rcs(u32 * cs,u32 value,u32 offset,u32 flags0,u32 flags1)74 __gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1)
75 {
76 *cs++ = GFX_OP_PIPE_CONTROL(6) | flags0;
77 *cs++ = flags1 | PIPE_CONTROL_QW_WRITE;
78 *cs++ = offset;
79 *cs++ = 0;
80 *cs++ = value;
81 *cs++ = 0; /* We're thrashing one extra dword. */
82
83 return cs;
84 }
85
86 static inline u32*
gen8_emit_ggtt_write_rcs(u32 * cs,u32 value,u32 gtt_offset,u32 flags)87 gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
88 {
89 /* We're using qword write, offset should be aligned to 8 bytes. */
90 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
91
92 return __gen8_emit_write_rcs(cs,
93 value,
94 gtt_offset,
95 0,
96 flags | PIPE_CONTROL_GLOBAL_GTT_IVB);
97 }
98
99 static inline u32*
gen12_emit_ggtt_write_rcs(u32 * cs,u32 value,u32 gtt_offset,u32 flags0,u32 flags1)100 gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)
101 {
102 /* We're using qword write, offset should be aligned to 8 bytes. */
103 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
104
105 return __gen8_emit_write_rcs(cs,
106 value,
107 gtt_offset,
108 flags0,
109 flags1 | PIPE_CONTROL_GLOBAL_GTT_IVB);
110 }
111
112 static inline u32 *
__gen8_emit_flush_dw(u32 * cs,u32 value,u32 gtt_offset,u32 flags)113 __gen8_emit_flush_dw(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
114 {
115 *cs++ = (MI_FLUSH_DW + 1) | flags;
116 *cs++ = gtt_offset;
117 *cs++ = 0;
118 *cs++ = value;
119
120 return cs;
121 }
122
123 static inline u32 *
gen8_emit_ggtt_write(u32 * cs,u32 value,u32 gtt_offset,u32 flags)124 gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
125 {
126 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
127 GEM_BUG_ON(gtt_offset & (1 << 5));
128 /* Offset should be aligned to 8 bytes for both (QW/DW) write types */
129 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
130
131 return __gen8_emit_flush_dw(cs,
132 value,
133 gtt_offset | MI_FLUSH_DW_USE_GTT,
134 flags | MI_FLUSH_DW_OP_STOREDW);
135 }
136
137 #endif /* __GEN8_ENGINE_CS_H__ */
138