1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. */
3 
4 #include <linux/completion.h>
5 #include <linux/circ_buf.h>
6 #include <linux/list.h>
7 
8 #include "a6xx_gmu.h"
9 #include "a6xx_gmu.xml.h"
10 #include "a6xx_gpu.h"
11 
12 #define HFI_MSG_ID(val) [val] = #val
13 
14 static const char * const a6xx_hfi_msg_id[] = {
15 	HFI_MSG_ID(HFI_H2F_MSG_INIT),
16 	HFI_MSG_ID(HFI_H2F_MSG_FW_VERSION),
17 	HFI_MSG_ID(HFI_H2F_MSG_BW_TABLE),
18 	HFI_MSG_ID(HFI_H2F_MSG_PERF_TABLE),
19 	HFI_MSG_ID(HFI_H2F_MSG_TEST),
20 	HFI_MSG_ID(HFI_H2F_MSG_START),
21 	HFI_MSG_ID(HFI_H2F_MSG_CORE_FW_START),
22 	HFI_MSG_ID(HFI_H2F_MSG_GX_BW_PERF_VOTE),
23 	HFI_MSG_ID(HFI_H2F_MSG_PREPARE_SLUMBER),
24 };
25 
a6xx_hfi_queue_read(struct a6xx_gmu * gmu,struct a6xx_hfi_queue * queue,u32 * data,u32 dwords)26 static int a6xx_hfi_queue_read(struct a6xx_gmu *gmu,
27 	struct a6xx_hfi_queue *queue, u32 *data, u32 dwords)
28 {
29 	struct a6xx_hfi_queue_header *header = queue->header;
30 	u32 i, hdr, index = header->read_index;
31 
32 	if (header->read_index == header->write_index) {
33 		header->rx_request = 1;
34 		return 0;
35 	}
36 
37 	hdr = queue->data[index];
38 
39 	queue->history[(queue->history_idx++) % HFI_HISTORY_SZ] = index;
40 
41 	/*
42 	 * If we are to assume that the GMU firmware is in fact a rational actor
43 	 * and is programmed to not send us a larger response than we expect
44 	 * then we can also assume that if the header size is unexpectedly large
45 	 * that it is due to memory corruption and/or hardware failure. In this
46 	 * case the only reasonable course of action is to BUG() to help harden
47 	 * the failure.
48 	 */
49 
50 	BUG_ON(HFI_HEADER_SIZE(hdr) > dwords);
51 
52 	for (i = 0; i < HFI_HEADER_SIZE(hdr); i++) {
53 		data[i] = queue->data[index];
54 		index = (index + 1) % header->size;
55 	}
56 
57 	if (!gmu->legacy)
58 		index = ALIGN(index, 4) % header->size;
59 
60 	header->read_index = index;
61 	return HFI_HEADER_SIZE(hdr);
62 }
63 
a6xx_hfi_queue_write(struct a6xx_gmu * gmu,struct a6xx_hfi_queue * queue,u32 * data,u32 dwords)64 static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu,
65 	struct a6xx_hfi_queue *queue, u32 *data, u32 dwords)
66 {
67 	struct a6xx_hfi_queue_header *header = queue->header;
68 	u32 i, space, index = header->write_index;
69 
70 	spin_lock(&queue->lock);
71 
72 	space = CIRC_SPACE(header->write_index, header->read_index,
73 		header->size);
74 	if (space < dwords) {
75 		header->dropped++;
76 		spin_unlock(&queue->lock);
77 		return -ENOSPC;
78 	}
79 
80 	queue->history[(queue->history_idx++) % HFI_HISTORY_SZ] = index;
81 
82 	for (i = 0; i < dwords; i++) {
83 		queue->data[index] = data[i];
84 		index = (index + 1) % header->size;
85 	}
86 
87 	/* Cookify any non used data at the end of the write buffer */
88 	if (!gmu->legacy) {
89 		for (; index % 4; index = (index + 1) % header->size)
90 			queue->data[index] = 0xfafafafa;
91 	}
92 
93 	header->write_index = index;
94 	spin_unlock(&queue->lock);
95 
96 	gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01);
97 	return 0;
98 }
99 
a6xx_hfi_wait_for_ack(struct a6xx_gmu * gmu,u32 id,u32 seqnum,u32 * payload,u32 payload_size)100 static int a6xx_hfi_wait_for_ack(struct a6xx_gmu *gmu, u32 id, u32 seqnum,
101 		u32 *payload, u32 payload_size)
102 {
103 	struct a6xx_hfi_queue *queue = &gmu->queues[HFI_RESPONSE_QUEUE];
104 	u32 val;
105 	int ret;
106 
107 	/* Wait for a response */
108 	ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,
109 		val & A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ, 100, 5000);
110 
111 	if (ret) {
112 		DRM_DEV_ERROR(gmu->dev,
113 			"Message %s id %d timed out waiting for response\n",
114 			a6xx_hfi_msg_id[id], seqnum);
115 		return -ETIMEDOUT;
116 	}
117 
118 	/* Clear the interrupt */
119 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR,
120 		A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ);
121 
122 	for (;;) {
123 		struct a6xx_hfi_msg_response resp;
124 
125 		/* Get the next packet */
126 		ret = a6xx_hfi_queue_read(gmu, queue, (u32 *) &resp,
127 			sizeof(resp) >> 2);
128 
129 		/* If the queue is empty our response never made it */
130 		if (!ret) {
131 			DRM_DEV_ERROR(gmu->dev,
132 				"The HFI response queue is unexpectedly empty\n");
133 
134 			return -ENOENT;
135 		}
136 
137 		if (HFI_HEADER_ID(resp.header) == HFI_F2H_MSG_ERROR) {
138 			struct a6xx_hfi_msg_error *error =
139 				(struct a6xx_hfi_msg_error *) &resp;
140 
141 			DRM_DEV_ERROR(gmu->dev, "GMU firmware error %d\n",
142 				error->code);
143 			continue;
144 		}
145 
146 		if (seqnum != HFI_HEADER_SEQNUM(resp.ret_header)) {
147 			DRM_DEV_ERROR(gmu->dev,
148 				"Unexpected message id %d on the response queue\n",
149 				HFI_HEADER_SEQNUM(resp.ret_header));
150 			continue;
151 		}
152 
153 		if (resp.error) {
154 			DRM_DEV_ERROR(gmu->dev,
155 				"Message %s id %d returned error %d\n",
156 				a6xx_hfi_msg_id[id], seqnum, resp.error);
157 			return -EINVAL;
158 		}
159 
160 		/* All is well, copy over the buffer */
161 		if (payload && payload_size)
162 			memcpy(payload, resp.payload,
163 				min_t(u32, payload_size, sizeof(resp.payload)));
164 
165 		return 0;
166 	}
167 }
168 
a6xx_hfi_send_msg(struct a6xx_gmu * gmu,int id,void * data,u32 size,u32 * payload,u32 payload_size)169 static int a6xx_hfi_send_msg(struct a6xx_gmu *gmu, int id,
170 		void *data, u32 size, u32 *payload, u32 payload_size)
171 {
172 	struct a6xx_hfi_queue *queue = &gmu->queues[HFI_COMMAND_QUEUE];
173 	int ret, dwords = size >> 2;
174 	u32 seqnum;
175 
176 	seqnum = atomic_inc_return(&queue->seqnum) % 0xfff;
177 
178 	/* First dword of the message is the message header - fill it in */
179 	*((u32 *) data) = (seqnum << 20) | (HFI_MSG_CMD << 16) |
180 		(dwords << 8) | id;
181 
182 	ret = a6xx_hfi_queue_write(gmu, queue, data, dwords);
183 	if (ret) {
184 		DRM_DEV_ERROR(gmu->dev, "Unable to send message %s id %d\n",
185 			a6xx_hfi_msg_id[id], seqnum);
186 		return ret;
187 	}
188 
189 	return a6xx_hfi_wait_for_ack(gmu, id, seqnum, payload, payload_size);
190 }
191 
a6xx_hfi_send_gmu_init(struct a6xx_gmu * gmu,int boot_state)192 static int a6xx_hfi_send_gmu_init(struct a6xx_gmu *gmu, int boot_state)
193 {
194 	struct a6xx_hfi_msg_gmu_init_cmd msg = { 0 };
195 
196 	msg.dbg_buffer_addr = (u32) gmu->debug.iova;
197 	msg.dbg_buffer_size = (u32) gmu->debug.size;
198 	msg.boot_state = boot_state;
199 
200 	return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_INIT, &msg, sizeof(msg),
201 		NULL, 0);
202 }
203 
a6xx_hfi_get_fw_version(struct a6xx_gmu * gmu,u32 * version)204 static int a6xx_hfi_get_fw_version(struct a6xx_gmu *gmu, u32 *version)
205 {
206 	struct a6xx_hfi_msg_fw_version msg = { 0 };
207 
208 	/* Currently supporting version 1.10 */
209 	msg.supported_version = (1 << 28) | (1 << 19) | (1 << 17);
210 
211 	return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_FW_VERSION, &msg, sizeof(msg),
212 		version, sizeof(*version));
213 }
214 
a6xx_hfi_send_perf_table_v1(struct a6xx_gmu * gmu)215 static int a6xx_hfi_send_perf_table_v1(struct a6xx_gmu *gmu)
216 {
217 	struct a6xx_hfi_msg_perf_table_v1 msg = { 0 };
218 	int i;
219 
220 	msg.num_gpu_levels = gmu->nr_gpu_freqs;
221 	msg.num_gmu_levels = gmu->nr_gmu_freqs;
222 
223 	for (i = 0; i < gmu->nr_gpu_freqs; i++) {
224 		msg.gx_votes[i].vote = gmu->gx_arc_votes[i];
225 		msg.gx_votes[i].freq = gmu->gpu_freqs[i] / 1000;
226 	}
227 
228 	for (i = 0; i < gmu->nr_gmu_freqs; i++) {
229 		msg.cx_votes[i].vote = gmu->cx_arc_votes[i];
230 		msg.cx_votes[i].freq = gmu->gmu_freqs[i] / 1000;
231 	}
232 
233 	return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_PERF_TABLE, &msg, sizeof(msg),
234 		NULL, 0);
235 }
236 
a6xx_hfi_send_perf_table(struct a6xx_gmu * gmu)237 static int a6xx_hfi_send_perf_table(struct a6xx_gmu *gmu)
238 {
239 	struct a6xx_hfi_msg_perf_table msg = { 0 };
240 	int i;
241 
242 	msg.num_gpu_levels = gmu->nr_gpu_freqs;
243 	msg.num_gmu_levels = gmu->nr_gmu_freqs;
244 
245 	for (i = 0; i < gmu->nr_gpu_freqs; i++) {
246 		msg.gx_votes[i].vote = gmu->gx_arc_votes[i];
247 		msg.gx_votes[i].acd = 0xffffffff;
248 		msg.gx_votes[i].freq = gmu->gpu_freqs[i] / 1000;
249 	}
250 
251 	for (i = 0; i < gmu->nr_gmu_freqs; i++) {
252 		msg.cx_votes[i].vote = gmu->cx_arc_votes[i];
253 		msg.cx_votes[i].freq = gmu->gmu_freqs[i] / 1000;
254 	}
255 
256 	return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_PERF_TABLE, &msg, sizeof(msg),
257 		NULL, 0);
258 }
259 
a618_build_bw_table(struct a6xx_hfi_msg_bw_table * msg)260 static void a618_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
261 {
262 	/* Send a single "off" entry since the 618 GMU doesn't do bus scaling */
263 	msg->bw_level_num = 1;
264 
265 	msg->ddr_cmds_num = 3;
266 	msg->ddr_wait_bitmask = 0x01;
267 
268 	msg->ddr_cmds_addrs[0] = 0x50000;
269 	msg->ddr_cmds_addrs[1] = 0x5003c;
270 	msg->ddr_cmds_addrs[2] = 0x5000c;
271 
272 	msg->ddr_cmds_data[0][0] =  0x40000000;
273 	msg->ddr_cmds_data[0][1] =  0x40000000;
274 	msg->ddr_cmds_data[0][2] =  0x40000000;
275 
276 	/*
277 	 * These are the CX (CNOC) votes - these are used by the GMU but the
278 	 * votes are known and fixed for the target
279 	 */
280 	msg->cnoc_cmds_num = 1;
281 	msg->cnoc_wait_bitmask = 0x01;
282 
283 	msg->cnoc_cmds_addrs[0] = 0x5007c;
284 	msg->cnoc_cmds_data[0][0] =  0x40000000;
285 	msg->cnoc_cmds_data[1][0] =  0x60000001;
286 }
287 
a619_build_bw_table(struct a6xx_hfi_msg_bw_table * msg)288 static void a619_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
289 {
290 	msg->bw_level_num = 13;
291 
292 	msg->ddr_cmds_num = 3;
293 	msg->ddr_wait_bitmask = 0x0;
294 
295 	msg->ddr_cmds_addrs[0] = 0x50000;
296 	msg->ddr_cmds_addrs[1] = 0x50004;
297 	msg->ddr_cmds_addrs[2] = 0x50080;
298 
299 	msg->ddr_cmds_data[0][0]  = 0x40000000;
300 	msg->ddr_cmds_data[0][1]  = 0x40000000;
301 	msg->ddr_cmds_data[0][2]  = 0x40000000;
302 	msg->ddr_cmds_data[1][0]  = 0x6000030c;
303 	msg->ddr_cmds_data[1][1]  = 0x600000db;
304 	msg->ddr_cmds_data[1][2]  = 0x60000008;
305 	msg->ddr_cmds_data[2][0]  = 0x60000618;
306 	msg->ddr_cmds_data[2][1]  = 0x600001b6;
307 	msg->ddr_cmds_data[2][2]  = 0x60000008;
308 	msg->ddr_cmds_data[3][0]  = 0x60000925;
309 	msg->ddr_cmds_data[3][1]  = 0x60000291;
310 	msg->ddr_cmds_data[3][2]  = 0x60000008;
311 	msg->ddr_cmds_data[4][0]  = 0x60000dc1;
312 	msg->ddr_cmds_data[4][1]  = 0x600003dc;
313 	msg->ddr_cmds_data[4][2]  = 0x60000008;
314 	msg->ddr_cmds_data[5][0]  = 0x600010ad;
315 	msg->ddr_cmds_data[5][1]  = 0x600004ae;
316 	msg->ddr_cmds_data[5][2]  = 0x60000008;
317 	msg->ddr_cmds_data[6][0]  = 0x600014c3;
318 	msg->ddr_cmds_data[6][1]  = 0x600005d4;
319 	msg->ddr_cmds_data[6][2]  = 0x60000008;
320 	msg->ddr_cmds_data[7][0]  = 0x6000176a;
321 	msg->ddr_cmds_data[7][1]  = 0x60000693;
322 	msg->ddr_cmds_data[7][2]  = 0x60000008;
323 	msg->ddr_cmds_data[8][0]  = 0x60001f01;
324 	msg->ddr_cmds_data[8][1]  = 0x600008b5;
325 	msg->ddr_cmds_data[8][2]  = 0x60000008;
326 	msg->ddr_cmds_data[9][0]  = 0x60002940;
327 	msg->ddr_cmds_data[9][1]  = 0x60000b95;
328 	msg->ddr_cmds_data[9][2]  = 0x60000008;
329 	msg->ddr_cmds_data[10][0] = 0x60002f68;
330 	msg->ddr_cmds_data[10][1] = 0x60000d50;
331 	msg->ddr_cmds_data[10][2] = 0x60000008;
332 	msg->ddr_cmds_data[11][0] = 0x60003700;
333 	msg->ddr_cmds_data[11][1] = 0x60000f71;
334 	msg->ddr_cmds_data[11][2] = 0x60000008;
335 	msg->ddr_cmds_data[12][0] = 0x60003fce;
336 	msg->ddr_cmds_data[12][1] = 0x600011ea;
337 	msg->ddr_cmds_data[12][2] = 0x60000008;
338 
339 	msg->cnoc_cmds_num = 1;
340 	msg->cnoc_wait_bitmask = 0x0;
341 
342 	msg->cnoc_cmds_addrs[0] = 0x50054;
343 
344 	msg->cnoc_cmds_data[0][0] = 0x40000000;
345 }
346 
a640_build_bw_table(struct a6xx_hfi_msg_bw_table * msg)347 static void a640_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
348 {
349 	/*
350 	 * Send a single "off" entry just to get things running
351 	 * TODO: bus scaling
352 	 */
353 	msg->bw_level_num = 1;
354 
355 	msg->ddr_cmds_num = 3;
356 	msg->ddr_wait_bitmask = 0x01;
357 
358 	msg->ddr_cmds_addrs[0] = 0x50000;
359 	msg->ddr_cmds_addrs[1] = 0x5003c;
360 	msg->ddr_cmds_addrs[2] = 0x5000c;
361 
362 	msg->ddr_cmds_data[0][0] =  0x40000000;
363 	msg->ddr_cmds_data[0][1] =  0x40000000;
364 	msg->ddr_cmds_data[0][2] =  0x40000000;
365 
366 	/*
367 	 * These are the CX (CNOC) votes - these are used by the GMU but the
368 	 * votes are known and fixed for the target
369 	 */
370 	msg->cnoc_cmds_num = 3;
371 	msg->cnoc_wait_bitmask = 0x01;
372 
373 	msg->cnoc_cmds_addrs[0] = 0x50034;
374 	msg->cnoc_cmds_addrs[1] = 0x5007c;
375 	msg->cnoc_cmds_addrs[2] = 0x5004c;
376 
377 	msg->cnoc_cmds_data[0][0] =  0x40000000;
378 	msg->cnoc_cmds_data[0][1] =  0x00000000;
379 	msg->cnoc_cmds_data[0][2] =  0x40000000;
380 
381 	msg->cnoc_cmds_data[1][0] =  0x60000001;
382 	msg->cnoc_cmds_data[1][1] =  0x20000001;
383 	msg->cnoc_cmds_data[1][2] =  0x60000001;
384 }
385 
a650_build_bw_table(struct a6xx_hfi_msg_bw_table * msg)386 static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
387 {
388 	/*
389 	 * Send a single "off" entry just to get things running
390 	 * TODO: bus scaling
391 	 */
392 	msg->bw_level_num = 1;
393 
394 	msg->ddr_cmds_num = 3;
395 	msg->ddr_wait_bitmask = 0x01;
396 
397 	msg->ddr_cmds_addrs[0] = 0x50000;
398 	msg->ddr_cmds_addrs[1] = 0x50004;
399 	msg->ddr_cmds_addrs[2] = 0x5007c;
400 
401 	msg->ddr_cmds_data[0][0] =  0x40000000;
402 	msg->ddr_cmds_data[0][1] =  0x40000000;
403 	msg->ddr_cmds_data[0][2] =  0x40000000;
404 
405 	/*
406 	 * These are the CX (CNOC) votes - these are used by the GMU but the
407 	 * votes are known and fixed for the target
408 	 */
409 	msg->cnoc_cmds_num = 1;
410 	msg->cnoc_wait_bitmask = 0x01;
411 
412 	msg->cnoc_cmds_addrs[0] = 0x500a4;
413 	msg->cnoc_cmds_data[0][0] =  0x40000000;
414 	msg->cnoc_cmds_data[1][0] =  0x60000001;
415 }
416 
a660_build_bw_table(struct a6xx_hfi_msg_bw_table * msg)417 static void a660_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
418 {
419 	/*
420 	 * Send a single "off" entry just to get things running
421 	 * TODO: bus scaling
422 	 */
423 	msg->bw_level_num = 1;
424 
425 	msg->ddr_cmds_num = 3;
426 	msg->ddr_wait_bitmask = 0x01;
427 
428 	msg->ddr_cmds_addrs[0] = 0x50004;
429 	msg->ddr_cmds_addrs[1] = 0x500a0;
430 	msg->ddr_cmds_addrs[2] = 0x50000;
431 
432 	msg->ddr_cmds_data[0][0] =  0x40000000;
433 	msg->ddr_cmds_data[0][1] =  0x40000000;
434 	msg->ddr_cmds_data[0][2] =  0x40000000;
435 
436 	/*
437 	 * These are the CX (CNOC) votes - these are used by the GMU but the
438 	 * votes are known and fixed for the target
439 	 */
440 	msg->cnoc_cmds_num = 1;
441 	msg->cnoc_wait_bitmask = 0x01;
442 
443 	msg->cnoc_cmds_addrs[0] = 0x50070;
444 	msg->cnoc_cmds_data[0][0] =  0x40000000;
445 	msg->cnoc_cmds_data[1][0] =  0x60000001;
446 }
447 
adreno_7c3_build_bw_table(struct a6xx_hfi_msg_bw_table * msg)448 static void adreno_7c3_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
449 {
450 	/*
451 	 * Send a single "off" entry just to get things running
452 	 * TODO: bus scaling
453 	 */
454 	msg->bw_level_num = 1;
455 
456 	msg->ddr_cmds_num = 3;
457 	msg->ddr_wait_bitmask = 0x07;
458 
459 	msg->ddr_cmds_addrs[0] = 0x50004;
460 	msg->ddr_cmds_addrs[1] = 0x50000;
461 	msg->ddr_cmds_addrs[2] = 0x50088;
462 
463 	msg->ddr_cmds_data[0][0] =  0x40000000;
464 	msg->ddr_cmds_data[0][1] =  0x40000000;
465 	msg->ddr_cmds_data[0][2] =  0x40000000;
466 
467 	/*
468 	 * These are the CX (CNOC) votes - these are used by the GMU but the
469 	 * votes are known and fixed for the target
470 	 */
471 	msg->cnoc_cmds_num = 1;
472 	msg->cnoc_wait_bitmask = 0x01;
473 
474 	msg->cnoc_cmds_addrs[0] = 0x5006c;
475 	msg->cnoc_cmds_data[0][0] =  0x40000000;
476 	msg->cnoc_cmds_data[1][0] =  0x60000001;
477 }
a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table * msg)478 static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
479 {
480 	/* Send a single "off" entry since the 630 GMU doesn't do bus scaling */
481 	msg->bw_level_num = 1;
482 
483 	msg->ddr_cmds_num = 3;
484 	msg->ddr_wait_bitmask = 0x07;
485 
486 	msg->ddr_cmds_addrs[0] = 0x50000;
487 	msg->ddr_cmds_addrs[1] = 0x5005c;
488 	msg->ddr_cmds_addrs[2] = 0x5000c;
489 
490 	msg->ddr_cmds_data[0][0] =  0x40000000;
491 	msg->ddr_cmds_data[0][1] =  0x40000000;
492 	msg->ddr_cmds_data[0][2] =  0x40000000;
493 
494 	/*
495 	 * These are the CX (CNOC) votes.  This is used but the values for the
496 	 * sdm845 GMU are known and fixed so we can hard code them.
497 	 */
498 
499 	msg->cnoc_cmds_num = 3;
500 	msg->cnoc_wait_bitmask = 0x05;
501 
502 	msg->cnoc_cmds_addrs[0] = 0x50034;
503 	msg->cnoc_cmds_addrs[1] = 0x5007c;
504 	msg->cnoc_cmds_addrs[2] = 0x5004c;
505 
506 	msg->cnoc_cmds_data[0][0] =  0x40000000;
507 	msg->cnoc_cmds_data[0][1] =  0x00000000;
508 	msg->cnoc_cmds_data[0][2] =  0x40000000;
509 
510 	msg->cnoc_cmds_data[1][0] =  0x60000001;
511 	msg->cnoc_cmds_data[1][1] =  0x20000001;
512 	msg->cnoc_cmds_data[1][2] =  0x60000001;
513 }
514 
515 
a6xx_hfi_send_bw_table(struct a6xx_gmu * gmu)516 static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
517 {
518 	struct a6xx_hfi_msg_bw_table msg = { 0 };
519 	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
520 	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
521 
522 	if (adreno_is_a618(adreno_gpu))
523 		a618_build_bw_table(&msg);
524 	else if (adreno_is_a619(adreno_gpu))
525 		a619_build_bw_table(&msg);
526 	else if (adreno_is_a640_family(adreno_gpu))
527 		a640_build_bw_table(&msg);
528 	else if (adreno_is_a650(adreno_gpu))
529 		a650_build_bw_table(&msg);
530 	else if (adreno_is_7c3(adreno_gpu))
531 		adreno_7c3_build_bw_table(&msg);
532 	else if (adreno_is_a660(adreno_gpu))
533 		a660_build_bw_table(&msg);
534 	else
535 		a6xx_build_bw_table(&msg);
536 
537 	return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_BW_TABLE, &msg, sizeof(msg),
538 		NULL, 0);
539 }
540 
a6xx_hfi_send_test(struct a6xx_gmu * gmu)541 static int a6xx_hfi_send_test(struct a6xx_gmu *gmu)
542 {
543 	struct a6xx_hfi_msg_test msg = { 0 };
544 
545 	return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_TEST, &msg, sizeof(msg),
546 		NULL, 0);
547 }
548 
a6xx_hfi_send_start(struct a6xx_gmu * gmu)549 static int a6xx_hfi_send_start(struct a6xx_gmu *gmu)
550 {
551 	struct a6xx_hfi_msg_start msg = { 0 };
552 
553 	return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_START, &msg, sizeof(msg),
554 		NULL, 0);
555 }
556 
a6xx_hfi_send_core_fw_start(struct a6xx_gmu * gmu)557 static int a6xx_hfi_send_core_fw_start(struct a6xx_gmu *gmu)
558 {
559 	struct a6xx_hfi_msg_core_fw_start msg = { 0 };
560 
561 	return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_CORE_FW_START, &msg,
562 		sizeof(msg), NULL, 0);
563 }
564 
a6xx_hfi_set_freq(struct a6xx_gmu * gmu,int index)565 int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index)
566 {
567 	struct a6xx_hfi_gx_bw_perf_vote_cmd msg = { 0 };
568 
569 	msg.ack_type = 1; /* blocking */
570 	msg.freq = index;
571 	msg.bw = 0; /* TODO: bus scaling */
572 
573 	return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_GX_BW_PERF_VOTE, &msg,
574 		sizeof(msg), NULL, 0);
575 }
576 
a6xx_hfi_send_prep_slumber(struct a6xx_gmu * gmu)577 int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu)
578 {
579 	struct a6xx_hfi_prep_slumber_cmd msg = { 0 };
580 
581 	/* TODO: should freq and bw fields be non-zero ? */
582 
583 	return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_PREPARE_SLUMBER, &msg,
584 		sizeof(msg), NULL, 0);
585 }
586 
a6xx_hfi_start_v1(struct a6xx_gmu * gmu,int boot_state)587 static int a6xx_hfi_start_v1(struct a6xx_gmu *gmu, int boot_state)
588 {
589 	int ret;
590 
591 	ret = a6xx_hfi_send_gmu_init(gmu, boot_state);
592 	if (ret)
593 		return ret;
594 
595 	ret = a6xx_hfi_get_fw_version(gmu, NULL);
596 	if (ret)
597 		return ret;
598 
599 	/*
600 	 * We have to get exchange version numbers per the sequence but at this
601 	 * point th kernel driver doesn't need to know the exact version of
602 	 * the GMU firmware
603 	 */
604 
605 	ret = a6xx_hfi_send_perf_table_v1(gmu);
606 	if (ret)
607 		return ret;
608 
609 	ret = a6xx_hfi_send_bw_table(gmu);
610 	if (ret)
611 		return ret;
612 
613 	/*
614 	 * Let the GMU know that there won't be any more HFI messages until next
615 	 * boot
616 	 */
617 	a6xx_hfi_send_test(gmu);
618 
619 	return 0;
620 }
621 
a6xx_hfi_start(struct a6xx_gmu * gmu,int boot_state)622 int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state)
623 {
624 	int ret;
625 
626 	if (gmu->legacy)
627 		return a6xx_hfi_start_v1(gmu, boot_state);
628 
629 
630 	ret = a6xx_hfi_send_perf_table(gmu);
631 	if (ret)
632 		return ret;
633 
634 	ret = a6xx_hfi_send_bw_table(gmu);
635 	if (ret)
636 		return ret;
637 
638 	ret = a6xx_hfi_send_core_fw_start(gmu);
639 	if (ret)
640 		return ret;
641 
642 	/*
643 	 * Downstream driver sends this in its "a6xx_hw_init" equivalent,
644 	 * but seems to be no harm in sending it here
645 	 */
646 	ret = a6xx_hfi_send_start(gmu);
647 	if (ret)
648 		return ret;
649 
650 	return 0;
651 }
652 
a6xx_hfi_stop(struct a6xx_gmu * gmu)653 void a6xx_hfi_stop(struct a6xx_gmu *gmu)
654 {
655 	int i;
656 
657 	for (i = 0; i < ARRAY_SIZE(gmu->queues); i++) {
658 		struct a6xx_hfi_queue *queue = &gmu->queues[i];
659 
660 		if (!queue->header)
661 			continue;
662 
663 		if (queue->header->read_index != queue->header->write_index)
664 			DRM_DEV_ERROR(gmu->dev, "HFI queue %d is not empty\n", i);
665 
666 		queue->header->read_index = 0;
667 		queue->header->write_index = 0;
668 
669 		memset(&queue->history, 0xff, sizeof(queue->history));
670 		queue->history_idx = 0;
671 	}
672 }
673 
a6xx_hfi_queue_init(struct a6xx_hfi_queue * queue,struct a6xx_hfi_queue_header * header,void * virt,u64 iova,u32 id)674 static void a6xx_hfi_queue_init(struct a6xx_hfi_queue *queue,
675 		struct a6xx_hfi_queue_header *header, void *virt, u64 iova,
676 		u32 id)
677 {
678 	spin_lock_init(&queue->lock);
679 	queue->header = header;
680 	queue->data = virt;
681 	atomic_set(&queue->seqnum, 0);
682 
683 	memset(&queue->history, 0xff, sizeof(queue->history));
684 	queue->history_idx = 0;
685 
686 	/* Set up the shared memory header */
687 	header->iova = iova;
688 	header->type =  10 << 8 | id;
689 	header->status = 1;
690 	header->size = SZ_4K >> 2;
691 	header->msg_size = 0;
692 	header->dropped = 0;
693 	header->rx_watermark = 1;
694 	header->tx_watermark = 1;
695 	header->rx_request = 1;
696 	header->tx_request = 0;
697 	header->read_index = 0;
698 	header->write_index = 0;
699 }
700 
a6xx_hfi_init(struct a6xx_gmu * gmu)701 void a6xx_hfi_init(struct a6xx_gmu *gmu)
702 {
703 	struct a6xx_gmu_bo *hfi = &gmu->hfi;
704 	struct a6xx_hfi_queue_table_header *table = hfi->virt;
705 	struct a6xx_hfi_queue_header *headers = hfi->virt + sizeof(*table);
706 	u64 offset;
707 	int table_size;
708 
709 	/*
710 	 * The table size is the size of the table header plus all of the queue
711 	 * headers
712 	 */
713 	table_size = sizeof(*table);
714 	table_size += (ARRAY_SIZE(gmu->queues) *
715 		sizeof(struct a6xx_hfi_queue_header));
716 
717 	table->version = 0;
718 	table->size = table_size;
719 	/* First queue header is located immediately after the table header */
720 	table->qhdr0_offset = sizeof(*table) >> 2;
721 	table->qhdr_size = sizeof(struct a6xx_hfi_queue_header) >> 2;
722 	table->num_queues = ARRAY_SIZE(gmu->queues);
723 	table->active_queues = ARRAY_SIZE(gmu->queues);
724 
725 	/* Command queue */
726 	offset = SZ_4K;
727 	a6xx_hfi_queue_init(&gmu->queues[0], &headers[0], hfi->virt + offset,
728 		hfi->iova + offset, 0);
729 
730 	/* GMU response queue */
731 	offset += SZ_4K;
732 	a6xx_hfi_queue_init(&gmu->queues[1], &headers[1], hfi->virt + offset,
733 		hfi->iova + offset, gmu->legacy ? 4 : 1);
734 }
735