1 #ifndef DSI_PHY_28NM_8960_XML
2 #define DSI_PHY_28NM_8960_XML
3 
4 /* Autogenerated file, DO NOT EDIT manually!
5 
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9 
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/tmp/mesa/src/freedreno/registers/msm.xml                   (    944 bytes, from 2022-03-03 01:18:13)
12 - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml   (   1572 bytes, from 2020-12-31 19:26:32)
13 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp4.xml              (  20912 bytes, from 2021-01-30 18:25:22)
14 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp_common.xml        (   2849 bytes, from 2021-01-30 18:25:22)
15 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp5.xml              (  37461 bytes, from 2021-01-30 18:25:22)
16 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi.xml               (  17560 bytes, from 2021-09-16 22:37:02)
17 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml        (   3236 bytes, from 2021-07-22 15:21:56)
18 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml (   4935 bytes, from 2021-07-22 15:21:56)
19 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml      (   7004 bytes, from 2021-07-22 15:21:56)
20 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml      (   3712 bytes, from 2021-07-22 15:21:56)
21 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml      (   5381 bytes, from 2021-07-22 15:21:56)
22 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml      (   4499 bytes, from 2021-07-22 15:21:56)
23 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml       (  11007 bytes, from 2022-03-03 01:18:13)
24 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/sfpb.xml              (    602 bytes, from 2021-01-30 18:25:22)
25 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/mmss_cc.xml           (   1686 bytes, from 2021-01-30 18:25:22)
26 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/qfprom.xml           (    600 bytes, from 2021-01-30 18:25:22)
27 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/hdmi.xml             (  41874 bytes, from 2021-01-30 18:25:22)
28 - /home/robclark/tmp/mesa/src/freedreno/registers/edp/edp.xml               (  10416 bytes, from 2021-01-30 18:25:22)
29 
30 Copyright (C) 2013-2021 by the following authors:
31 - Rob Clark <robdclark@gmail.com> (robclark)
32 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
33 
34 Permission is hereby granted, free of charge, to any person obtaining
35 a copy of this software and associated documentation files (the
36 "Software"), to deal in the Software without restriction, including
37 without limitation the rights to use, copy, modify, merge, publish,
38 distribute, sublicense, and/or sell copies of the Software, and to
39 permit persons to whom the Software is furnished to do so, subject to
40 the following conditions:
41 
42 The above copyright notice and this permission notice (including the
43 next paragraph) shall be included in all copies or substantial
44 portions of the Software.
45 
46 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
47 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
48 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
49 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
50 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
51 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
52 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
53 */
54 
55 
REG_DSI_28nm_8960_PHY_LN(uint32_t i0)56 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
57 
REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0)58 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
59 
REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0)60 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
61 
REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0)62 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
63 
REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0)64 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; }
65 
REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0)66 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; }
67 
REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0)68 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; }
69 
70 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_0			0x00000100
71 
72 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_1			0x00000104
73 
74 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_2			0x00000108
75 
76 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH		0x0000010c
77 
78 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0			0x00000114
79 
80 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1			0x00000118
81 
82 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0			0x00000140
83 #define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK		0x000000ff
84 #define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT		0
DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)85 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
86 {
87 	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
88 }
89 
90 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1			0x00000144
91 #define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK		0x000000ff
92 #define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT	0
DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)93 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
94 {
95 	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
96 }
97 
98 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2			0x00000148
99 #define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK	0x000000ff
100 #define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT	0
DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)101 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
102 {
103 	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
104 }
105 
106 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3			0x0000014c
107 
108 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4			0x00000150
109 #define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK		0x000000ff
110 #define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT		0
DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)111 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
112 {
113 	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
114 }
115 
116 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5			0x00000154
117 #define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK		0x000000ff
118 #define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT		0
DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)119 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
120 {
121 	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
122 }
123 
124 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6			0x00000158
125 #define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK	0x000000ff
126 #define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT	0
DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)127 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
128 {
129 	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
130 }
131 
132 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7			0x0000015c
133 #define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK		0x000000ff
134 #define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT		0
DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)135 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
136 {
137 	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
138 }
139 
140 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8			0x00000160
141 #define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK		0x000000ff
142 #define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT		0
DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)143 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
144 {
145 	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK;
146 }
147 
148 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9			0x00000164
149 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK		0x00000007
150 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT		0
DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)151 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
152 {
153 	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK;
154 }
155 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK		0x00000070
156 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT		4
DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)157 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
158 {
159 	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK;
160 }
161 
162 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10			0x00000168
163 #define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK		0x00000007
164 #define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT		0
DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)165 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
166 {
167 	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK;
168 }
169 
170 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11			0x0000016c
171 #define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK	0x000000ff
172 #define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT	0
DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)173 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
174 {
175 	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
176 }
177 
178 #define REG_DSI_28nm_8960_PHY_CTRL_0				0x00000170
179 
180 #define REG_DSI_28nm_8960_PHY_CTRL_1				0x00000174
181 
182 #define REG_DSI_28nm_8960_PHY_CTRL_2				0x00000178
183 
184 #define REG_DSI_28nm_8960_PHY_CTRL_3				0x0000017c
185 
186 #define REG_DSI_28nm_8960_PHY_STRENGTH_0			0x00000180
187 
188 #define REG_DSI_28nm_8960_PHY_STRENGTH_1			0x00000184
189 
190 #define REG_DSI_28nm_8960_PHY_STRENGTH_2			0x00000188
191 
192 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_0			0x0000018c
193 
194 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_1			0x00000190
195 
196 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_2			0x00000194
197 
198 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_3			0x00000198
199 
200 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_4			0x0000019c
201 
202 #define REG_DSI_28nm_8960_PHY_LDO_CTRL				0x000001b0
203 
204 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0		0x00000000
205 
206 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1		0x00000004
207 
208 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2		0x00000008
209 
210 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3		0x0000000c
211 
212 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4		0x00000010
213 
214 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5		0x00000014
215 
216 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG	0x00000018
217 
218 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER		0x00000028
219 
220 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0			0x0000002c
221 
222 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1			0x00000030
223 
224 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2			0x00000034
225 
226 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0			0x00000038
227 
228 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1			0x0000003c
229 
230 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2			0x00000040
231 
232 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3			0x00000044
233 
234 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4			0x00000048
235 
236 #define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS			0x00000050
237 #define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY		0x00000010
238 
239 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_0			0x00000000
240 #define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE			0x00000001
241 
242 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_1			0x00000004
243 
244 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_2			0x00000008
245 
246 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_3			0x0000000c
247 
248 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_4			0x00000010
249 
250 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_5			0x00000014
251 
252 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_6			0x00000018
253 
254 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_7			0x0000001c
255 
256 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_8			0x00000020
257 
258 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_9			0x00000024
259 
260 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_10			0x00000028
261 
262 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_11			0x0000002c
263 
264 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_12			0x00000030
265 
266 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_13			0x00000034
267 
268 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_14			0x00000038
269 
270 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_15			0x0000003c
271 
272 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_16			0x00000040
273 
274 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_17			0x00000044
275 
276 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_18			0x00000048
277 
278 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_19			0x0000004c
279 
280 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_20			0x00000050
281 
282 #define REG_DSI_28nm_8960_PHY_PLL_RDY				0x00000080
283 #define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY			0x00000001
284 
285 
286 #endif /* DSI_PHY_28NM_8960_XML */
287