1 /*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22 #include "ctxgf100.h"
23
24 static void
gm20b_grctx_generate_main(struct gf100_gr_chan * chan)25 gm20b_grctx_generate_main(struct gf100_gr_chan *chan)
26 {
27 struct gf100_gr *gr = chan->gr;
28 struct nvkm_device *device = gr->base.engine.subdev.device;
29 const struct gf100_grctx_func *grctx = gr->func->grctx;
30 u32 idle_timeout;
31 int i, tmp;
32
33 gf100_gr_mmio(gr, gr->sw_ctx);
34
35 gf100_gr_wait_idle(gr);
36
37 idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000);
38
39 grctx->attrib_cb(chan, chan->attrib_cb->addr, grctx->attrib_cb_size(gr));
40 grctx->attrib(chan);
41
42 grctx->unkn(gr);
43
44 gf100_grctx_generate_floorsweep(gr);
45
46 for (i = 0; i < 8; i++)
47 nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
48
49 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
50
51 nvkm_wr32(device, 0x408908, nvkm_rd32(device, 0x410108) | 0x80000000);
52
53 for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
54 tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4);
55 nvkm_wr32(device, 0x4041c4, tmp);
56
57 gm200_grctx_generate_smid_config(gr);
58
59 gf100_gr_wait_idle(gr);
60
61 nvkm_wr32(device, 0x404154, idle_timeout);
62 gf100_gr_wait_idle(gr);
63
64 gf100_gr_mthd(gr, gr->method);
65 gf100_gr_wait_idle(gr);
66
67 gf100_gr_icmd(gr, gr->bundle);
68 grctx->pagepool(chan, chan->pagepool->addr);
69 grctx->bundle(chan, chan->bundle_cb->addr, grctx->bundle_size);
70 }
71
72 const struct gf100_grctx_func
73 gm20b_grctx = {
74 .main = gm20b_grctx_generate_main,
75 .unkn = gk104_grctx_generate_unkn,
76 .bundle = gm107_grctx_generate_bundle,
77 .bundle_size = 0x1800,
78 .bundle_min_gpm_fifo_depth = 0x182,
79 .bundle_token_limit = 0x1c0,
80 .pagepool = gm107_grctx_generate_pagepool,
81 .pagepool_size = 0x8000,
82 .attrib_cb_size = gf100_grctx_generate_attrib_cb_size,
83 .attrib_cb = gm107_grctx_generate_attrib_cb,
84 .attrib = gm107_grctx_generate_attrib,
85 .attrib_nr_max = 0x600,
86 .attrib_nr = 0x400,
87 .alpha_nr_max = 0xc00,
88 .alpha_nr = 0x800,
89 .sm_id = gm107_grctx_generate_sm_id,
90 .rop_mapping = gf117_grctx_generate_rop_mapping,
91 };
92