1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * HDMI header definition for OMAP4 HDMI core IP
4  *
5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
6  */
7 
8 #ifndef _HDMI4_CORE_H_
9 #define _HDMI4_CORE_H_
10 
11 #include "hdmi.h"
12 
13 /* OMAP4 HDMI IP Core System */
14 
15 #define HDMI_CORE_SYS_VND_IDL			0x0
16 #define HDMI_CORE_SYS_DEV_IDL			0x8
17 #define HDMI_CORE_SYS_DEV_IDH			0xC
18 #define HDMI_CORE_SYS_DEV_REV			0x10
19 #define HDMI_CORE_SYS_SRST			0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1			0x20
21 #define HDMI_CORE_SYS_SYS_STAT			0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3			0x28
23 #define HDMI_CORE_SYS_DCTL			0x34
24 #define HDMI_CORE_SYS_DE_DLY			0xC8
25 #define HDMI_CORE_SYS_DE_CTRL			0xCC
26 #define HDMI_CORE_SYS_DE_TOP			0xD0
27 #define HDMI_CORE_SYS_DE_CNTL			0xD8
28 #define HDMI_CORE_SYS_DE_CNTH			0xDC
29 #define HDMI_CORE_SYS_DE_LINL			0xE0
30 #define HDMI_CORE_SYS_DE_LINH_1			0xE4
31 #define HDMI_CORE_SYS_HRES_L			0xE8
32 #define HDMI_CORE_SYS_HRES_H			0xEC
33 #define HDMI_CORE_SYS_VRES_L			0xF0
34 #define HDMI_CORE_SYS_VRES_H			0xF4
35 #define HDMI_CORE_SYS_IADJUST			0xF8
36 #define HDMI_CORE_SYS_POLDETECT			0xFC
37 #define HDMI_CORE_SYS_HWIDTH1			0x110
38 #define HDMI_CORE_SYS_HWIDTH2			0x114
39 #define HDMI_CORE_SYS_VWIDTH			0x11C
40 #define HDMI_CORE_SYS_VID_CTRL			0x120
41 #define HDMI_CORE_SYS_VID_ACEN			0x124
42 #define HDMI_CORE_SYS_VID_MODE			0x128
43 #define HDMI_CORE_SYS_VID_BLANK1		0x12C
44 #define HDMI_CORE_SYS_VID_BLANK2		0x130
45 #define HDMI_CORE_SYS_VID_BLANK3		0x134
46 #define HDMI_CORE_SYS_DC_HEADER			0x138
47 #define HDMI_CORE_SYS_VID_DITHER		0x13C
48 #define HDMI_CORE_SYS_RGB2XVYCC_CT		0x140
49 #define HDMI_CORE_SYS_R2Y_COEFF_LOW		0x144
50 #define HDMI_CORE_SYS_R2Y_COEFF_UP		0x148
51 #define HDMI_CORE_SYS_G2Y_COEFF_LOW		0x14C
52 #define HDMI_CORE_SYS_G2Y_COEFF_UP		0x150
53 #define HDMI_CORE_SYS_B2Y_COEFF_LOW		0x154
54 #define HDMI_CORE_SYS_B2Y_COEFF_UP		0x158
55 #define HDMI_CORE_SYS_R2CB_COEFF_LOW		0x15C
56 #define HDMI_CORE_SYS_R2CB_COEFF_UP		0x160
57 #define HDMI_CORE_SYS_G2CB_COEFF_LOW		0x164
58 #define HDMI_CORE_SYS_G2CB_COEFF_UP		0x168
59 #define HDMI_CORE_SYS_B2CB_COEFF_LOW		0x16C
60 #define HDMI_CORE_SYS_B2CB_COEFF_UP		0x170
61 #define HDMI_CORE_SYS_R2CR_COEFF_LOW		0x174
62 #define HDMI_CORE_SYS_R2CR_COEFF_UP		0x178
63 #define HDMI_CORE_SYS_G2CR_COEFF_LOW		0x17C
64 #define HDMI_CORE_SYS_G2CR_COEFF_UP		0x180
65 #define HDMI_CORE_SYS_B2CR_COEFF_LOW		0x184
66 #define HDMI_CORE_SYS_B2CR_COEFF_UP		0x188
67 #define HDMI_CORE_SYS_RGB_OFFSET_LOW		0x18C
68 #define HDMI_CORE_SYS_RGB_OFFSET_UP		0x190
69 #define HDMI_CORE_SYS_Y_OFFSET_LOW		0x194
70 #define HDMI_CORE_SYS_Y_OFFSET_UP		0x198
71 #define HDMI_CORE_SYS_CBCR_OFFSET_LOW		0x19C
72 #define HDMI_CORE_SYS_CBCR_OFFSET_UP		0x1A0
73 #define HDMI_CORE_SYS_INTR_STATE		0x1C0
74 #define HDMI_CORE_SYS_INTR1			0x1C4
75 #define HDMI_CORE_SYS_INTR2			0x1C8
76 #define HDMI_CORE_SYS_INTR3			0x1CC
77 #define HDMI_CORE_SYS_INTR4			0x1D0
78 #define HDMI_CORE_SYS_INTR_UNMASK1		0x1D4
79 #define HDMI_CORE_SYS_INTR_UNMASK2		0x1D8
80 #define HDMI_CORE_SYS_INTR_UNMASK3		0x1DC
81 #define HDMI_CORE_SYS_INTR_UNMASK4		0x1E0
82 #define HDMI_CORE_SYS_INTR_CTRL			0x1E4
83 #define HDMI_CORE_SYS_TMDS_CTRL			0x208
84 
85 /* value definitions for HDMI_CORE_SYS_SYS_CTRL1 fields */
86 #define HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC	0x1
87 #define HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC	0x1
88 #define HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS	0x1
89 #define HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE	0x1
90 
91 /* HDMI DDC E-DID */
92 #define HDMI_CORE_DDC_ADDR			0x3B4
93 #define HDMI_CORE_DDC_SEGM			0x3B8
94 #define HDMI_CORE_DDC_OFFSET			0x3BC
95 #define HDMI_CORE_DDC_COUNT1			0x3C0
96 #define HDMI_CORE_DDC_COUNT2			0x3C4
97 #define HDMI_CORE_DDC_STATUS			0x3C8
98 #define HDMI_CORE_DDC_CMD			0x3CC
99 #define HDMI_CORE_DDC_DATA			0x3D0
100 
101 /* HDMI IP Core Audio Video */
102 
103 #define HDMI_CORE_AV_ACR_CTRL			0x4
104 #define HDMI_CORE_AV_FREQ_SVAL			0x8
105 #define HDMI_CORE_AV_N_SVAL1			0xC
106 #define HDMI_CORE_AV_N_SVAL2			0x10
107 #define HDMI_CORE_AV_N_SVAL3			0x14
108 #define HDMI_CORE_AV_CTS_SVAL1			0x18
109 #define HDMI_CORE_AV_CTS_SVAL2			0x1C
110 #define HDMI_CORE_AV_CTS_SVAL3			0x20
111 #define HDMI_CORE_AV_CTS_HVAL1			0x24
112 #define HDMI_CORE_AV_CTS_HVAL2			0x28
113 #define HDMI_CORE_AV_CTS_HVAL3			0x2C
114 #define HDMI_CORE_AV_AUD_MODE			0x50
115 #define HDMI_CORE_AV_SPDIF_CTRL			0x54
116 #define HDMI_CORE_AV_HW_SPDIF_FS		0x60
117 #define HDMI_CORE_AV_SWAP_I2S			0x64
118 #define HDMI_CORE_AV_SPDIF_ERTH			0x6C
119 #define HDMI_CORE_AV_I2S_IN_MAP			0x70
120 #define HDMI_CORE_AV_I2S_IN_CTRL		0x74
121 #define HDMI_CORE_AV_I2S_CHST0			0x78
122 #define HDMI_CORE_AV_I2S_CHST1			0x7C
123 #define HDMI_CORE_AV_I2S_CHST2			0x80
124 #define HDMI_CORE_AV_I2S_CHST4			0x84
125 #define HDMI_CORE_AV_I2S_CHST5			0x88
126 #define HDMI_CORE_AV_ASRC			0x8C
127 #define HDMI_CORE_AV_I2S_IN_LEN			0x90
128 #define HDMI_CORE_AV_HDMI_CTRL			0xBC
129 #define HDMI_CORE_AV_AUDO_TXSTAT		0xC0
130 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_1		0xCC
131 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_2		0xD0
132 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_3		0xD4
133 #define HDMI_CORE_AV_TEST_TXCTRL		0xF0
134 #define HDMI_CORE_AV_DPD			0xF4
135 #define HDMI_CORE_AV_PB_CTRL1			0xF8
136 #define HDMI_CORE_AV_PB_CTRL2			0xFC
137 #define HDMI_CORE_AV_AVI_BASE			0x100
138 #define HDMI_CORE_AV_AVI_TYPE			0x100
139 #define HDMI_CORE_AV_AVI_VERS			0x104
140 #define HDMI_CORE_AV_AVI_LEN			0x108
141 #define HDMI_CORE_AV_AVI_CHSUM			0x10C
142 #define HDMI_CORE_AV_AVI_DBYTE(n)		(n * 4 + 0x110)
143 #define HDMI_CORE_AV_SPD_TYPE			0x180
144 #define HDMI_CORE_AV_SPD_VERS			0x184
145 #define HDMI_CORE_AV_SPD_LEN			0x188
146 #define HDMI_CORE_AV_SPD_CHSUM			0x18C
147 #define HDMI_CORE_AV_SPD_DBYTE(n)		(n * 4 + 0x190)
148 #define HDMI_CORE_AV_AUDIO_TYPE			0x200
149 #define HDMI_CORE_AV_AUDIO_VERS			0x204
150 #define HDMI_CORE_AV_AUDIO_LEN			0x208
151 #define HDMI_CORE_AV_AUDIO_CHSUM		0x20C
152 #define HDMI_CORE_AV_AUD_DBYTE(n)		(n * 4 + 0x210)
153 #define HDMI_CORE_AV_MPEG_TYPE			0x280
154 #define HDMI_CORE_AV_MPEG_VERS			0x284
155 #define HDMI_CORE_AV_MPEG_LEN			0x288
156 #define HDMI_CORE_AV_MPEG_CHSUM			0x28C
157 #define HDMI_CORE_AV_MPEG_DBYTE(n)		(n * 4 + 0x290)
158 #define HDMI_CORE_AV_GEN_DBYTE(n)		(n * 4 + 0x300)
159 #define HDMI_CORE_AV_CP_BYTE1			0x37C
160 #define HDMI_CORE_AV_GEN2_DBYTE(n)		(n * 4 + 0x380)
161 #define HDMI_CORE_AV_CEC_ADDR_ID		0x3FC
162 
163 #define HDMI_CORE_AV_SPD_DBYTE_ELSIZE		0x4
164 #define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE		0x4
165 #define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE		0x4
166 #define HDMI_CORE_AV_GEN_DBYTE_ELSIZE		0x4
167 
168 #define HDMI_CORE_AV_AVI_DBYTE_NELEMS		15
169 #define HDMI_CORE_AV_SPD_DBYTE_NELEMS		27
170 #define HDMI_CORE_AV_AUD_DBYTE_NELEMS		10
171 #define HDMI_CORE_AV_MPEG_DBYTE_NELEMS		27
172 #define HDMI_CORE_AV_GEN_DBYTE_NELEMS		31
173 #define HDMI_CORE_AV_GEN2_DBYTE_NELEMS		31
174 
175 enum hdmi_core_inputbus_width {
176 	HDMI_INPUT_8BIT = 0,
177 	HDMI_INPUT_10BIT = 1,
178 	HDMI_INPUT_12BIT = 2
179 };
180 
181 enum hdmi_core_dither_trunc {
182 	HDMI_OUTPUTTRUNCATION_8BIT = 0,
183 	HDMI_OUTPUTTRUNCATION_10BIT = 1,
184 	HDMI_OUTPUTTRUNCATION_12BIT = 2,
185 	HDMI_OUTPUTDITHER_8BIT = 3,
186 	HDMI_OUTPUTDITHER_10BIT = 4,
187 	HDMI_OUTPUTDITHER_12BIT = 5
188 };
189 
190 enum hdmi_core_deepcolor_ed {
191 	HDMI_DEEPCOLORPACKECTDISABLE = 0,
192 	HDMI_DEEPCOLORPACKECTENABLE = 1
193 };
194 
195 enum hdmi_core_packet_mode {
196 	HDMI_PACKETMODERESERVEDVALUE = 0,
197 	HDMI_PACKETMODE24BITPERPIXEL = 4,
198 	HDMI_PACKETMODE30BITPERPIXEL = 5,
199 	HDMI_PACKETMODE36BITPERPIXEL = 6,
200 	HDMI_PACKETMODE48BITPERPIXEL = 7
201 };
202 
203 enum hdmi_core_tclkselclkmult {
204 	HDMI_FPLL05IDCK = 0,
205 	HDMI_FPLL10IDCK = 1,
206 	HDMI_FPLL20IDCK = 2,
207 	HDMI_FPLL40IDCK = 3
208 };
209 
210 enum hdmi_core_packet_ctrl {
211 	HDMI_PACKETENABLE = 1,
212 	HDMI_PACKETDISABLE = 0,
213 	HDMI_PACKETREPEATON = 1,
214 	HDMI_PACKETREPEATOFF = 0
215 };
216 
217 enum hdmi_audio_i2s_config {
218 	HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0,
219 	HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1,
220 	HDMI_AUDIO_I2S_SCK_EDGE_FALLING = 0,
221 	HDMI_AUDIO_I2S_SCK_EDGE_RISING = 1,
222 	HDMI_AUDIO_I2S_VBIT_FOR_PCM = 0,
223 	HDMI_AUDIO_I2S_VBIT_FOR_COMPRESSED = 1,
224 	HDMI_AUDIO_I2S_FIRST_BIT_SHIFT = 0,
225 	HDMI_AUDIO_I2S_FIRST_BIT_NO_SHIFT = 1,
226 	HDMI_AUDIO_I2S_SD0_EN = 1,
227 	HDMI_AUDIO_I2S_SD1_EN = 1 << 1,
228 	HDMI_AUDIO_I2S_SD2_EN = 1 << 2,
229 	HDMI_AUDIO_I2S_SD3_EN = 1 << 3,
230 };
231 
232 struct hdmi_core_video_config {
233 	enum hdmi_core_inputbus_width	ip_bus_width;
234 	enum hdmi_core_dither_trunc	op_dither_truc;
235 	enum hdmi_core_deepcolor_ed	deep_color_pkt;
236 	enum hdmi_core_packet_mode	pkt_mode;
237 	enum hdmi_core_hdmi_dvi		hdmi_dvi;
238 	enum hdmi_core_tclkselclkmult	tclk_sel_clkmult;
239 };
240 
241 struct hdmi_core_packet_enable_repeat {
242 	u32	audio_pkt;
243 	u32	audio_pkt_repeat;
244 	u32	avi_infoframe;
245 	u32	avi_infoframe_repeat;
246 	u32	gen_cntrl_pkt;
247 	u32	gen_cntrl_pkt_repeat;
248 	u32	generic_pkt;
249 	u32	generic_pkt_repeat;
250 };
251 
252 int hdmi4_core_ddc_init(struct hdmi_core_data *core);
253 int hdmi4_core_ddc_read(void *data, u8 *buf, unsigned int block, size_t len);
254 
255 void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
256 		struct hdmi_config *cfg);
257 void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s);
258 int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core);
259 
260 int hdmi4_core_enable(struct hdmi_core_data *core);
261 void hdmi4_core_disable(struct hdmi_core_data *core);
262 void hdmi4_core_powerdown_disable(struct hdmi_core_data *core);
263 
264 int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
265 void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
266 int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
267 		struct omap_dss_audio *audio, u32 pclk);
268 #endif
269