1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * drivers/i2c/busses/i2c-ibm_iic.h
4  *
5  * Support for the IIC peripheral on IBM PPC 4xx
6  *
7  * Copyright (c) 2003 Zultys Technologies.
8  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
9  *
10  * Based on original work by
11  * 	Ian DaSilva  <idasilva@mvista.com>
12  *      Armin Kuster <akuster@mvista.com>
13  * 	Matt Porter  <mporter@mvista.com>
14  *
15  *      Copyright 2000-2003 MontaVista Software Inc.
16  */
17 #ifndef __I2C_IBM_IIC_H_
18 #define __I2C_IBM_IIC_H_
19 
20 #include <linux/i2c.h>
21 
22 struct iic_regs {
23 	u16 mdbuf;
24 	u16 sbbuf;
25 	u8 lmadr;
26 	u8 hmadr;
27 	u8 cntl;
28 	u8 mdcntl;
29 	u8 sts;
30 	u8 extsts;
31 	u8 lsadr;
32 	u8 hsadr;
33 	u8 clkdiv;
34 	u8 intmsk;
35 	u8 xfrcnt;
36 	u8 xtcntlss;
37 	u8 directcntl;
38 };
39 
40 struct ibm_iic_private {
41 	struct i2c_adapter adap;
42 	volatile struct iic_regs __iomem *vaddr;
43 	wait_queue_head_t wq;
44 	int idx;
45 	int irq;
46 	int fast_mode;
47 	u8  clckdiv;
48 };
49 
50 /* IICx_CNTL register */
51 #define CNTL_HMT	0x80
52 #define CNTL_AMD	0x40
53 #define CNTL_TCT_MASK	0x30
54 #define CNTL_TCT_SHIFT	4
55 #define CNTL_RPST	0x08
56 #define CNTL_CHT	0x04
57 #define CNTL_RW		0x02
58 #define CNTL_PT		0x01
59 
60 /* IICx_MDCNTL register */
61 #define MDCNTL_FSDB	0x80
62 #define MDCNTL_FMDB	0x40
63 #define MDCNTL_EGC	0x20
64 #define MDCNTL_FSM	0x10
65 #define MDCNTL_ESM	0x08
66 #define MDCNTL_EINT	0x04
67 #define MDCNTL_EUBS	0x02
68 #define MDCNTL_HSCL	0x01
69 
70 /* IICx_STS register */
71 #define STS_SSS		0x80
72 #define STS_SLPR	0x40
73 #define STS_MDBS	0x20
74 #define STS_MDBF	0x10
75 #define STS_SCMP	0x08
76 #define STS_ERR		0x04
77 #define STS_IRQA	0x02
78 #define STS_PT		0x01
79 
80 /* IICx_EXTSTS register */
81 #define EXTSTS_IRQP	0x80
82 #define EXTSTS_BCS_MASK	0x70
83 #define   EXTSTS_BCS_FREE  0x40
84 #define EXTSTS_IRQD	0x08
85 #define EXTSTS_LA	0x04
86 #define EXTSTS_ICT	0x02
87 #define EXTSTS_XFRA	0x01
88 
89 /* IICx_INTRMSK register */
90 #define INTRMSK_EIRC	0x80
91 #define INTRMSK_EIRS	0x40
92 #define INTRMSK_EIWC	0x20
93 #define INTRMSK_EIWS	0x10
94 #define INTRMSK_EIHE	0x08
95 #define INTRMSK_EIIC	0x04
96 #define INTRMSK_EITA	0x02
97 #define INTRMSK_EIMTC	0x01
98 
99 /* IICx_XFRCNT register */
100 #define XFRCNT_MTC_MASK	0x07
101 
102 /* IICx_XTCNTLSS register */
103 #define XTCNTLSS_SRC	0x80
104 #define XTCNTLSS_SRS	0x40
105 #define XTCNTLSS_SWC	0x20
106 #define XTCNTLSS_SWS	0x10
107 #define XTCNTLSS_SRST	0x01
108 
109 /* IICx_DIRECTCNTL register */
110 #define DIRCNTL_SDAC	0x08
111 #define DIRCNTL_SCC	0x04
112 #define DIRCNTL_MSDA	0x02
113 #define DIRCNTL_MSC	0x01
114 
115 /* Check if we really control the I2C bus and bus is free */
116 #define DIRCTNL_FREE(v)	(((v) & 0x0f) == 0x0f)
117 
118 #endif /* __I2C_IBM_IIC_H_ */
119