1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Freescale MXS LRADC ADC driver
4 *
5 * Copyright (c) 2012 DENX Software Engineering, GmbH.
6 * Copyright (c) 2017 Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
7 *
8 * Authors:
9 * Marek Vasut <marex@denx.de>
10 * Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
11 */
12
13 #include <linux/completion.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/mfd/core.h>
18 #include <linux/mfd/mxs-lradc.h>
19 #include <linux/module.h>
20 #include <linux/of_irq.h>
21 #include <linux/platform_device.h>
22 #include <linux/sysfs.h>
23
24 #include <linux/iio/buffer.h>
25 #include <linux/iio/iio.h>
26 #include <linux/iio/trigger.h>
27 #include <linux/iio/trigger_consumer.h>
28 #include <linux/iio/triggered_buffer.h>
29 #include <linux/iio/sysfs.h>
30
31 /*
32 * Make this runtime configurable if necessary. Currently, if the buffered mode
33 * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
34 * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
35 * seconds. The result is that the samples arrive every 500mS.
36 */
37 #define LRADC_DELAY_TIMER_PER 200
38 #define LRADC_DELAY_TIMER_LOOP 5
39
40 #define VREF_MV_BASE 1850
41
42 static const char *mx23_lradc_adc_irq_names[] = {
43 "mxs-lradc-channel0",
44 "mxs-lradc-channel1",
45 "mxs-lradc-channel2",
46 "mxs-lradc-channel3",
47 "mxs-lradc-channel4",
48 "mxs-lradc-channel5",
49 };
50
51 static const char *mx28_lradc_adc_irq_names[] = {
52 "mxs-lradc-thresh0",
53 "mxs-lradc-thresh1",
54 "mxs-lradc-channel0",
55 "mxs-lradc-channel1",
56 "mxs-lradc-channel2",
57 "mxs-lradc-channel3",
58 "mxs-lradc-channel4",
59 "mxs-lradc-channel5",
60 "mxs-lradc-button0",
61 "mxs-lradc-button1",
62 };
63
64 static const u32 mxs_lradc_adc_vref_mv[][LRADC_MAX_TOTAL_CHANS] = {
65 [IMX23_LRADC] = {
66 VREF_MV_BASE, /* CH0 */
67 VREF_MV_BASE, /* CH1 */
68 VREF_MV_BASE, /* CH2 */
69 VREF_MV_BASE, /* CH3 */
70 VREF_MV_BASE, /* CH4 */
71 VREF_MV_BASE, /* CH5 */
72 VREF_MV_BASE * 2, /* CH6 VDDIO */
73 VREF_MV_BASE * 4, /* CH7 VBATT */
74 VREF_MV_BASE, /* CH8 Temp sense 0 */
75 VREF_MV_BASE, /* CH9 Temp sense 1 */
76 VREF_MV_BASE, /* CH10 */
77 VREF_MV_BASE, /* CH11 */
78 VREF_MV_BASE, /* CH12 USB_DP */
79 VREF_MV_BASE, /* CH13 USB_DN */
80 VREF_MV_BASE, /* CH14 VBG */
81 VREF_MV_BASE * 4, /* CH15 VDD5V */
82 },
83 [IMX28_LRADC] = {
84 VREF_MV_BASE, /* CH0 */
85 VREF_MV_BASE, /* CH1 */
86 VREF_MV_BASE, /* CH2 */
87 VREF_MV_BASE, /* CH3 */
88 VREF_MV_BASE, /* CH4 */
89 VREF_MV_BASE, /* CH5 */
90 VREF_MV_BASE, /* CH6 */
91 VREF_MV_BASE * 4, /* CH7 VBATT */
92 VREF_MV_BASE, /* CH8 Temp sense 0 */
93 VREF_MV_BASE, /* CH9 Temp sense 1 */
94 VREF_MV_BASE * 2, /* CH10 VDDIO */
95 VREF_MV_BASE, /* CH11 VTH */
96 VREF_MV_BASE * 2, /* CH12 VDDA */
97 VREF_MV_BASE, /* CH13 VDDD */
98 VREF_MV_BASE, /* CH14 VBG */
99 VREF_MV_BASE * 4, /* CH15 VDD5V */
100 },
101 };
102
103 enum mxs_lradc_divbytwo {
104 MXS_LRADC_DIV_DISABLED = 0,
105 MXS_LRADC_DIV_ENABLED,
106 };
107
108 struct mxs_lradc_scale {
109 unsigned int integer;
110 unsigned int nano;
111 };
112
113 struct mxs_lradc_adc {
114 struct mxs_lradc *lradc;
115 struct device *dev;
116
117 void __iomem *base;
118 /* Maximum of 8 channels + 8 byte ts */
119 u32 buffer[10] __aligned(8);
120 struct iio_trigger *trig;
121 struct completion completion;
122 spinlock_t lock;
123
124 const u32 *vref_mv;
125 struct mxs_lradc_scale scale_avail[LRADC_MAX_TOTAL_CHANS][2];
126 unsigned long is_divided;
127 };
128
129
130 /* Raw I/O operations */
mxs_lradc_adc_read_single(struct iio_dev * iio_dev,int chan,int * val)131 static int mxs_lradc_adc_read_single(struct iio_dev *iio_dev, int chan,
132 int *val)
133 {
134 struct mxs_lradc_adc *adc = iio_priv(iio_dev);
135 struct mxs_lradc *lradc = adc->lradc;
136 int ret;
137
138 /*
139 * See if there is no buffered operation in progress. If there is simply
140 * bail out. This can be improved to support both buffered and raw IO at
141 * the same time, yet the code becomes horribly complicated. Therefore I
142 * applied KISS principle here.
143 */
144 ret = iio_device_claim_direct_mode(iio_dev);
145 if (ret)
146 return ret;
147
148 reinit_completion(&adc->completion);
149
150 /*
151 * No buffered operation in progress, map the channel and trigger it.
152 * Virtual channel 0 is always used here as the others are always not
153 * used if doing raw sampling.
154 */
155 if (lradc->soc == IMX28_LRADC)
156 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
157 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
158 writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
159
160 /* Enable / disable the divider per requirement */
161 if (test_bit(chan, &adc->is_divided))
162 writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
163 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET);
164 else
165 writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
166 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR);
167
168 /* Clean the slot's previous content, then set new one. */
169 writel(LRADC_CTRL4_LRADCSELECT_MASK(0),
170 adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
171 writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
172
173 writel(0, adc->base + LRADC_CH(0));
174
175 /* Enable the IRQ and start sampling the channel. */
176 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
177 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
178 writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
179
180 /* Wait for completion on the channel, 1 second max. */
181 ret = wait_for_completion_killable_timeout(&adc->completion, HZ);
182 if (!ret)
183 ret = -ETIMEDOUT;
184 if (ret < 0)
185 goto err;
186
187 /* Read the data. */
188 *val = readl(adc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
189 ret = IIO_VAL_INT;
190
191 err:
192 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
193 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
194
195 iio_device_release_direct_mode(iio_dev);
196
197 return ret;
198 }
199
mxs_lradc_adc_read_temp(struct iio_dev * iio_dev,int * val)200 static int mxs_lradc_adc_read_temp(struct iio_dev *iio_dev, int *val)
201 {
202 int ret, min, max;
203
204 ret = mxs_lradc_adc_read_single(iio_dev, 8, &min);
205 if (ret != IIO_VAL_INT)
206 return ret;
207
208 ret = mxs_lradc_adc_read_single(iio_dev, 9, &max);
209 if (ret != IIO_VAL_INT)
210 return ret;
211
212 *val = max - min;
213
214 return IIO_VAL_INT;
215 }
216
mxs_lradc_adc_read_raw(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long m)217 static int mxs_lradc_adc_read_raw(struct iio_dev *iio_dev,
218 const struct iio_chan_spec *chan,
219 int *val, int *val2, long m)
220 {
221 struct mxs_lradc_adc *adc = iio_priv(iio_dev);
222
223 switch (m) {
224 case IIO_CHAN_INFO_RAW:
225 if (chan->type == IIO_TEMP)
226 return mxs_lradc_adc_read_temp(iio_dev, val);
227
228 return mxs_lradc_adc_read_single(iio_dev, chan->channel, val);
229
230 case IIO_CHAN_INFO_SCALE:
231 if (chan->type == IIO_TEMP) {
232 /*
233 * From the datasheet, we have to multiply by 1.012 and
234 * divide by 4
235 */
236 *val = 0;
237 *val2 = 253000;
238 return IIO_VAL_INT_PLUS_MICRO;
239 }
240
241 *val = adc->vref_mv[chan->channel];
242 *val2 = chan->scan_type.realbits -
243 test_bit(chan->channel, &adc->is_divided);
244 return IIO_VAL_FRACTIONAL_LOG2;
245
246 case IIO_CHAN_INFO_OFFSET:
247 if (chan->type == IIO_TEMP) {
248 /*
249 * The calculated value from the ADC is in Kelvin, we
250 * want Celsius for hwmon so the offset is -273.15
251 * The offset is applied before scaling so it is
252 * actually -213.15 * 4 / 1.012 = -1079.644268
253 */
254 *val = -1079;
255 *val2 = 644268;
256
257 return IIO_VAL_INT_PLUS_MICRO;
258 }
259
260 return -EINVAL;
261
262 default:
263 break;
264 }
265
266 return -EINVAL;
267 }
268
mxs_lradc_adc_write_raw(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,int val,int val2,long m)269 static int mxs_lradc_adc_write_raw(struct iio_dev *iio_dev,
270 const struct iio_chan_spec *chan,
271 int val, int val2, long m)
272 {
273 struct mxs_lradc_adc *adc = iio_priv(iio_dev);
274 struct mxs_lradc_scale *scale_avail =
275 adc->scale_avail[chan->channel];
276 int ret;
277
278 ret = iio_device_claim_direct_mode(iio_dev);
279 if (ret)
280 return ret;
281
282 switch (m) {
283 case IIO_CHAN_INFO_SCALE:
284 ret = -EINVAL;
285 if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
286 val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
287 /* divider by two disabled */
288 clear_bit(chan->channel, &adc->is_divided);
289 ret = 0;
290 } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
291 val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
292 /* divider by two enabled */
293 set_bit(chan->channel, &adc->is_divided);
294 ret = 0;
295 }
296
297 break;
298 default:
299 ret = -EINVAL;
300 break;
301 }
302
303 iio_device_release_direct_mode(iio_dev);
304
305 return ret;
306 }
307
mxs_lradc_adc_write_raw_get_fmt(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,long m)308 static int mxs_lradc_adc_write_raw_get_fmt(struct iio_dev *iio_dev,
309 const struct iio_chan_spec *chan,
310 long m)
311 {
312 return IIO_VAL_INT_PLUS_NANO;
313 }
314
mxs_lradc_adc_show_scale_avail(struct device * dev,struct device_attribute * attr,char * buf)315 static ssize_t mxs_lradc_adc_show_scale_avail(struct device *dev,
316 struct device_attribute *attr,
317 char *buf)
318 {
319 struct iio_dev *iio = dev_to_iio_dev(dev);
320 struct mxs_lradc_adc *adc = iio_priv(iio);
321 struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
322 int i, ch, len = 0;
323
324 ch = iio_attr->address;
325 for (i = 0; i < ARRAY_SIZE(adc->scale_avail[ch]); i++)
326 len += sprintf(buf + len, "%u.%09u ",
327 adc->scale_avail[ch][i].integer,
328 adc->scale_avail[ch][i].nano);
329
330 len += sprintf(buf + len, "\n");
331
332 return len;
333 }
334
335 #define SHOW_SCALE_AVAILABLE_ATTR(ch)\
336 IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, 0444,\
337 mxs_lradc_adc_show_scale_avail, NULL, ch)
338
339 static SHOW_SCALE_AVAILABLE_ATTR(0);
340 static SHOW_SCALE_AVAILABLE_ATTR(1);
341 static SHOW_SCALE_AVAILABLE_ATTR(2);
342 static SHOW_SCALE_AVAILABLE_ATTR(3);
343 static SHOW_SCALE_AVAILABLE_ATTR(4);
344 static SHOW_SCALE_AVAILABLE_ATTR(5);
345 static SHOW_SCALE_AVAILABLE_ATTR(6);
346 static SHOW_SCALE_AVAILABLE_ATTR(7);
347 static SHOW_SCALE_AVAILABLE_ATTR(10);
348 static SHOW_SCALE_AVAILABLE_ATTR(11);
349 static SHOW_SCALE_AVAILABLE_ATTR(12);
350 static SHOW_SCALE_AVAILABLE_ATTR(13);
351 static SHOW_SCALE_AVAILABLE_ATTR(14);
352 static SHOW_SCALE_AVAILABLE_ATTR(15);
353
354 static struct attribute *mxs_lradc_adc_attributes[] = {
355 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
356 &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
357 &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
358 &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
359 &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
360 &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
361 &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
362 &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
363 &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
364 &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
365 &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
366 &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
367 &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
368 &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
369 NULL
370 };
371
372 static const struct attribute_group mxs_lradc_adc_attribute_group = {
373 .attrs = mxs_lradc_adc_attributes,
374 };
375
376 static const struct iio_info mxs_lradc_adc_iio_info = {
377 .read_raw = mxs_lradc_adc_read_raw,
378 .write_raw = mxs_lradc_adc_write_raw,
379 .write_raw_get_fmt = mxs_lradc_adc_write_raw_get_fmt,
380 .attrs = &mxs_lradc_adc_attribute_group,
381 };
382
383 /* IRQ Handling */
mxs_lradc_adc_handle_irq(int irq,void * data)384 static irqreturn_t mxs_lradc_adc_handle_irq(int irq, void *data)
385 {
386 struct iio_dev *iio = data;
387 struct mxs_lradc_adc *adc = iio_priv(iio);
388 struct mxs_lradc *lradc = adc->lradc;
389 unsigned long reg = readl(adc->base + LRADC_CTRL1);
390 unsigned long flags;
391
392 if (!(reg & mxs_lradc_irq_mask(lradc)))
393 return IRQ_NONE;
394
395 if (iio_buffer_enabled(iio)) {
396 if (reg & lradc->buffer_vchans) {
397 spin_lock_irqsave(&adc->lock, flags);
398 iio_trigger_poll(iio->trig);
399 spin_unlock_irqrestore(&adc->lock, flags);
400 }
401 } else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) {
402 complete(&adc->completion);
403 }
404
405 writel(reg & mxs_lradc_irq_mask(lradc),
406 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
407
408 return IRQ_HANDLED;
409 }
410
411
412 /* Trigger handling */
mxs_lradc_adc_trigger_handler(int irq,void * p)413 static irqreturn_t mxs_lradc_adc_trigger_handler(int irq, void *p)
414 {
415 struct iio_poll_func *pf = p;
416 struct iio_dev *iio = pf->indio_dev;
417 struct mxs_lradc_adc *adc = iio_priv(iio);
418 const u32 chan_value = LRADC_CH_ACCUMULATE |
419 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
420 unsigned int i, j = 0;
421
422 for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
423 adc->buffer[j] = readl(adc->base + LRADC_CH(j));
424 writel(chan_value, adc->base + LRADC_CH(j));
425 adc->buffer[j] &= LRADC_CH_VALUE_MASK;
426 adc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
427 j++;
428 }
429
430 iio_push_to_buffers_with_timestamp(iio, adc->buffer, pf->timestamp);
431
432 iio_trigger_notify_done(iio->trig);
433
434 return IRQ_HANDLED;
435 }
436
mxs_lradc_adc_configure_trigger(struct iio_trigger * trig,bool state)437 static int mxs_lradc_adc_configure_trigger(struct iio_trigger *trig, bool state)
438 {
439 struct iio_dev *iio = iio_trigger_get_drvdata(trig);
440 struct mxs_lradc_adc *adc = iio_priv(iio);
441 const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
442
443 writel(LRADC_DELAY_KICK, adc->base + (LRADC_DELAY(0) + st));
444
445 return 0;
446 }
447
448 static const struct iio_trigger_ops mxs_lradc_adc_trigger_ops = {
449 .set_trigger_state = &mxs_lradc_adc_configure_trigger,
450 };
451
mxs_lradc_adc_trigger_init(struct iio_dev * iio)452 static int mxs_lradc_adc_trigger_init(struct iio_dev *iio)
453 {
454 int ret;
455 struct iio_trigger *trig;
456 struct mxs_lradc_adc *adc = iio_priv(iio);
457
458 trig = devm_iio_trigger_alloc(&iio->dev, "%s-dev%i", iio->name,
459 iio_device_id(iio));
460 if (!trig)
461 return -ENOMEM;
462
463 trig->dev.parent = adc->dev;
464 iio_trigger_set_drvdata(trig, iio);
465 trig->ops = &mxs_lradc_adc_trigger_ops;
466
467 ret = iio_trigger_register(trig);
468 if (ret)
469 return ret;
470
471 adc->trig = trig;
472
473 return 0;
474 }
475
mxs_lradc_adc_trigger_remove(struct iio_dev * iio)476 static void mxs_lradc_adc_trigger_remove(struct iio_dev *iio)
477 {
478 struct mxs_lradc_adc *adc = iio_priv(iio);
479
480 iio_trigger_unregister(adc->trig);
481 }
482
mxs_lradc_adc_buffer_preenable(struct iio_dev * iio)483 static int mxs_lradc_adc_buffer_preenable(struct iio_dev *iio)
484 {
485 struct mxs_lradc_adc *adc = iio_priv(iio);
486 struct mxs_lradc *lradc = adc->lradc;
487 int chan, ofs = 0;
488 unsigned long enable = 0;
489 u32 ctrl4_set = 0;
490 u32 ctrl4_clr = 0;
491 u32 ctrl1_irq = 0;
492 const u32 chan_value = LRADC_CH_ACCUMULATE |
493 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
494
495 if (lradc->soc == IMX28_LRADC)
496 writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
497 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
498 writel(lradc->buffer_vchans,
499 adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
500
501 for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
502 ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
503 ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
504 ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
505 writel(chan_value, adc->base + LRADC_CH(ofs));
506 bitmap_set(&enable, ofs, 1);
507 ofs++;
508 }
509
510 writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
511 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
512 writel(ctrl4_clr, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
513 writel(ctrl4_set, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
514 writel(ctrl1_irq, adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
515 writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
516 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET);
517
518 return 0;
519 }
520
mxs_lradc_adc_buffer_postdisable(struct iio_dev * iio)521 static int mxs_lradc_adc_buffer_postdisable(struct iio_dev *iio)
522 {
523 struct mxs_lradc_adc *adc = iio_priv(iio);
524 struct mxs_lradc *lradc = adc->lradc;
525
526 writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
527 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
528
529 writel(lradc->buffer_vchans,
530 adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
531 if (lradc->soc == IMX28_LRADC)
532 writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
533 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
534
535 return 0;
536 }
537
mxs_lradc_adc_validate_scan_mask(struct iio_dev * iio,const unsigned long * mask)538 static bool mxs_lradc_adc_validate_scan_mask(struct iio_dev *iio,
539 const unsigned long *mask)
540 {
541 struct mxs_lradc_adc *adc = iio_priv(iio);
542 struct mxs_lradc *lradc = adc->lradc;
543 const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
544 int rsvd_chans = 0;
545 unsigned long rsvd_mask = 0;
546
547 if (lradc->use_touchbutton)
548 rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
549 if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_4WIRE)
550 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
551 if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_5WIRE)
552 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
553
554 if (lradc->use_touchbutton)
555 rsvd_chans++;
556 if (lradc->touchscreen_wire)
557 rsvd_chans += 2;
558
559 /* Test for attempts to map channels with special mode of operation. */
560 if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
561 return false;
562
563 /* Test for attempts to map more channels then available slots. */
564 if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
565 return false;
566
567 return true;
568 }
569
570 static const struct iio_buffer_setup_ops mxs_lradc_adc_buffer_ops = {
571 .preenable = &mxs_lradc_adc_buffer_preenable,
572 .postdisable = &mxs_lradc_adc_buffer_postdisable,
573 .validate_scan_mask = &mxs_lradc_adc_validate_scan_mask,
574 };
575
576 /* Driver initialization */
577 #define MXS_ADC_CHAN(idx, chan_type, name) { \
578 .type = (chan_type), \
579 .indexed = 1, \
580 .scan_index = (idx), \
581 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
582 BIT(IIO_CHAN_INFO_SCALE), \
583 .channel = (idx), \
584 .address = (idx), \
585 .scan_type = { \
586 .sign = 'u', \
587 .realbits = LRADC_RESOLUTION, \
588 .storagebits = 32, \
589 }, \
590 .datasheet_name = (name), \
591 }
592
593 static const struct iio_chan_spec mx23_lradc_chan_spec[] = {
594 MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
595 MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
596 MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
597 MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
598 MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
599 MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
600 MXS_ADC_CHAN(6, IIO_VOLTAGE, "VDDIO"),
601 MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
602 /* Combined Temperature sensors */
603 {
604 .type = IIO_TEMP,
605 .indexed = 1,
606 .scan_index = 8,
607 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
608 BIT(IIO_CHAN_INFO_OFFSET) |
609 BIT(IIO_CHAN_INFO_SCALE),
610 .channel = 8,
611 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
612 .datasheet_name = "TEMP_DIE",
613 },
614 /* Hidden channel to keep indexes */
615 {
616 .type = IIO_TEMP,
617 .indexed = 1,
618 .scan_index = -1,
619 .channel = 9,
620 },
621 MXS_ADC_CHAN(10, IIO_VOLTAGE, NULL),
622 MXS_ADC_CHAN(11, IIO_VOLTAGE, NULL),
623 MXS_ADC_CHAN(12, IIO_VOLTAGE, "USB_DP"),
624 MXS_ADC_CHAN(13, IIO_VOLTAGE, "USB_DN"),
625 MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
626 MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
627 };
628
629 static const struct iio_chan_spec mx28_lradc_chan_spec[] = {
630 MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
631 MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
632 MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
633 MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
634 MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
635 MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
636 MXS_ADC_CHAN(6, IIO_VOLTAGE, "LRADC6"),
637 MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
638 /* Combined Temperature sensors */
639 {
640 .type = IIO_TEMP,
641 .indexed = 1,
642 .scan_index = 8,
643 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
644 BIT(IIO_CHAN_INFO_OFFSET) |
645 BIT(IIO_CHAN_INFO_SCALE),
646 .channel = 8,
647 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
648 .datasheet_name = "TEMP_DIE",
649 },
650 /* Hidden channel to keep indexes */
651 {
652 .type = IIO_TEMP,
653 .indexed = 1,
654 .scan_index = -1,
655 .channel = 9,
656 },
657 MXS_ADC_CHAN(10, IIO_VOLTAGE, "VDDIO"),
658 MXS_ADC_CHAN(11, IIO_VOLTAGE, "VTH"),
659 MXS_ADC_CHAN(12, IIO_VOLTAGE, "VDDA"),
660 MXS_ADC_CHAN(13, IIO_VOLTAGE, "VDDD"),
661 MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
662 MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
663 };
664
mxs_lradc_adc_hw_init(struct mxs_lradc_adc * adc)665 static void mxs_lradc_adc_hw_init(struct mxs_lradc_adc *adc)
666 {
667 /* The ADC always uses DELAY CHANNEL 0. */
668 const u32 adc_cfg =
669 (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
670 (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
671
672 /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
673 writel(adc_cfg, adc->base + LRADC_DELAY(0));
674
675 /*
676 * Start internal temperature sensing by clearing bit
677 * HW_LRADC_CTRL2_TEMPSENSE_PWD. This bit can be left cleared
678 * after power up.
679 */
680 writel(0, adc->base + LRADC_CTRL2);
681 }
682
mxs_lradc_adc_hw_stop(struct mxs_lradc_adc * adc)683 static void mxs_lradc_adc_hw_stop(struct mxs_lradc_adc *adc)
684 {
685 writel(0, adc->base + LRADC_DELAY(0));
686 }
687
mxs_lradc_adc_probe(struct platform_device * pdev)688 static int mxs_lradc_adc_probe(struct platform_device *pdev)
689 {
690 struct device *dev = &pdev->dev;
691 struct mxs_lradc *lradc = dev_get_drvdata(dev->parent);
692 struct mxs_lradc_adc *adc;
693 struct iio_dev *iio;
694 struct resource *iores;
695 int ret, irq, virq, i, s, n;
696 u64 scale_uv;
697 const char **irq_name;
698
699 /* Allocate the IIO device. */
700 iio = devm_iio_device_alloc(dev, sizeof(*adc));
701 if (!iio) {
702 dev_err(dev, "Failed to allocate IIO device\n");
703 return -ENOMEM;
704 }
705
706 adc = iio_priv(iio);
707 adc->lradc = lradc;
708 adc->dev = dev;
709
710 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
711 if (!iores)
712 return -EINVAL;
713
714 adc->base = devm_ioremap(dev, iores->start, resource_size(iores));
715 if (!adc->base)
716 return -ENOMEM;
717
718 init_completion(&adc->completion);
719 spin_lock_init(&adc->lock);
720
721 platform_set_drvdata(pdev, iio);
722
723 iio->name = pdev->name;
724 iio->dev.of_node = dev->parent->of_node;
725 iio->info = &mxs_lradc_adc_iio_info;
726 iio->modes = INDIO_DIRECT_MODE;
727 iio->masklength = LRADC_MAX_TOTAL_CHANS;
728
729 if (lradc->soc == IMX23_LRADC) {
730 iio->channels = mx23_lradc_chan_spec;
731 iio->num_channels = ARRAY_SIZE(mx23_lradc_chan_spec);
732 irq_name = mx23_lradc_adc_irq_names;
733 n = ARRAY_SIZE(mx23_lradc_adc_irq_names);
734 } else {
735 iio->channels = mx28_lradc_chan_spec;
736 iio->num_channels = ARRAY_SIZE(mx28_lradc_chan_spec);
737 irq_name = mx28_lradc_adc_irq_names;
738 n = ARRAY_SIZE(mx28_lradc_adc_irq_names);
739 }
740
741 ret = stmp_reset_block(adc->base);
742 if (ret)
743 return ret;
744
745 for (i = 0; i < n; i++) {
746 irq = platform_get_irq_byname(pdev, irq_name[i]);
747 if (irq < 0)
748 return irq;
749
750 virq = irq_of_parse_and_map(dev->parent->of_node, irq);
751
752 ret = devm_request_irq(dev, virq, mxs_lradc_adc_handle_irq,
753 0, irq_name[i], iio);
754 if (ret)
755 return ret;
756 }
757
758 ret = mxs_lradc_adc_trigger_init(iio);
759 if (ret)
760 goto err_trig;
761
762 ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
763 &mxs_lradc_adc_trigger_handler,
764 &mxs_lradc_adc_buffer_ops);
765 if (ret)
766 return ret;
767
768 adc->vref_mv = mxs_lradc_adc_vref_mv[lradc->soc];
769
770 /* Populate available ADC input ranges */
771 for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
772 for (s = 0; s < ARRAY_SIZE(adc->scale_avail[i]); s++) {
773 /*
774 * [s=0] = optional divider by two disabled (default)
775 * [s=1] = optional divider by two enabled
776 *
777 * The scale is calculated by doing:
778 * Vref >> (realbits - s)
779 * which multiplies by two on the second component
780 * of the array.
781 */
782 scale_uv = ((u64)adc->vref_mv[i] * 100000000) >>
783 (LRADC_RESOLUTION - s);
784 adc->scale_avail[i][s].nano =
785 do_div(scale_uv, 100000000) * 10;
786 adc->scale_avail[i][s].integer = scale_uv;
787 }
788 }
789
790 /* Configure the hardware. */
791 mxs_lradc_adc_hw_init(adc);
792
793 /* Register IIO device. */
794 ret = iio_device_register(iio);
795 if (ret) {
796 dev_err(dev, "Failed to register IIO device\n");
797 goto err_dev;
798 }
799
800 return 0;
801
802 err_dev:
803 mxs_lradc_adc_hw_stop(adc);
804 mxs_lradc_adc_trigger_remove(iio);
805 err_trig:
806 iio_triggered_buffer_cleanup(iio);
807 return ret;
808 }
809
mxs_lradc_adc_remove(struct platform_device * pdev)810 static int mxs_lradc_adc_remove(struct platform_device *pdev)
811 {
812 struct iio_dev *iio = platform_get_drvdata(pdev);
813 struct mxs_lradc_adc *adc = iio_priv(iio);
814
815 iio_device_unregister(iio);
816 mxs_lradc_adc_hw_stop(adc);
817 mxs_lradc_adc_trigger_remove(iio);
818 iio_triggered_buffer_cleanup(iio);
819
820 return 0;
821 }
822
823 static struct platform_driver mxs_lradc_adc_driver = {
824 .driver = {
825 .name = "mxs-lradc-adc",
826 },
827 .probe = mxs_lradc_adc_probe,
828 .remove = mxs_lradc_adc_remove,
829 };
830 module_platform_driver(mxs_lradc_adc_driver);
831
832 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
833 MODULE_DESCRIPTION("Freescale MXS LRADC driver general purpose ADC driver");
834 MODULE_LICENSE("GPL");
835 MODULE_ALIAS("platform:mxs-lradc-adc");
836