1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2022 Microchip Technology Inc.
3 // pci1xxxx gpio driver
4
5 #include <linux/module.h>
6 #include <linux/spinlock.h>
7 #include <linux/gpio/driver.h>
8 #include <linux/bio.h>
9 #include <linux/mutex.h>
10 #include <linux/kthread.h>
11 #include <linux/interrupt.h>
12
13 #include "mchp_pci1xxxx_gp.h"
14
15 #define PCI1XXXX_NR_PINS 93
16 #define PERI_GEN_RESET 0
17 #define OUT_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400)
18 #define INP_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x10)
19 #define OUT_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x20)
20 #define INP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x30)
21 #define PULLUP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x40)
22 #define PULLDOWN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x50)
23 #define OPENDRAIN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x60)
24 #define WAKEMASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x70)
25 #define MODE_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x80)
26 #define INTR_LO_TO_HI_EDGE_CONFIG(x) ((((x) / 32) * 4) + 0x400 + 0x90)
27 #define INTR_HI_TO_LO_EDGE_CONFIG(x) ((((x) / 32) * 4) + 0x400 + 0xA0)
28 #define INTR_LEVEL_CONFIG_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xB0)
29 #define INTR_LEVEL_MASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xC0)
30 #define INTR_STAT_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xD0)
31 #define DEBOUNCE_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xE0)
32 #define PIO_GLOBAL_CONFIG_OFFSET (0x400 + 0xF0)
33 #define PIO_PCI_CTRL_REG_OFFSET (0x400 + 0xF4)
34 #define INTR_MASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x100)
35 #define INTR_STATUS_OFFSET(x) (((x) * 4) + 0x400 + 0xD0)
36
37 struct pci1xxxx_gpio {
38 struct auxiliary_device *aux_dev;
39 void __iomem *reg_base;
40 struct gpio_chip gpio;
41 spinlock_t lock;
42 int irq_base;
43 };
44
pci1xxxx_gpio_get_direction(struct gpio_chip * gpio,unsigned int nr)45 static int pci1xxxx_gpio_get_direction(struct gpio_chip *gpio, unsigned int nr)
46 {
47 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
48 u32 data;
49 int ret = -EINVAL;
50
51 data = readl(priv->reg_base + INP_EN_OFFSET(nr));
52 if (data & BIT(nr % 32)) {
53 ret = 1;
54 } else {
55 data = readl(priv->reg_base + OUT_EN_OFFSET(nr));
56 if (data & BIT(nr % 32))
57 ret = 0;
58 }
59
60 return ret;
61 }
62
pci1xxx_assign_bit(void __iomem * base_addr,unsigned int reg_offset,unsigned int bitpos,bool set)63 static inline void pci1xxx_assign_bit(void __iomem *base_addr, unsigned int reg_offset,
64 unsigned int bitpos, bool set)
65 {
66 u32 data;
67
68 data = readl(base_addr + reg_offset);
69 if (set)
70 data |= BIT(bitpos);
71 else
72 data &= ~BIT(bitpos);
73 writel(data, base_addr + reg_offset);
74 }
75
pci1xxxx_gpio_direction_input(struct gpio_chip * gpio,unsigned int nr)76 static int pci1xxxx_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
77 {
78 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
79 unsigned long flags;
80
81 spin_lock_irqsave(&priv->lock, flags);
82 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), true);
83 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), false);
84 spin_unlock_irqrestore(&priv->lock, flags);
85
86 return 0;
87 }
88
pci1xxxx_gpio_get(struct gpio_chip * gpio,unsigned int nr)89 static int pci1xxxx_gpio_get(struct gpio_chip *gpio, unsigned int nr)
90 {
91 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
92
93 return (readl(priv->reg_base + INP_OFFSET(nr)) >> (nr % 32)) & 1;
94 }
95
pci1xxxx_gpio_direction_output(struct gpio_chip * gpio,unsigned int nr,int val)96 static int pci1xxxx_gpio_direction_output(struct gpio_chip *gpio,
97 unsigned int nr, int val)
98 {
99 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
100 unsigned long flags;
101 u32 data;
102
103 spin_lock_irqsave(&priv->lock, flags);
104 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), false);
105 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), true);
106 data = readl(priv->reg_base + OUT_OFFSET(nr));
107 if (val)
108 data |= (1 << (nr % 32));
109 else
110 data &= ~(1 << (nr % 32));
111 writel(data, priv->reg_base + OUT_OFFSET(nr));
112 spin_unlock_irqrestore(&priv->lock, flags);
113
114 return 0;
115 }
116
pci1xxxx_gpio_set(struct gpio_chip * gpio,unsigned int nr,int val)117 static void pci1xxxx_gpio_set(struct gpio_chip *gpio,
118 unsigned int nr, int val)
119 {
120 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
121 unsigned long flags;
122
123 spin_lock_irqsave(&priv->lock, flags);
124 pci1xxx_assign_bit(priv->reg_base, OUT_OFFSET(nr), (nr % 32), val);
125 spin_unlock_irqrestore(&priv->lock, flags);
126 }
127
pci1xxxx_gpio_set_config(struct gpio_chip * gpio,unsigned int offset,unsigned long config)128 static int pci1xxxx_gpio_set_config(struct gpio_chip *gpio, unsigned int offset,
129 unsigned long config)
130 {
131 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
132 unsigned long flags;
133 int ret = 0;
134
135 spin_lock_irqsave(&priv->lock, flags);
136 switch (pinconf_to_config_param(config)) {
137 case PIN_CONFIG_BIAS_PULL_UP:
138 pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), true);
139 break;
140 case PIN_CONFIG_BIAS_PULL_DOWN:
141 pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), true);
142 break;
143 case PIN_CONFIG_BIAS_DISABLE:
144 pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), false);
145 pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), false);
146 break;
147 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
148 pci1xxx_assign_bit(priv->reg_base, OPENDRAIN_OFFSET(offset), (offset % 32), true);
149 break;
150 default:
151 ret = -EOPNOTSUPP;
152 break;
153 }
154 spin_unlock_irqrestore(&priv->lock, flags);
155
156 return ret;
157 }
158
pci1xxxx_gpio_irq_ack(struct irq_data * data)159 static void pci1xxxx_gpio_irq_ack(struct irq_data *data)
160 {
161 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
162 struct pci1xxxx_gpio *priv = gpiochip_get_data(chip);
163 unsigned int gpio = irqd_to_hwirq(data);
164 unsigned long flags;
165
166 spin_lock_irqsave(&priv->lock, flags);
167 pci1xxx_assign_bit(priv->reg_base, INTR_STAT_OFFSET(gpio), (gpio % 32), true);
168 spin_unlock_irqrestore(&priv->lock, flags);
169 }
170
pci1xxxx_gpio_irq_set_mask(struct irq_data * data,bool set)171 static void pci1xxxx_gpio_irq_set_mask(struct irq_data *data, bool set)
172 {
173 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
174 struct pci1xxxx_gpio *priv = gpiochip_get_data(chip);
175 unsigned int gpio = irqd_to_hwirq(data);
176 unsigned long flags;
177
178 spin_lock_irqsave(&priv->lock, flags);
179 pci1xxx_assign_bit(priv->reg_base, INTR_MASK_OFFSET(gpio), (gpio % 32), set);
180 spin_unlock_irqrestore(&priv->lock, flags);
181 }
182
pci1xxxx_gpio_irq_mask(struct irq_data * data)183 static void pci1xxxx_gpio_irq_mask(struct irq_data *data)
184 {
185 pci1xxxx_gpio_irq_set_mask(data, true);
186 }
187
pci1xxxx_gpio_irq_unmask(struct irq_data * data)188 static void pci1xxxx_gpio_irq_unmask(struct irq_data *data)
189 {
190 pci1xxxx_gpio_irq_set_mask(data, false);
191 }
192
pci1xxxx_gpio_set_type(struct irq_data * data,unsigned int trigger_type)193 static int pci1xxxx_gpio_set_type(struct irq_data *data, unsigned int trigger_type)
194 {
195 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
196 struct pci1xxxx_gpio *priv = gpiochip_get_data(chip);
197 unsigned int gpio = irqd_to_hwirq(data);
198 unsigned int bitpos = gpio % 32;
199
200 if (trigger_type & IRQ_TYPE_EDGE_FALLING) {
201 pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio),
202 bitpos, false);
203 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio),
204 bitpos, false);
205 irq_set_handler_locked(data, handle_edge_irq);
206 } else {
207 pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio),
208 bitpos, true);
209 }
210
211 if (trigger_type & IRQ_TYPE_EDGE_RISING) {
212 pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio),
213 bitpos, false);
214 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,
215 false);
216 irq_set_handler_locked(data, handle_edge_irq);
217 } else {
218 pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio),
219 bitpos, true);
220 }
221
222 if (trigger_type & IRQ_TYPE_LEVEL_LOW) {
223 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio),
224 bitpos, true);
225 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio),
226 bitpos, false);
227 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,
228 true);
229 irq_set_handler_locked(data, handle_edge_irq);
230 }
231
232 if (trigger_type & IRQ_TYPE_LEVEL_HIGH) {
233 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio),
234 bitpos, false);
235 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio),
236 bitpos, false);
237 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,
238 true);
239 irq_set_handler_locked(data, handle_edge_irq);
240 }
241
242 if ((!(trigger_type & IRQ_TYPE_LEVEL_LOW)) && (!(trigger_type & IRQ_TYPE_LEVEL_HIGH)))
243 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), bitpos, true);
244
245 return true;
246 }
247
pci1xxxx_gpio_irq_handler(int irq,void * dev_id)248 static irqreturn_t pci1xxxx_gpio_irq_handler(int irq, void *dev_id)
249 {
250 struct pci1xxxx_gpio *priv = dev_id;
251 struct gpio_chip *gc = &priv->gpio;
252 unsigned long int_status = 0;
253 unsigned long flags;
254 u8 pincount;
255 int bit;
256 u8 gpiobank;
257
258 spin_lock_irqsave(&priv->lock, flags);
259 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, true);
260 spin_unlock_irqrestore(&priv->lock, flags);
261 for (gpiobank = 0; gpiobank < 3; gpiobank++) {
262 spin_lock_irqsave(&priv->lock, flags);
263 int_status = readl(priv->reg_base + INTR_STATUS_OFFSET(gpiobank));
264 spin_unlock_irqrestore(&priv->lock, flags);
265 if (gpiobank == 2)
266 pincount = 29;
267 else
268 pincount = 32;
269 for_each_set_bit(bit, &int_status, pincount) {
270 unsigned int irq;
271
272 spin_lock_irqsave(&priv->lock, flags);
273 writel(BIT(bit), priv->reg_base + INTR_STATUS_OFFSET(gpiobank));
274 spin_unlock_irqrestore(&priv->lock, flags);
275 irq = irq_find_mapping(gc->irq.domain, (bit + (gpiobank * 32)));
276 generic_handle_irq(irq);
277 }
278 }
279 spin_lock_irqsave(&priv->lock, flags);
280 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, false);
281 spin_unlock_irqrestore(&priv->lock, flags);
282
283 return IRQ_HANDLED;
284 }
285
286 static struct irq_chip pci1xxxx_gpio_irqchip = {
287 .name = "pci1xxxx_gpio",
288 .irq_ack = pci1xxxx_gpio_irq_ack,
289 .irq_mask = pci1xxxx_gpio_irq_mask,
290 .irq_unmask = pci1xxxx_gpio_irq_unmask,
291 .irq_set_type = pci1xxxx_gpio_set_type,
292 };
293
pci1xxxx_gpio_suspend(struct device * dev)294 static int pci1xxxx_gpio_suspend(struct device *dev)
295 {
296 struct pci1xxxx_gpio *priv = dev_get_drvdata(dev);
297 unsigned long flags;
298
299 spin_lock_irqsave(&priv->lock, flags);
300 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
301 16, true);
302 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
303 17, false);
304 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, true);
305 spin_unlock_irqrestore(&priv->lock, flags);
306
307 return 0;
308 }
309
pci1xxxx_gpio_resume(struct device * dev)310 static int pci1xxxx_gpio_resume(struct device *dev)
311 {
312 struct pci1xxxx_gpio *priv = dev_get_drvdata(dev);
313 unsigned long flags;
314
315 spin_lock_irqsave(&priv->lock, flags);
316 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
317 17, true);
318 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
319 16, false);
320 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, false);
321 spin_unlock_irqrestore(&priv->lock, flags);
322
323 return 0;
324 }
325
pci1xxxx_gpio_setup(struct pci1xxxx_gpio * priv,int irq)326 static int pci1xxxx_gpio_setup(struct pci1xxxx_gpio *priv, int irq)
327 {
328 struct gpio_chip *gchip = &priv->gpio;
329 struct gpio_irq_chip *girq;
330 int retval;
331
332 gchip->label = dev_name(&priv->aux_dev->dev);
333 gchip->parent = &priv->aux_dev->dev;
334 gchip->owner = THIS_MODULE;
335 gchip->direction_input = pci1xxxx_gpio_direction_input;
336 gchip->direction_output = pci1xxxx_gpio_direction_output;
337 gchip->get_direction = pci1xxxx_gpio_get_direction;
338 gchip->get = pci1xxxx_gpio_get;
339 gchip->set = pci1xxxx_gpio_set;
340 gchip->set_config = pci1xxxx_gpio_set_config;
341 gchip->dbg_show = NULL;
342 gchip->base = -1;
343 gchip->ngpio = PCI1XXXX_NR_PINS;
344 gchip->can_sleep = false;
345
346 retval = devm_request_threaded_irq(&priv->aux_dev->dev, irq,
347 NULL, pci1xxxx_gpio_irq_handler,
348 IRQF_ONESHOT, "PCI1xxxxGPIO", priv);
349
350 if (retval)
351 return retval;
352
353 girq = &priv->gpio.irq;
354 girq->chip = &pci1xxxx_gpio_irqchip;
355 girq->parent_handler = NULL;
356 girq->num_parents = 0;
357 girq->parents = NULL;
358 girq->default_type = IRQ_TYPE_NONE;
359 girq->handler = handle_bad_irq;
360
361 return 0;
362 }
363
pci1xxxx_gpio_probe(struct auxiliary_device * aux_dev,const struct auxiliary_device_id * id)364 static int pci1xxxx_gpio_probe(struct auxiliary_device *aux_dev,
365 const struct auxiliary_device_id *id)
366
367 {
368 struct auxiliary_device_wrapper *aux_dev_wrapper;
369 struct gp_aux_data_type *pdata;
370 struct pci1xxxx_gpio *priv;
371 int retval;
372
373 aux_dev_wrapper = (struct auxiliary_device_wrapper *)
374 container_of(aux_dev, struct auxiliary_device_wrapper, aux_dev);
375
376 pdata = &aux_dev_wrapper->gp_aux_data;
377
378 if (!pdata)
379 return -EINVAL;
380
381 priv = devm_kzalloc(&aux_dev->dev, sizeof(struct pci1xxxx_gpio), GFP_KERNEL);
382 if (!priv)
383 return -ENOMEM;
384
385 spin_lock_init(&priv->lock);
386 priv->aux_dev = aux_dev;
387
388 if (!devm_request_mem_region(&aux_dev->dev, pdata->region_start, 0x800, aux_dev->name))
389 return -EBUSY;
390
391 priv->reg_base = devm_ioremap(&aux_dev->dev, pdata->region_start, 0x800);
392 if (!priv->reg_base)
393 return -ENOMEM;
394
395 writel(0x0264, (priv->reg_base + 0x400 + 0xF0));
396
397 retval = pci1xxxx_gpio_setup(priv, pdata->irq_num);
398
399 if (retval < 0)
400 return retval;
401
402 dev_set_drvdata(&aux_dev->dev, priv);
403
404 return devm_gpiochip_add_data(&aux_dev->dev, &priv->gpio, priv);
405 }
406
407 static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_gpio_pm_ops, pci1xxxx_gpio_suspend, pci1xxxx_gpio_resume);
408
409 static const struct auxiliary_device_id pci1xxxx_gpio_auxiliary_id_table[] = {
410 {.name = "mchp_pci1xxxx_gp.gp_gpio"},
411 {}
412 };
413 MODULE_DEVICE_TABLE(auxiliary, pci1xxxx_gpio_auxiliary_id_table);
414
415 static struct auxiliary_driver pci1xxxx_gpio_driver = {
416 .driver = {
417 .name = "PCI1xxxxGPIO",
418 .pm = &pci1xxxx_gpio_pm_ops,
419 },
420 .probe = pci1xxxx_gpio_probe,
421 .id_table = pci1xxxx_gpio_auxiliary_id_table
422 };
423 module_auxiliary_driver(pci1xxxx_gpio_driver);
424
425 MODULE_DESCRIPTION("Microchip Technology Inc. PCI1xxxx GPIO controller");
426 MODULE_AUTHOR("Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>");
427 MODULE_LICENSE("GPL");
428