1 /* Generic NS8390 register definitions. */
2 
3 /* This file is part of Donald Becker's 8390 drivers, and is distributed
4  * under the same license. Auto-loading of 8390.o only in v2.2 - Paul G.
5  * Some of these names and comments originated from the Crynwr
6  * packet drivers, which are distributed under the GPL.
7  */
8 
9 #ifndef _8390_h
10 #define _8390_h
11 
12 #include <linux/if_ether.h>
13 #include <linux/ioport.h>
14 #include <linux/irqreturn.h>
15 #include <linux/skbuff.h>
16 
17 #define TX_PAGES 12	/* Two Tx slots */
18 
19 /* The 8390 specific per-packet-header format. */
20 struct e8390_pkt_hdr {
21 	unsigned char status; /* status */
22 	unsigned char next;   /* pointer to next packet. */
23 	unsigned short count; /* header + packet length in bytes */
24 };
25 
26 #ifdef CONFIG_NET_POLL_CONTROLLER
27 void ei_poll(struct net_device *dev);
28 void eip_poll(struct net_device *dev);
29 #endif
30 
31 
32 /* Without I/O delay - non ISA or later chips */
33 void NS8390_init(struct net_device *dev, int startp);
34 int ei_open(struct net_device *dev);
35 int ei_close(struct net_device *dev);
36 irqreturn_t ei_interrupt(int irq, void *dev_id);
37 void ei_tx_timeout(struct net_device *dev, unsigned int txqueue);
38 netdev_tx_t ei_start_xmit(struct sk_buff *skb, struct net_device *dev);
39 void ei_set_multicast_list(struct net_device *dev);
40 struct net_device_stats *ei_get_stats(struct net_device *dev);
41 
42 extern const struct net_device_ops ei_netdev_ops;
43 
44 struct net_device *__alloc_ei_netdev(int size);
alloc_ei_netdev(void)45 static inline struct net_device *alloc_ei_netdev(void)
46 {
47 	return __alloc_ei_netdev(0);
48 }
49 
50 /* With I/O delay form */
51 void NS8390p_init(struct net_device *dev, int startp);
52 int eip_open(struct net_device *dev);
53 int eip_close(struct net_device *dev);
54 irqreturn_t eip_interrupt(int irq, void *dev_id);
55 void eip_tx_timeout(struct net_device *dev, unsigned int txqueue);
56 netdev_tx_t eip_start_xmit(struct sk_buff *skb, struct net_device *dev);
57 void eip_set_multicast_list(struct net_device *dev);
58 struct net_device_stats *eip_get_stats(struct net_device *dev);
59 
60 extern const struct net_device_ops eip_netdev_ops;
61 
62 struct net_device *__alloc_eip_netdev(int size);
alloc_eip_netdev(void)63 static inline struct net_device *alloc_eip_netdev(void)
64 {
65 	return __alloc_eip_netdev(0);
66 }
67 
68 /* You have one of these per-board */
69 struct ei_device {
70 	const char *name;
71 	void (*reset_8390)(struct net_device *dev);
72 	void (*get_8390_hdr)(struct net_device *dev,
73 			     struct e8390_pkt_hdr *hdr, int ring_page);
74 	void (*block_output)(struct net_device *dev, int count,
75 			     const unsigned char *buf, int start_page);
76 	void (*block_input)(struct net_device *dev, int count,
77 			    struct sk_buff *skb, int ring_offset);
78 	unsigned long rmem_start;
79 	unsigned long rmem_end;
80 	void __iomem *mem;
81 	unsigned char mcfilter[8];
82 	unsigned open:1;
83 	unsigned word16:1;		/* We have the 16-bit (vs 8-bit)
84 					 * version of the card.
85 					 */
86 	unsigned bigendian:1;		/* 16-bit big endian mode. Do NOT
87 					 * set this on random 8390 clones!
88 					 */
89 	unsigned txing:1;		/* Transmit Active */
90 	unsigned irqlock:1;		/* 8390's intrs disabled when '1'. */
91 	unsigned dmaing:1;		/* Remote DMA Active */
92 	unsigned char tx_start_page, rx_start_page, stop_page;
93 	unsigned char current_page;	/* Read pointer in buffer  */
94 	unsigned char interface_num;	/* Net port (AUI, 10bT.) to use. */
95 	unsigned char txqueue;		/* Tx Packet buffer queue length. */
96 	short tx1, tx2;			/* Packet lengths for ping-pong tx. */
97 	short lasttx;			/* Alpha version consistency check. */
98 	unsigned char reg0;		/* Register '0' in a WD8013 */
99 	unsigned char reg5;		/* Register '5' in a WD8013 */
100 	unsigned char saved_irq;	/* Original dev->irq value. */
101 	u32 *reg_offset;		/* Register mapping table */
102 	spinlock_t page_lock;		/* Page register locks */
103 	unsigned long priv;		/* Private field to store bus IDs etc. */
104 	u32 msg_enable;			/* debug message level */
105 #ifdef AX88796_PLATFORM
106 	unsigned char rxcr_base;	/* default value for RXCR */
107 #endif
108 };
109 
110 /* The maximum number of 8390 interrupt service routines called per IRQ. */
111 #define MAX_SERVICE 12
112 
113 /* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */
114 #define TX_TIMEOUT (20*HZ/100)
115 
116 #define ei_status (*(struct ei_device *)netdev_priv(dev))
117 
118 /* Some generic ethernet register configurations. */
119 #define E8390_TX_IRQ_MASK	0xa	/* For register EN0_ISR */
120 #define E8390_RX_IRQ_MASK	0x5
121 
122 #ifdef AX88796_PLATFORM
123 #define E8390_RXCONFIG		(ei_status.rxcr_base | 0x04)
124 #define E8390_RXOFF		(ei_status.rxcr_base | 0x20)
125 #else
126 /* EN0_RXCR: broadcasts, no multicast,errors */
127 #define E8390_RXCONFIG		0x4
128 /* EN0_RXCR: Accept no packets */
129 #define E8390_RXOFF		0x20
130 #endif
131 
132 /* EN0_TXCR: Normal transmit mode */
133 #define E8390_TXCONFIG		0x00
134 /* EN0_TXCR: Transmitter off */
135 #define E8390_TXOFF		0x02
136 
137 
138 /*  Register accessed at EN_CMD, the 8390 base addr.  */
139 #define E8390_STOP	0x01	/* Stop and reset the chip */
140 #define E8390_START	0x02	/* Start the chip, clear reset */
141 #define E8390_TRANS	0x04	/* Transmit a frame */
142 #define E8390_RREAD	0x08	/* Remote read */
143 #define E8390_RWRITE	0x10	/* Remote write  */
144 #define E8390_NODMA	0x20	/* Remote DMA */
145 #define E8390_PAGE0	0x00	/* Select page chip registers */
146 #define E8390_PAGE1	0x40	/* using the two high-order bits */
147 #define E8390_PAGE2	0x80	/* Page 3 is invalid. */
148 
149 /* Only generate indirect loads given a machine that needs them.
150  * - removed AMIGA_PCMCIA from this list, handled as ISA io now
151  * - the _p for generates no delay by default 8390p.c overrides this.
152  */
153 
154 #ifndef ei_inb
155 #define ei_inb(_p)	inb(_p)
156 #define ei_outb(_v, _p)	outb(_v, _p)
157 #define ei_inb_p(_p)	inb(_p)
158 #define ei_outb_p(_v, _p) outb(_v, _p)
159 #endif
160 
161 #ifndef EI_SHIFT
162 #define EI_SHIFT(x)	(x)
163 #endif
164 
165 #define E8390_CMD	EI_SHIFT(0x00)  /* The command register (for all pages) */
166 /* Page 0 register offsets. */
167 #define EN0_CLDALO	EI_SHIFT(0x01)	/* Low byte of current local dma addr RD */
168 #define EN0_STARTPG	EI_SHIFT(0x01)	/* Starting page of ring bfr WR */
169 #define EN0_CLDAHI	EI_SHIFT(0x02)	/* High byte of current local dma addr RD */
170 #define EN0_STOPPG	EI_SHIFT(0x02)	/* Ending page +1 of ring bfr WR */
171 #define EN0_BOUNDARY	EI_SHIFT(0x03)	/* Boundary page of ring bfr RD WR */
172 #define EN0_TSR		EI_SHIFT(0x04)	/* Transmit status reg RD */
173 #define EN0_TPSR	EI_SHIFT(0x04)	/* Transmit starting page WR */
174 #define EN0_NCR		EI_SHIFT(0x05)	/* Number of collision reg RD */
175 #define EN0_TCNTLO	EI_SHIFT(0x05)	/* Low  byte of tx byte count WR */
176 #define EN0_FIFO	EI_SHIFT(0x06)	/* FIFO RD */
177 #define EN0_TCNTHI	EI_SHIFT(0x06)	/* High byte of tx byte count WR */
178 #define EN0_ISR		EI_SHIFT(0x07)	/* Interrupt status reg RD WR */
179 #define EN0_CRDALO	EI_SHIFT(0x08)	/* low byte of current remote dma address RD */
180 #define EN0_RSARLO	EI_SHIFT(0x08)	/* Remote start address reg 0 */
181 #define EN0_CRDAHI	EI_SHIFT(0x09)	/* high byte, current remote dma address RD */
182 #define EN0_RSARHI	EI_SHIFT(0x09)	/* Remote start address reg 1 */
183 #define EN0_RCNTLO	EI_SHIFT(0x0a)	/* Remote byte count reg WR */
184 #define EN0_RCNTHI	EI_SHIFT(0x0b)	/* Remote byte count reg WR */
185 #define EN0_RSR		EI_SHIFT(0x0c)	/* rx status reg RD */
186 #define EN0_RXCR	EI_SHIFT(0x0c)	/* RX configuration reg WR */
187 #define EN0_TXCR	EI_SHIFT(0x0d)	/* TX configuration reg WR */
188 #define EN0_COUNTER0	EI_SHIFT(0x0d)	/* Rcv alignment error counter RD */
189 #define EN0_DCFG	EI_SHIFT(0x0e)	/* Data configuration reg WR */
190 #define EN0_COUNTER1	EI_SHIFT(0x0e)	/* Rcv CRC error counter RD */
191 #define EN0_IMR		EI_SHIFT(0x0f)	/* Interrupt mask reg WR */
192 #define EN0_COUNTER2	EI_SHIFT(0x0f)	/* Rcv missed frame error counter RD */
193 
194 /* Bits in EN0_ISR - Interrupt status register */
195 #define ENISR_RX	0x01	/* Receiver, no error */
196 #define ENISR_TX	0x02	/* Transmitter, no error */
197 #define ENISR_RX_ERR	0x04	/* Receiver, with error */
198 #define ENISR_TX_ERR	0x08	/* Transmitter, with error */
199 #define ENISR_OVER	0x10	/* Receiver overwrote the ring */
200 #define ENISR_COUNTERS	0x20	/* Counters need emptying */
201 #define ENISR_RDC	0x40	/* remote dma complete */
202 #define ENISR_RESET	0x80	/* Reset completed */
203 #define ENISR_ALL	0x3f	/* Interrupts we will enable */
204 
205 /* Bits in EN0_DCFG - Data config register */
206 #define ENDCFG_WTS	0x01	/* word transfer mode selection */
207 #define ENDCFG_BOS	0x02	/* byte order selection */
208 
209 /* Page 1 register offsets. */
210 #define EN1_PHYS   EI_SHIFT(0x01)	/* This board's physical enet addr RD WR */
211 #define EN1_PHYS_SHIFT(i)  EI_SHIFT(i+1) /* Get and set mac address */
212 #define EN1_CURPAG EI_SHIFT(0x07)	/* Current memory page RD WR */
213 #define EN1_MULT   EI_SHIFT(0x08)	/* Multicast filter mask array (8 bytes) RD WR */
214 #define EN1_MULT_SHIFT(i)  EI_SHIFT(8+i) /* Get and set multicast filter */
215 
216 /* Bits in received packet status byte and EN0_RSR*/
217 #define ENRSR_RXOK	0x01	/* Received a good packet */
218 #define ENRSR_CRC	0x02	/* CRC error */
219 #define ENRSR_FAE	0x04	/* frame alignment error */
220 #define ENRSR_FO	0x08	/* FIFO overrun */
221 #define ENRSR_MPA	0x10	/* missed pkt */
222 #define ENRSR_PHY	0x20	/* physical/multicast address */
223 #define ENRSR_DIS	0x40	/* receiver disable. set in monitor mode */
224 #define ENRSR_DEF	0x80	/* deferring */
225 
226 /* Transmitted packet status, EN0_TSR. */
227 #define ENTSR_PTX 0x01	/* Packet transmitted without error */
228 #define ENTSR_ND  0x02	/* The transmit wasn't deferred. */
229 #define ENTSR_COL 0x04	/* The transmit collided at least once. */
230 #define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
231 #define ENTSR_CRS 0x10	/* The carrier sense was lost. */
232 #define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
233 #define ENTSR_CDH 0x40	/* The collision detect "heartbeat" signal was lost. */
234 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
235 
236 #endif /* _8390_h */
237