1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c)  2018 Intel Corporation */
3 
4 #ifndef _IGC_BASE_H_
5 #define _IGC_BASE_H_
6 
7 /* forward declaration */
8 void igc_rx_fifo_flush_base(struct igc_hw *hw);
9 void igc_power_down_phy_copper_base(struct igc_hw *hw);
10 bool igc_is_device_id_i225(struct igc_hw *hw);
11 bool igc_is_device_id_i226(struct igc_hw *hw);
12 
13 /* Transmit Descriptor - Advanced */
14 union igc_adv_tx_desc {
15 	struct {
16 		__le64 buffer_addr;    /* Address of descriptor's data buf */
17 		__le32 cmd_type_len;
18 		__le32 olinfo_status;
19 	} read;
20 	struct {
21 		__le64 rsvd;       /* Reserved */
22 		__le32 nxtseq_seed;
23 		__le32 status;
24 	} wb;
25 };
26 
27 /* Context descriptors */
28 struct igc_adv_tx_context_desc {
29 	__le32 vlan_macip_lens;
30 	__le32 launch_time;
31 	__le32 type_tucmd_mlhl;
32 	__le32 mss_l4len_idx;
33 };
34 
35 /* Adv Transmit Descriptor Config Masks */
36 #define IGC_ADVTXD_MAC_TSTAMP	0x00080000 /* IEEE1588 Timestamp packet */
37 #define IGC_ADVTXD_DTYP_CTXT	0x00200000 /* Advanced Context Descriptor */
38 #define IGC_ADVTXD_DTYP_DATA	0x00300000 /* Advanced Data Descriptor */
39 #define IGC_ADVTXD_DCMD_EOP	0x01000000 /* End of Packet */
40 #define IGC_ADVTXD_DCMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
41 #define IGC_ADVTXD_DCMD_RS	0x08000000 /* Report Status */
42 #define IGC_ADVTXD_DCMD_DEXT	0x20000000 /* Descriptor extension (1=Adv) */
43 #define IGC_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
44 #define IGC_ADVTXD_DCMD_TSE	0x80000000 /* TCP Seg enable */
45 #define IGC_ADVTXD_PAYLEN_SHIFT	14 /* Adv desc PAYLEN shift */
46 
47 #define IGC_RAR_ENTRIES		16
48 
49 /* Receive Descriptor - Advanced */
50 union igc_adv_rx_desc {
51 	struct {
52 		__le64 pkt_addr; /* Packet buffer address */
53 		__le64 hdr_addr; /* Header buffer address */
54 	} read;
55 	struct {
56 		struct {
57 			union {
58 				__le32 data;
59 				struct {
60 					__le16 pkt_info; /*RSS type, Pkt type*/
61 					/* Split Header, header buffer len */
62 					__le16 hdr_info;
63 				} hs_rss;
64 			} lo_dword;
65 			union {
66 				__le32 rss; /* RSS Hash */
67 				struct {
68 					__le16 ip_id; /* IP id */
69 					__le16 csum; /* Packet Checksum */
70 				} csum_ip;
71 			} hi_dword;
72 		} lower;
73 		struct {
74 			__le32 status_error; /* ext status/error */
75 			__le16 length; /* Packet length */
76 			__le16 vlan; /* VLAN tag */
77 		} upper;
78 	} wb;  /* writeback */
79 };
80 
81 /* Additional Transmit Descriptor Control definitions */
82 #define IGC_TXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Tx Queue */
83 #define IGC_TXDCTL_SWFLUSH	0x04000000 /* Transmit Software Flush */
84 
85 /* Additional Receive Descriptor Control definitions */
86 #define IGC_RXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Rx Queue */
87 #define IGC_RXDCTL_SWFLUSH		0x04000000 /* Receive Software Flush */
88 
89 /* SRRCTL bit definitions */
90 #define IGC_SRRCTL_BSIZEPKT_SHIFT		10 /* Shift _right_ */
91 #define IGC_SRRCTL_BSIZEHDRSIZE_SHIFT		2  /* Shift _left_ */
92 #define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF	0x02000000
93 
94 #endif /* _IGC_BASE_H */
95