1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2022 Marvell. 5 * 6 */ 7 8 #ifndef __RVU_NPC_HASH_H 9 #define __RVU_NPC_HASH_H 10 11 #define RVU_NPC_HASH_SECRET_KEY0 0xa9d5af4c9fbc76b1 12 #define RVU_NPC_HASH_SECRET_KEY1 0xa9d5af4c9fbc87b4 13 #define RVU_NPC_HASH_SECRET_KEY2 0x5954c9e7 14 15 #define NPC_MAX_HASH 2 16 #define NPC_MAX_HASH_MASK 2 17 18 #define KEX_LD_CFG_USE_HASH(use_hash, bytesm1, hdr_ofs, ena, flags_ena, key_ofs) \ 19 ((use_hash) << 20 | ((bytesm1) << 16) | ((hdr_ofs) << 8) | \ 20 ((ena) << 7) | ((flags_ena) << 6) | ((key_ofs) & 0x3F)) 21 #define KEX_LD_CFG_HASH(hdr_ofs, bytesm1, lt_en, lid_en, lid, ltype_match, ltype_mask) \ 22 (((hdr_ofs) << 32) | ((bytesm1) << 16) | \ 23 ((lt_en) << 12) | ((lid_en) << 11) | ((lid) << 8) | \ 24 ((ltype_match) << 4) | ((ltype_mask) & 0xF)) 25 26 #define SET_KEX_LD_HASH(intf, ld, cfg) \ 27 rvu_write64(rvu, blkaddr, \ 28 NPC_AF_INTFX_HASHX_CFG(intf, ld), cfg) 29 30 #define SET_KEX_LD_HASH_MASK(intf, ld, mask_idx, cfg) \ 31 rvu_write64(rvu, blkaddr, \ 32 NPC_AF_INTFX_HASHX_MASKX(intf, ld, mask_idx), cfg) 33 34 #define SET_KEX_LD_HASH_CTRL(intf, ld, cfg) \ 35 rvu_write64(rvu, blkaddr, \ 36 NPC_AF_INTFX_HASHX_RESULT_CTRL(intf, ld), cfg) 37 38 struct npc_mcam_kex_hash { 39 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 40 bool lid_lt_ld_hash_en[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 41 /* NPC_AF_INTF(0..1)_HASH(0..1)_CFG */ 42 u64 hash[NPC_MAX_INTF][NPC_MAX_HASH]; 43 /* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */ 44 u64 hash_mask[NPC_MAX_INTF][NPC_MAX_HASH][NPC_MAX_HASH_MASK]; 45 /* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */ 46 u64 hash_ctrl[NPC_MAX_INTF][NPC_MAX_HASH]; 47 } __packed; 48 49 void npc_update_field_hash(struct rvu *rvu, u8 intf, 50 struct mcam_entry *entry, 51 int blkaddr, 52 u64 features, 53 struct flow_msg *pkt, 54 struct flow_msg *mask, 55 struct flow_msg *opkt, 56 struct flow_msg *omask); 57 void npc_config_secret_key(struct rvu *rvu, int blkaddr); 58 void npc_program_mkex_hash(struct rvu *rvu, int blkaddr); 59 u32 npc_field_hash_calc(u64 *ldata, struct npc_mcam_kex_hash *mkex_hash, 60 u64 *secret_key, u8 intf, u8 hash_idx); 61 62 static struct npc_mcam_kex_hash npc_mkex_hash_default __maybe_unused = { 63 .lid_lt_ld_hash_en = { 64 [NIX_INTF_RX] = { 65 [NPC_LID_LC] = { 66 [NPC_LT_LC_IP6] = { 67 true, 68 true, 69 }, 70 }, 71 }, 72 73 [NIX_INTF_TX] = { 74 [NPC_LID_LC] = { 75 [NPC_LT_LC_IP6] = { 76 true, 77 true, 78 }, 79 }, 80 }, 81 }, 82 83 .hash = { 84 [NIX_INTF_RX] = { 85 KEX_LD_CFG_HASH(0x8ULL, 0xf, 0x1, 0x1, NPC_LID_LC, NPC_LT_LC_IP6, 0xf), 86 KEX_LD_CFG_HASH(0x18ULL, 0xf, 0x1, 0x1, NPC_LID_LC, NPC_LT_LC_IP6, 0xf), 87 }, 88 89 [NIX_INTF_TX] = { 90 KEX_LD_CFG_HASH(0x8ULL, 0xf, 0x1, 0x1, NPC_LID_LC, NPC_LT_LC_IP6, 0xf), 91 KEX_LD_CFG_HASH(0x18ULL, 0xf, 0x1, 0x1, NPC_LID_LC, NPC_LT_LC_IP6, 0xf), 92 }, 93 }, 94 95 .hash_mask = { 96 [NIX_INTF_RX] = { 97 [0] = { 98 GENMASK_ULL(63, 0), 99 GENMASK_ULL(63, 0), 100 }, 101 [1] = { 102 GENMASK_ULL(63, 0), 103 GENMASK_ULL(63, 0), 104 }, 105 }, 106 107 [NIX_INTF_TX] = { 108 [0] = { 109 GENMASK_ULL(63, 0), 110 GENMASK_ULL(63, 0), 111 }, 112 [1] = { 113 GENMASK_ULL(63, 0), 114 GENMASK_ULL(63, 0), 115 }, 116 }, 117 }, 118 119 .hash_ctrl = { 120 [NIX_INTF_RX] = { 121 [0] = GENMASK_ULL(63, 32), /* MSB 32 bit is mask and LSB 32 bit is offset. */ 122 [1] = GENMASK_ULL(63, 32), /* MSB 32 bit is mask and LSB 32 bit is offset. */ 123 }, 124 125 [NIX_INTF_TX] = { 126 [0] = GENMASK_ULL(63, 32), /* MSB 32 bit is mask and LSB 32 bit is offset. */ 127 [1] = GENMASK_ULL(63, 32), /* MSB 32 bit is mask and LSB 32 bit is offset. */ 128 }, 129 }, 130 }; 131 132 /* If exact match table support is enabled, enable drop rules */ 133 #define NPC_MCAM_DROP_RULE_MAX 30 134 #define NPC_MCAM_SDP_DROP_RULE_IDX 0 135 136 #define RVU_PFFUNC(pf, func) \ 137 ((((pf) & RVU_PFVF_PF_MASK) << RVU_PFVF_PF_SHIFT) | \ 138 (((func) & RVU_PFVF_FUNC_MASK) << RVU_PFVF_FUNC_SHIFT)) 139 140 enum npc_exact_opc_type { 141 NPC_EXACT_OPC_MEM, 142 NPC_EXACT_OPC_CAM, 143 }; 144 145 struct npc_exact_table_entry { 146 struct list_head list; 147 struct list_head glist; 148 u32 seq_id; /* Sequence number of entry */ 149 u32 index; /* Mem table or cam table index */ 150 u32 mcam_idx; 151 /* Mcam index. This is valid only if "cmd" field is false */ 152 enum npc_exact_opc_type opc_type; 153 u16 chan; 154 u16 pcifunc; 155 u8 ways; 156 u8 mac[ETH_ALEN]; 157 u8 ctype; 158 u8 cgx_id; 159 u8 lmac_id; 160 bool cmd; /* Is added by ethtool command ? */ 161 }; 162 163 struct npc_exact_table { 164 struct mutex lock; /* entries update lock */ 165 unsigned long *id_bmap; 166 int num_drop_rules; 167 u32 tot_ids; 168 u16 cnt_cmd_rules[NPC_MCAM_DROP_RULE_MAX]; 169 u16 counter_idx[NPC_MCAM_DROP_RULE_MAX]; 170 bool promisc_mode[NPC_MCAM_DROP_RULE_MAX]; 171 struct { 172 int ways; 173 int depth; 174 unsigned long *bmap; 175 u64 mask; // Masks before hash calculation. 176 u16 hash_mask; // 11 bits for hash mask 177 u16 hash_offset; // 11 bits offset 178 } mem_table; 179 180 struct { 181 int depth; 182 unsigned long *bmap; 183 } cam_table; 184 185 struct { 186 bool valid; 187 u16 chan_val; 188 u16 chan_mask; 189 u16 pcifunc; 190 u8 drop_rule_idx; 191 } drop_rule_map[NPC_MCAM_DROP_RULE_MAX]; 192 193 #define NPC_EXACT_TBL_MAX_WAYS 4 194 195 struct list_head lhead_mem_tbl_entry[NPC_EXACT_TBL_MAX_WAYS]; 196 int mem_tbl_entry_cnt; 197 198 struct list_head lhead_cam_tbl_entry; 199 int cam_tbl_entry_cnt; 200 201 struct list_head lhead_gbl; 202 }; 203 204 bool rvu_npc_exact_has_match_table(struct rvu *rvu); 205 u32 rvu_npc_exact_get_max_entries(struct rvu *rvu); 206 int rvu_npc_exact_init(struct rvu *rvu); 207 int rvu_npc_exact_mac_addr_reset(struct rvu *rvu, struct cgx_mac_addr_reset_req *req, 208 struct msg_rsp *rsp); 209 210 int rvu_npc_exact_mac_addr_update(struct rvu *rvu, 211 struct cgx_mac_addr_update_req *req, 212 struct cgx_mac_addr_update_rsp *rsp); 213 214 int rvu_npc_exact_mac_addr_add(struct rvu *rvu, 215 struct cgx_mac_addr_add_req *req, 216 struct cgx_mac_addr_add_rsp *rsp); 217 218 int rvu_npc_exact_mac_addr_del(struct rvu *rvu, 219 struct cgx_mac_addr_del_req *req, 220 struct msg_rsp *rsp); 221 222 int rvu_npc_exact_mac_addr_set(struct rvu *rvu, struct cgx_mac_addr_set_or_get *req, 223 struct cgx_mac_addr_set_or_get *rsp); 224 225 void rvu_npc_exact_reset(struct rvu *rvu, u16 pcifunc); 226 227 bool rvu_npc_exact_can_disable_feature(struct rvu *rvu); 228 void rvu_npc_exact_disable_feature(struct rvu *rvu); 229 void rvu_npc_exact_reset(struct rvu *rvu, u16 pcifunc); 230 u16 rvu_npc_exact_drop_rule_to_pcifunc(struct rvu *rvu, u32 drop_rule_idx); 231 int rvu_npc_exact_promisc_disable(struct rvu *rvu, u16 pcifunc); 232 int rvu_npc_exact_promisc_enable(struct rvu *rvu, u16 pcifunc); 233 #endif /* RVU_NPC_HASH_H */ 234