1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3   Copyright (C) 2013  Vayavya Labs Pvt Ltd
4 
5   This implements all the API for managing HW timestamp & PTP.
6 
7 
8   Author: Rayagond Kokatanur <rayagond@vayavyalabs.com>
9   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
10 *******************************************************************************/
11 
12 #include <linux/io.h>
13 #include <linux/iopoll.h>
14 #include <linux/delay.h>
15 #include <linux/ptp_clock_kernel.h>
16 #include "common.h"
17 #include "stmmac_ptp.h"
18 #include "dwmac4.h"
19 #include "stmmac.h"
20 
config_hw_tstamping(void __iomem * ioaddr,u32 data)21 static void config_hw_tstamping(void __iomem *ioaddr, u32 data)
22 {
23 	writel(data, ioaddr + PTP_TCR);
24 }
25 
config_sub_second_increment(void __iomem * ioaddr,u32 ptp_clock,int gmac4,u32 * ssinc)26 static void config_sub_second_increment(void __iomem *ioaddr,
27 		u32 ptp_clock, int gmac4, u32 *ssinc)
28 {
29 	u32 value = readl(ioaddr + PTP_TCR);
30 	unsigned long data;
31 	u32 reg_value;
32 
33 	/* For GMAC3.x, 4.x versions, in "fine adjustement mode" set sub-second
34 	 * increment to twice the number of nanoseconds of a clock cycle.
35 	 * The calculation of the default_addend value by the caller will set it
36 	 * to mid-range = 2^31 when the remainder of this division is zero,
37 	 * which will make the accumulator overflow once every 2 ptp_clock
38 	 * cycles, adding twice the number of nanoseconds of a clock cycle :
39 	 * 2000000000ULL / ptp_clock.
40 	 */
41 	if (value & PTP_TCR_TSCFUPDT)
42 		data = (2000000000ULL / ptp_clock);
43 	else
44 		data = (1000000000ULL / ptp_clock);
45 
46 	/* 0.465ns accuracy */
47 	if (!(value & PTP_TCR_TSCTRLSSR))
48 		data = (data * 1000) / 465;
49 
50 	if (data > PTP_SSIR_SSINC_MAX)
51 		data = PTP_SSIR_SSINC_MAX;
52 
53 	reg_value = data;
54 	if (gmac4)
55 		reg_value <<= GMAC4_PTP_SSIR_SSINC_SHIFT;
56 
57 	writel(reg_value, ioaddr + PTP_SSIR);
58 
59 	if (ssinc)
60 		*ssinc = data;
61 }
62 
init_systime(void __iomem * ioaddr,u32 sec,u32 nsec)63 static int init_systime(void __iomem *ioaddr, u32 sec, u32 nsec)
64 {
65 	u32 value;
66 
67 	writel(sec, ioaddr + PTP_STSUR);
68 	writel(nsec, ioaddr + PTP_STNSUR);
69 	/* issue command to initialize the system time value */
70 	value = readl(ioaddr + PTP_TCR);
71 	value |= PTP_TCR_TSINIT;
72 	writel(value, ioaddr + PTP_TCR);
73 
74 	/* wait for present system time initialize to complete */
75 	return readl_poll_timeout_atomic(ioaddr + PTP_TCR, value,
76 				 !(value & PTP_TCR_TSINIT),
77 				 10, 100000);
78 }
79 
config_addend(void __iomem * ioaddr,u32 addend)80 static int config_addend(void __iomem *ioaddr, u32 addend)
81 {
82 	u32 value;
83 	int limit;
84 
85 	writel(addend, ioaddr + PTP_TAR);
86 	/* issue command to update the addend value */
87 	value = readl(ioaddr + PTP_TCR);
88 	value |= PTP_TCR_TSADDREG;
89 	writel(value, ioaddr + PTP_TCR);
90 
91 	/* wait for present addend update to complete */
92 	limit = 10;
93 	while (limit--) {
94 		if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSADDREG))
95 			break;
96 		mdelay(10);
97 	}
98 	if (limit < 0)
99 		return -EBUSY;
100 
101 	return 0;
102 }
103 
adjust_systime(void __iomem * ioaddr,u32 sec,u32 nsec,int add_sub,int gmac4)104 static int adjust_systime(void __iomem *ioaddr, u32 sec, u32 nsec,
105 		int add_sub, int gmac4)
106 {
107 	u32 value;
108 	int limit;
109 
110 	if (add_sub) {
111 		/* If the new sec value needs to be subtracted with
112 		 * the system time, then MAC_STSUR reg should be
113 		 * programmed with (2^32 – <new_sec_value>)
114 		 */
115 		if (gmac4)
116 			sec = -sec;
117 
118 		value = readl(ioaddr + PTP_TCR);
119 		if (value & PTP_TCR_TSCTRLSSR)
120 			nsec = (PTP_DIGITAL_ROLLOVER_MODE - nsec);
121 		else
122 			nsec = (PTP_BINARY_ROLLOVER_MODE - nsec);
123 	}
124 
125 	writel(sec, ioaddr + PTP_STSUR);
126 	value = (add_sub << PTP_STNSUR_ADDSUB_SHIFT) | nsec;
127 	writel(value, ioaddr + PTP_STNSUR);
128 
129 	/* issue command to initialize the system time value */
130 	value = readl(ioaddr + PTP_TCR);
131 	value |= PTP_TCR_TSUPDT;
132 	writel(value, ioaddr + PTP_TCR);
133 
134 	/* wait for present system time adjust/update to complete */
135 	limit = 10;
136 	while (limit--) {
137 		if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSUPDT))
138 			break;
139 		mdelay(10);
140 	}
141 	if (limit < 0)
142 		return -EBUSY;
143 
144 	return 0;
145 }
146 
get_systime(void __iomem * ioaddr,u64 * systime)147 static void get_systime(void __iomem *ioaddr, u64 *systime)
148 {
149 	u64 ns, sec0, sec1;
150 
151 	/* Get the TSS value */
152 	sec1 = readl_relaxed(ioaddr + PTP_STSR);
153 	do {
154 		sec0 = sec1;
155 		/* Get the TSSS value */
156 		ns = readl_relaxed(ioaddr + PTP_STNSR);
157 		/* Get the TSS value */
158 		sec1 = readl_relaxed(ioaddr + PTP_STSR);
159 	} while (sec0 != sec1);
160 
161 	if (systime)
162 		*systime = ns + (sec1 * 1000000000ULL);
163 }
164 
get_ptptime(void __iomem * ptpaddr,u64 * ptp_time)165 static void get_ptptime(void __iomem *ptpaddr, u64 *ptp_time)
166 {
167 	u64 ns;
168 
169 	ns = readl(ptpaddr + PTP_ATNR);
170 	ns += readl(ptpaddr + PTP_ATSR) * NSEC_PER_SEC;
171 
172 	*ptp_time = ns;
173 }
174 
timestamp_interrupt(struct stmmac_priv * priv)175 static void timestamp_interrupt(struct stmmac_priv *priv)
176 {
177 	u32 num_snapshot, ts_status, tsync_int;
178 	struct ptp_clock_event event;
179 	unsigned long flags;
180 	u64 ptp_time;
181 	int i;
182 
183 	if (priv->plat->int_snapshot_en) {
184 		wake_up(&priv->tstamp_busy_wait);
185 		return;
186 	}
187 
188 	tsync_int = readl(priv->ioaddr + GMAC_INT_STATUS) & GMAC_INT_TSIE;
189 
190 	if (!tsync_int)
191 		return;
192 
193 	/* Read timestamp status to clear interrupt from either external
194 	 * timestamp or start/end of PPS.
195 	 */
196 	ts_status = readl(priv->ioaddr + GMAC_TIMESTAMP_STATUS);
197 
198 	if (!priv->plat->ext_snapshot_en)
199 		return;
200 
201 	num_snapshot = (ts_status & GMAC_TIMESTAMP_ATSNS_MASK) >>
202 		       GMAC_TIMESTAMP_ATSNS_SHIFT;
203 
204 	for (i = 0; i < num_snapshot; i++) {
205 		read_lock_irqsave(&priv->ptp_lock, flags);
206 		get_ptptime(priv->ptpaddr, &ptp_time);
207 		read_unlock_irqrestore(&priv->ptp_lock, flags);
208 		event.type = PTP_CLOCK_EXTTS;
209 		event.index = 0;
210 		event.timestamp = ptp_time;
211 		ptp_clock_event(priv->ptp_clock, &event);
212 	}
213 }
214 
215 const struct stmmac_hwtimestamp stmmac_ptp = {
216 	.config_hw_tstamping = config_hw_tstamping,
217 	.init_systime = init_systime,
218 	.config_sub_second_increment = config_sub_second_increment,
219 	.config_addend = config_addend,
220 	.adjust_systime = adjust_systime,
221 	.get_systime = get_systime,
222 	.get_ptptime = get_ptptime,
223 	.timestamp_interrupt = timestamp_interrupt,
224 };
225