1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 STMMAC Ethernet Driver -- MDIO bus implementation
4 Provides Bus interface for MII registers
5
6 Copyright (C) 2007-2009 STMicroelectronics Ltd
7
8
9 Author: Carl Shaw <carl.shaw@st.com>
10 Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
11 *******************************************************************************/
12
13 #include <linux/gpio/consumer.h>
14 #include <linux/io.h>
15 #include <linux/iopoll.h>
16 #include <linux/mii.h>
17 #include <linux/of_mdio.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/phy.h>
20 #include <linux/property.h>
21 #include <linux/slab.h>
22
23 #include "dwxgmac2.h"
24 #include "stmmac.h"
25
26 #define MII_BUSY 0x00000001
27 #define MII_WRITE 0x00000002
28 #define MII_DATA_MASK GENMASK(15, 0)
29
30 /* GMAC4 defines */
31 #define MII_GMAC4_GOC_SHIFT 2
32 #define MII_GMAC4_REG_ADDR_SHIFT 16
33 #define MII_GMAC4_WRITE (1 << MII_GMAC4_GOC_SHIFT)
34 #define MII_GMAC4_READ (3 << MII_GMAC4_GOC_SHIFT)
35 #define MII_GMAC4_C45E BIT(1)
36
37 /* XGMAC defines */
38 #define MII_XGMAC_SADDR BIT(18)
39 #define MII_XGMAC_CMD_SHIFT 16
40 #define MII_XGMAC_WRITE (1 << MII_XGMAC_CMD_SHIFT)
41 #define MII_XGMAC_READ (3 << MII_XGMAC_CMD_SHIFT)
42 #define MII_XGMAC_BUSY BIT(22)
43 #define MII_XGMAC_MAX_C22ADDR 3
44 #define MII_XGMAC_C22P_MASK GENMASK(MII_XGMAC_MAX_C22ADDR, 0)
45 #define MII_XGMAC_PA_SHIFT 16
46 #define MII_XGMAC_DA_SHIFT 21
47
stmmac_xgmac2_c45_format(struct stmmac_priv * priv,int phyaddr,int devad,int phyreg,u32 * hw_addr)48 static void stmmac_xgmac2_c45_format(struct stmmac_priv *priv, int phyaddr,
49 int devad, int phyreg, u32 *hw_addr)
50 {
51 u32 tmp;
52
53 /* Set port as Clause 45 */
54 tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P);
55 tmp &= ~BIT(phyaddr);
56 writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P);
57
58 *hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0xffff);
59 *hw_addr |= devad << MII_XGMAC_DA_SHIFT;
60 }
61
stmmac_xgmac2_c22_format(struct stmmac_priv * priv,int phyaddr,int phyreg,u32 * hw_addr)62 static void stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr,
63 int phyreg, u32 *hw_addr)
64 {
65 u32 tmp;
66
67 /* Set port as Clause 22 */
68 tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P);
69 tmp &= ~MII_XGMAC_C22P_MASK;
70 tmp |= BIT(phyaddr);
71 writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P);
72
73 *hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0x1f);
74 }
75
stmmac_xgmac2_mdio_read(struct stmmac_priv * priv,u32 addr,u32 value)76 static int stmmac_xgmac2_mdio_read(struct stmmac_priv *priv, u32 addr,
77 u32 value)
78 {
79 unsigned int mii_address = priv->hw->mii.addr;
80 unsigned int mii_data = priv->hw->mii.data;
81 u32 tmp;
82 int ret;
83
84 ret = pm_runtime_resume_and_get(priv->device);
85 if (ret < 0)
86 return ret;
87
88 /* Wait until any existing MII operation is complete */
89 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
90 !(tmp & MII_XGMAC_BUSY), 100, 10000)) {
91 ret = -EBUSY;
92 goto err_disable_clks;
93 }
94
95 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
96 & priv->hw->mii.clk_csr_mask;
97 value |= MII_XGMAC_READ;
98
99 /* Wait until any existing MII operation is complete */
100 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
101 !(tmp & MII_XGMAC_BUSY), 100, 10000)) {
102 ret = -EBUSY;
103 goto err_disable_clks;
104 }
105
106 /* Set the MII address register to read */
107 writel(addr, priv->ioaddr + mii_address);
108 writel(value, priv->ioaddr + mii_data);
109
110 /* Wait until any existing MII operation is complete */
111 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
112 !(tmp & MII_XGMAC_BUSY), 100, 10000)) {
113 ret = -EBUSY;
114 goto err_disable_clks;
115 }
116
117 /* Read the data from the MII data register */
118 ret = (int)readl(priv->ioaddr + mii_data) & GENMASK(15, 0);
119
120 err_disable_clks:
121 pm_runtime_put(priv->device);
122
123 return ret;
124 }
125
stmmac_xgmac2_mdio_read_c22(struct mii_bus * bus,int phyaddr,int phyreg)126 static int stmmac_xgmac2_mdio_read_c22(struct mii_bus *bus, int phyaddr,
127 int phyreg)
128 {
129 struct net_device *ndev = bus->priv;
130 struct stmmac_priv *priv;
131 u32 addr;
132
133 priv = netdev_priv(ndev);
134
135 /* HW does not support C22 addr >= 4 */
136 if (phyaddr > MII_XGMAC_MAX_C22ADDR)
137 return -ENODEV;
138
139 stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
140
141 return stmmac_xgmac2_mdio_read(priv, addr, MII_XGMAC_BUSY);
142 }
143
stmmac_xgmac2_mdio_read_c45(struct mii_bus * bus,int phyaddr,int devad,int phyreg)144 static int stmmac_xgmac2_mdio_read_c45(struct mii_bus *bus, int phyaddr,
145 int devad, int phyreg)
146 {
147 struct net_device *ndev = bus->priv;
148 struct stmmac_priv *priv;
149 u32 addr;
150
151 priv = netdev_priv(ndev);
152
153 stmmac_xgmac2_c45_format(priv, phyaddr, devad, phyreg, &addr);
154
155 return stmmac_xgmac2_mdio_read(priv, addr, MII_XGMAC_BUSY);
156 }
157
stmmac_xgmac2_mdio_write(struct stmmac_priv * priv,u32 addr,u32 value,u16 phydata)158 static int stmmac_xgmac2_mdio_write(struct stmmac_priv *priv, u32 addr,
159 u32 value, u16 phydata)
160 {
161 unsigned int mii_address = priv->hw->mii.addr;
162 unsigned int mii_data = priv->hw->mii.data;
163 u32 tmp;
164 int ret;
165
166 ret = pm_runtime_resume_and_get(priv->device);
167 if (ret < 0)
168 return ret;
169
170 /* Wait until any existing MII operation is complete */
171 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
172 !(tmp & MII_XGMAC_BUSY), 100, 10000)) {
173 ret = -EBUSY;
174 goto err_disable_clks;
175 }
176
177 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
178 & priv->hw->mii.clk_csr_mask;
179 value |= phydata;
180 value |= MII_XGMAC_WRITE;
181
182 /* Wait until any existing MII operation is complete */
183 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
184 !(tmp & MII_XGMAC_BUSY), 100, 10000)) {
185 ret = -EBUSY;
186 goto err_disable_clks;
187 }
188
189 /* Set the MII address register to write */
190 writel(addr, priv->ioaddr + mii_address);
191 writel(value, priv->ioaddr + mii_data);
192
193 /* Wait until any existing MII operation is complete */
194 ret = readl_poll_timeout(priv->ioaddr + mii_data, tmp,
195 !(tmp & MII_XGMAC_BUSY), 100, 10000);
196
197 err_disable_clks:
198 pm_runtime_put(priv->device);
199
200 return ret;
201 }
202
stmmac_xgmac2_mdio_write_c22(struct mii_bus * bus,int phyaddr,int phyreg,u16 phydata)203 static int stmmac_xgmac2_mdio_write_c22(struct mii_bus *bus, int phyaddr,
204 int phyreg, u16 phydata)
205 {
206 struct net_device *ndev = bus->priv;
207 struct stmmac_priv *priv;
208 u32 addr;
209
210 priv = netdev_priv(ndev);
211
212 /* HW does not support C22 addr >= 4 */
213 if (phyaddr > MII_XGMAC_MAX_C22ADDR)
214 return -ENODEV;
215
216 stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
217
218 return stmmac_xgmac2_mdio_write(priv, addr,
219 MII_XGMAC_BUSY | MII_XGMAC_SADDR, phydata);
220 }
221
stmmac_xgmac2_mdio_write_c45(struct mii_bus * bus,int phyaddr,int devad,int phyreg,u16 phydata)222 static int stmmac_xgmac2_mdio_write_c45(struct mii_bus *bus, int phyaddr,
223 int devad, int phyreg, u16 phydata)
224 {
225 struct net_device *ndev = bus->priv;
226 struct stmmac_priv *priv;
227 u32 addr;
228
229 priv = netdev_priv(ndev);
230
231 stmmac_xgmac2_c45_format(priv, phyaddr, devad, phyreg, &addr);
232
233 return stmmac_xgmac2_mdio_write(priv, addr, MII_XGMAC_BUSY,
234 phydata);
235 }
236
stmmac_mdio_read(struct stmmac_priv * priv,int data,u32 value)237 static int stmmac_mdio_read(struct stmmac_priv *priv, int data, u32 value)
238 {
239 unsigned int mii_address = priv->hw->mii.addr;
240 unsigned int mii_data = priv->hw->mii.data;
241 u32 v;
242
243 if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
244 100, 10000))
245 return -EBUSY;
246
247 writel(data, priv->ioaddr + mii_data);
248 writel(value, priv->ioaddr + mii_address);
249
250 if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
251 100, 10000))
252 return -EBUSY;
253
254 /* Read the data from the MII data register */
255 return readl(priv->ioaddr + mii_data) & MII_DATA_MASK;
256 }
257
258 /**
259 * stmmac_mdio_read_c22
260 * @bus: points to the mii_bus structure
261 * @phyaddr: MII addr
262 * @phyreg: MII reg
263 * Description: it reads data from the MII register from within the phy device.
264 * For the 7111 GMAC, we must set the bit 0 in the MII address register while
265 * accessing the PHY registers.
266 * Fortunately, it seems this has no drawback for the 7109 MAC.
267 */
stmmac_mdio_read_c22(struct mii_bus * bus,int phyaddr,int phyreg)268 static int stmmac_mdio_read_c22(struct mii_bus *bus, int phyaddr, int phyreg)
269 {
270 struct net_device *ndev = bus->priv;
271 struct stmmac_priv *priv = netdev_priv(ndev);
272 u32 value = MII_BUSY;
273 int data = 0;
274
275 data = pm_runtime_resume_and_get(priv->device);
276 if (data < 0)
277 return data;
278
279 value |= (phyaddr << priv->hw->mii.addr_shift)
280 & priv->hw->mii.addr_mask;
281 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
282 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
283 & priv->hw->mii.clk_csr_mask;
284 if (priv->plat->has_gmac4) {
285 value |= MII_GMAC4_READ;
286 }
287
288 data = stmmac_mdio_read(priv, data, value);
289
290 pm_runtime_put(priv->device);
291
292 return data;
293 }
294
295 /**
296 * stmmac_mdio_read_c45
297 * @bus: points to the mii_bus structure
298 * @phyaddr: MII addr
299 * @devad: device address to read
300 * @phyreg: MII reg
301 * Description: it reads data from the MII register from within the phy device.
302 * For the 7111 GMAC, we must set the bit 0 in the MII address register while
303 * accessing the PHY registers.
304 * Fortunately, it seems this has no drawback for the 7109 MAC.
305 */
stmmac_mdio_read_c45(struct mii_bus * bus,int phyaddr,int devad,int phyreg)306 static int stmmac_mdio_read_c45(struct mii_bus *bus, int phyaddr, int devad,
307 int phyreg)
308 {
309 struct net_device *ndev = bus->priv;
310 struct stmmac_priv *priv = netdev_priv(ndev);
311 u32 value = MII_BUSY;
312 int data = 0;
313
314 data = pm_runtime_get_sync(priv->device);
315 if (data < 0) {
316 pm_runtime_put_noidle(priv->device);
317 return data;
318 }
319
320 value |= (phyaddr << priv->hw->mii.addr_shift)
321 & priv->hw->mii.addr_mask;
322 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
323 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
324 & priv->hw->mii.clk_csr_mask;
325 value |= MII_GMAC4_READ;
326 value |= MII_GMAC4_C45E;
327 value &= ~priv->hw->mii.reg_mask;
328 value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
329
330 data |= phyreg << MII_GMAC4_REG_ADDR_SHIFT;
331
332 data = stmmac_mdio_read(priv, data, value);
333
334 pm_runtime_put(priv->device);
335
336 return data;
337 }
338
stmmac_mdio_write(struct stmmac_priv * priv,int data,u32 value)339 static int stmmac_mdio_write(struct stmmac_priv *priv, int data, u32 value)
340 {
341 unsigned int mii_address = priv->hw->mii.addr;
342 unsigned int mii_data = priv->hw->mii.data;
343 u32 v;
344
345 /* Wait until any existing MII operation is complete */
346 if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
347 100, 10000))
348 return -EBUSY;
349
350 /* Set the MII address register to write */
351 writel(data, priv->ioaddr + mii_data);
352 writel(value, priv->ioaddr + mii_address);
353
354 /* Wait until any existing MII operation is complete */
355 return readl_poll_timeout(priv->ioaddr + mii_address, v,
356 !(v & MII_BUSY), 100, 10000);
357 }
358
359 /**
360 * stmmac_mdio_write_c22
361 * @bus: points to the mii_bus structure
362 * @phyaddr: MII addr
363 * @phyreg: MII reg
364 * @phydata: phy data
365 * Description: it writes the data into the MII register from within the device.
366 */
stmmac_mdio_write_c22(struct mii_bus * bus,int phyaddr,int phyreg,u16 phydata)367 static int stmmac_mdio_write_c22(struct mii_bus *bus, int phyaddr, int phyreg,
368 u16 phydata)
369 {
370 struct net_device *ndev = bus->priv;
371 struct stmmac_priv *priv = netdev_priv(ndev);
372 int ret, data = phydata;
373 u32 value = MII_BUSY;
374
375 ret = pm_runtime_resume_and_get(priv->device);
376 if (ret < 0)
377 return ret;
378
379 value |= (phyaddr << priv->hw->mii.addr_shift)
380 & priv->hw->mii.addr_mask;
381 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
382
383 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
384 & priv->hw->mii.clk_csr_mask;
385 if (priv->plat->has_gmac4)
386 value |= MII_GMAC4_WRITE;
387 else
388 value |= MII_WRITE;
389
390 ret = stmmac_mdio_write(priv, data, value);
391
392 pm_runtime_put(priv->device);
393
394 return ret;
395 }
396
397 /**
398 * stmmac_mdio_write_c45
399 * @bus: points to the mii_bus structure
400 * @phyaddr: MII addr
401 * @phyreg: MII reg
402 * @devad: device address to read
403 * @phydata: phy data
404 * Description: it writes the data into the MII register from within the device.
405 */
stmmac_mdio_write_c45(struct mii_bus * bus,int phyaddr,int devad,int phyreg,u16 phydata)406 static int stmmac_mdio_write_c45(struct mii_bus *bus, int phyaddr,
407 int devad, int phyreg, u16 phydata)
408 {
409 struct net_device *ndev = bus->priv;
410 struct stmmac_priv *priv = netdev_priv(ndev);
411 int ret, data = phydata;
412 u32 value = MII_BUSY;
413
414 ret = pm_runtime_get_sync(priv->device);
415 if (ret < 0) {
416 pm_runtime_put_noidle(priv->device);
417 return ret;
418 }
419
420 value |= (phyaddr << priv->hw->mii.addr_shift)
421 & priv->hw->mii.addr_mask;
422 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
423
424 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
425 & priv->hw->mii.clk_csr_mask;
426
427 value |= MII_GMAC4_WRITE;
428 value |= MII_GMAC4_C45E;
429 value &= ~priv->hw->mii.reg_mask;
430 value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
431
432 data |= phyreg << MII_GMAC4_REG_ADDR_SHIFT;
433
434 ret = stmmac_mdio_write(priv, data, value);
435
436 pm_runtime_put(priv->device);
437
438 return ret;
439 }
440
441 /**
442 * stmmac_mdio_reset
443 * @bus: points to the mii_bus structure
444 * Description: reset the MII bus
445 */
stmmac_mdio_reset(struct mii_bus * bus)446 int stmmac_mdio_reset(struct mii_bus *bus)
447 {
448 #if IS_ENABLED(CONFIG_STMMAC_PLATFORM)
449 struct net_device *ndev = bus->priv;
450 struct stmmac_priv *priv = netdev_priv(ndev);
451 unsigned int mii_address = priv->hw->mii.addr;
452
453 #ifdef CONFIG_OF
454 if (priv->device->of_node) {
455 struct gpio_desc *reset_gpio;
456 u32 delays[3] = { 0, 0, 0 };
457
458 reset_gpio = devm_gpiod_get_optional(priv->device,
459 "snps,reset",
460 GPIOD_OUT_LOW);
461 if (IS_ERR(reset_gpio))
462 return PTR_ERR(reset_gpio);
463
464 device_property_read_u32_array(priv->device,
465 "snps,reset-delays-us",
466 delays, ARRAY_SIZE(delays));
467
468 if (delays[0])
469 msleep(DIV_ROUND_UP(delays[0], 1000));
470
471 gpiod_set_value_cansleep(reset_gpio, 1);
472 if (delays[1])
473 msleep(DIV_ROUND_UP(delays[1], 1000));
474
475 gpiod_set_value_cansleep(reset_gpio, 0);
476 if (delays[2])
477 msleep(DIV_ROUND_UP(delays[2], 1000));
478 }
479 #endif
480
481 /* This is a workaround for problems with the STE101P PHY.
482 * It doesn't complete its reset until at least one clock cycle
483 * on MDC, so perform a dummy mdio read. To be updated for GMAC4
484 * if needed.
485 */
486 if (!priv->plat->has_gmac4)
487 writel(0, priv->ioaddr + mii_address);
488 #endif
489 return 0;
490 }
491
stmmac_xpcs_setup(struct mii_bus * bus)492 int stmmac_xpcs_setup(struct mii_bus *bus)
493 {
494 struct net_device *ndev = bus->priv;
495 struct mdio_device *mdiodev;
496 struct stmmac_priv *priv;
497 struct dw_xpcs *xpcs;
498 int mode, addr;
499
500 priv = netdev_priv(ndev);
501 mode = priv->plat->phy_interface;
502
503 /* Try to probe the XPCS by scanning all addresses. */
504 for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
505 mdiodev = mdio_device_create(bus, addr);
506 if (IS_ERR(mdiodev))
507 continue;
508
509 xpcs = xpcs_create(mdiodev, mode);
510 if (IS_ERR_OR_NULL(xpcs)) {
511 mdio_device_free(mdiodev);
512 continue;
513 }
514
515 priv->hw->xpcs = xpcs;
516 break;
517 }
518
519 if (!priv->hw->xpcs) {
520 dev_warn(priv->device, "No xPCS found\n");
521 return -ENODEV;
522 }
523
524 return 0;
525 }
526
527 /**
528 * stmmac_mdio_register
529 * @ndev: net device structure
530 * Description: it registers the MII bus
531 */
stmmac_mdio_register(struct net_device * ndev)532 int stmmac_mdio_register(struct net_device *ndev)
533 {
534 int err = 0;
535 struct mii_bus *new_bus;
536 struct stmmac_priv *priv = netdev_priv(ndev);
537 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
538 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
539 struct device_node *mdio_node = priv->plat->mdio_node;
540 struct device *dev = ndev->dev.parent;
541 struct fwnode_handle *fixed_node;
542 int addr, found, max_addr;
543
544 if (!mdio_bus_data)
545 return 0;
546
547 new_bus = mdiobus_alloc();
548 if (!new_bus)
549 return -ENOMEM;
550
551 if (mdio_bus_data->irqs)
552 memcpy(new_bus->irq, mdio_bus_data->irqs, sizeof(new_bus->irq));
553
554 new_bus->name = "stmmac";
555
556 if (priv->plat->has_xgmac) {
557 new_bus->read = &stmmac_xgmac2_mdio_read_c22;
558 new_bus->write = &stmmac_xgmac2_mdio_write_c22;
559 new_bus->read_c45 = &stmmac_xgmac2_mdio_read_c45;
560 new_bus->write_c45 = &stmmac_xgmac2_mdio_write_c45;
561
562 /* Right now only C22 phys are supported */
563 max_addr = MII_XGMAC_MAX_C22ADDR + 1;
564
565 /* Check if DT specified an unsupported phy addr */
566 if (priv->plat->phy_addr > MII_XGMAC_MAX_C22ADDR)
567 dev_err(dev, "Unsupported phy_addr (max=%d)\n",
568 MII_XGMAC_MAX_C22ADDR);
569 } else {
570 new_bus->read = &stmmac_mdio_read_c22;
571 new_bus->write = &stmmac_mdio_write_c22;
572 if (priv->plat->has_gmac4) {
573 new_bus->read_c45 = &stmmac_mdio_read_c45;
574 new_bus->write_c45 = &stmmac_mdio_write_c45;
575 }
576
577 max_addr = PHY_MAX_ADDR;
578 }
579
580 if (mdio_bus_data->needs_reset)
581 new_bus->reset = &stmmac_mdio_reset;
582
583 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x",
584 new_bus->name, priv->plat->bus_id);
585 new_bus->priv = ndev;
586 new_bus->phy_mask = mdio_bus_data->phy_mask;
587 new_bus->parent = priv->device;
588
589 err = of_mdiobus_register(new_bus, mdio_node);
590 if (err != 0) {
591 dev_err_probe(dev, err, "Cannot register the MDIO bus\n");
592 goto bus_register_fail;
593 }
594
595 /* Looks like we need a dummy read for XGMAC only and C45 PHYs */
596 if (priv->plat->has_xgmac)
597 stmmac_xgmac2_mdio_read_c45(new_bus, 0, 0, 0);
598
599 /* If fixed-link is set, skip PHY scanning */
600 if (!fwnode)
601 fwnode = dev_fwnode(priv->device);
602
603 if (fwnode) {
604 fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link");
605 if (fixed_node) {
606 fwnode_handle_put(fixed_node);
607 goto bus_register_done;
608 }
609 }
610
611 if (priv->plat->phy_node || mdio_node)
612 goto bus_register_done;
613
614 found = 0;
615 for (addr = 0; addr < max_addr; addr++) {
616 struct phy_device *phydev = mdiobus_get_phy(new_bus, addr);
617
618 if (!phydev)
619 continue;
620
621 /*
622 * If an IRQ was provided to be assigned after
623 * the bus probe, do it here.
624 */
625 if (!mdio_bus_data->irqs &&
626 (mdio_bus_data->probed_phy_irq > 0)) {
627 new_bus->irq[addr] = mdio_bus_data->probed_phy_irq;
628 phydev->irq = mdio_bus_data->probed_phy_irq;
629 }
630
631 /*
632 * If we're going to bind the MAC to this PHY bus,
633 * and no PHY number was provided to the MAC,
634 * use the one probed here.
635 */
636 if (priv->plat->phy_addr == -1)
637 priv->plat->phy_addr = addr;
638
639 phy_attached_info(phydev);
640 found = 1;
641 }
642
643 if (!found && !mdio_node) {
644 dev_warn(dev, "No PHY found\n");
645 err = -ENODEV;
646 goto no_phy_found;
647 }
648
649 bus_register_done:
650 priv->mii = new_bus;
651
652 return 0;
653
654 no_phy_found:
655 mdiobus_unregister(new_bus);
656 bus_register_fail:
657 mdiobus_free(new_bus);
658 return err;
659 }
660
661 /**
662 * stmmac_mdio_unregister
663 * @ndev: net device structure
664 * Description: it unregisters the MII bus
665 */
stmmac_mdio_unregister(struct net_device * ndev)666 int stmmac_mdio_unregister(struct net_device *ndev)
667 {
668 struct stmmac_priv *priv = netdev_priv(ndev);
669
670 if (!priv->mii)
671 return 0;
672
673 if (priv->hw->xpcs) {
674 mdio_device_free(priv->hw->xpcs->mdiodev);
675 xpcs_destroy(priv->hw->xpcs);
676 }
677
678 mdiobus_unregister(priv->mii);
679 priv->mii->priv = NULL;
680 mdiobus_free(priv->mii);
681 priv->mii = NULL;
682
683 return 0;
684 }
685