1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2023 Linaro Ltd. 5 */ 6 #ifndef _GSI_REG_H_ 7 #define _GSI_REG_H_ 8 9 /* === Only "gsi.c" and "gsi_reg.c" should include this file === */ 10 11 #include <linux/bits.h> 12 13 /** 14 * DOC: GSI Registers 15 * 16 * GSI registers are located within the "gsi" address space defined by Device 17 * Tree. The offset of each register within that space is specified by 18 * symbols defined below. The GSI address space is mapped to virtual memory 19 * space in gsi_init(). All GSI registers are 32 bits wide. 20 * 21 * Each register type is duplicated for a number of instances of something. 22 * For example, each GSI channel has its own set of registers defining its 23 * configuration. The offset to a channel's set of registers is computed 24 * based on a "base" offset plus an additional "stride" amount computed 25 * from the channel's ID. For such registers, the offset is computed by a 26 * function-like macro that takes a parameter used in the computation. 27 * 28 * The offset of a register dependent on execution environment is computed 29 * by a macro that is supplied a parameter "ee". The "ee" value is a member 30 * of the gsi_ee_id enumerated type. 31 * 32 * The offset of a channel register is computed by a macro that is supplied a 33 * parameter "ch". The "ch" value is a channel id whose maximum value is 30 34 * (though the actual limit is hardware-dependent). 35 * 36 * The offset of an event register is computed by a macro that is supplied a 37 * parameter "ev". The "ev" value is an event id whose maximum value is 15 38 * (though the actual limit is hardware-dependent). 39 */ 40 41 /* enum gsi_reg_id - GSI register IDs */ 42 enum gsi_reg_id { 43 INTER_EE_SRC_CH_IRQ_MSK, /* IPA v3.5+ */ 44 INTER_EE_SRC_EV_CH_IRQ_MSK, /* IPA v3.5+ */ 45 CH_C_CNTXT_0, 46 CH_C_CNTXT_1, 47 CH_C_CNTXT_2, 48 CH_C_CNTXT_3, 49 CH_C_QOS, 50 CH_C_SCRATCH_0, 51 CH_C_SCRATCH_1, 52 CH_C_SCRATCH_2, 53 CH_C_SCRATCH_3, 54 EV_CH_E_CNTXT_0, 55 EV_CH_E_CNTXT_1, 56 EV_CH_E_CNTXT_2, 57 EV_CH_E_CNTXT_3, 58 EV_CH_E_CNTXT_4, 59 EV_CH_E_CNTXT_8, 60 EV_CH_E_CNTXT_9, 61 EV_CH_E_CNTXT_10, 62 EV_CH_E_CNTXT_11, 63 EV_CH_E_CNTXT_12, 64 EV_CH_E_CNTXT_13, 65 EV_CH_E_SCRATCH_0, 66 EV_CH_E_SCRATCH_1, 67 CH_C_DOORBELL_0, 68 EV_CH_E_DOORBELL_0, 69 GSI_STATUS, 70 CH_CMD, 71 EV_CH_CMD, 72 GENERIC_CMD, 73 HW_PARAM_2, /* IPA v3.5.1+ */ 74 HW_PARAM_4, /* IPA v5.0+ */ 75 CNTXT_TYPE_IRQ, 76 CNTXT_TYPE_IRQ_MSK, 77 CNTXT_SRC_CH_IRQ, 78 CNTXT_SRC_CH_IRQ_MSK, 79 CNTXT_SRC_CH_IRQ_CLR, 80 CNTXT_SRC_EV_CH_IRQ, 81 CNTXT_SRC_EV_CH_IRQ_MSK, 82 CNTXT_SRC_EV_CH_IRQ_CLR, 83 CNTXT_SRC_IEOB_IRQ, 84 CNTXT_SRC_IEOB_IRQ_MSK, 85 CNTXT_SRC_IEOB_IRQ_CLR, 86 CNTXT_GLOB_IRQ_STTS, 87 CNTXT_GLOB_IRQ_EN, 88 CNTXT_GLOB_IRQ_CLR, 89 CNTXT_GSI_IRQ_STTS, 90 CNTXT_GSI_IRQ_EN, 91 CNTXT_GSI_IRQ_CLR, 92 CNTXT_INTSET, 93 ERROR_LOG, 94 ERROR_LOG_CLR, 95 CNTXT_SCRATCH_0, 96 GSI_REG_ID_COUNT, /* Last; not an ID */ 97 }; 98 99 /* CH_C_CNTXT_0 register */ 100 enum gsi_reg_ch_c_cntxt_0_field_id { 101 CHTYPE_PROTOCOL, 102 CHTYPE_DIR, 103 CH_EE, 104 CHID, 105 CHTYPE_PROTOCOL_MSB, /* IPA v4.5-4.11 */ 106 ERINDEX, /* Not IPA v5.0+ */ 107 CHSTATE, 108 ELEMENT_SIZE, 109 }; 110 111 /** enum gsi_channel_type - CHTYPE_PROTOCOL field values in CH_C_CNTXT_0 */ 112 enum gsi_channel_type { 113 GSI_CHANNEL_TYPE_MHI = 0x0, 114 GSI_CHANNEL_TYPE_XHCI = 0x1, 115 GSI_CHANNEL_TYPE_GPI = 0x2, 116 GSI_CHANNEL_TYPE_XDCI = 0x3, 117 GSI_CHANNEL_TYPE_WDI2 = 0x4, 118 GSI_CHANNEL_TYPE_GCI = 0x5, 119 GSI_CHANNEL_TYPE_WDI3 = 0x6, 120 GSI_CHANNEL_TYPE_MHIP = 0x7, 121 GSI_CHANNEL_TYPE_AQC = 0x8, 122 GSI_CHANNEL_TYPE_11AD = 0x9, 123 }; 124 125 /* CH_C_CNTXT_1 register */ 126 enum gsi_reg_ch_c_cntxt_1_field_id { 127 CH_R_LENGTH, 128 CH_ERINDEX, /* IPA v5.0+ */ 129 }; 130 131 /* CH_C_QOS register */ 132 enum gsi_reg_ch_c_qos_field_id { 133 WRR_WEIGHT, 134 MAX_PREFETCH, 135 USE_DB_ENG, 136 USE_ESCAPE_BUF_ONLY, /* IPA v4.0-4.2 */ 137 PREFETCH_MODE, /* IPA v4.5+ */ 138 EMPTY_LVL_THRSHOLD, /* IPA v4.5+ */ 139 DB_IN_BYTES, /* IPA v4.9+ */ 140 LOW_LATENCY_EN, /* IPA v5.0+ */ 141 }; 142 143 /** enum gsi_prefetch_mode - PREFETCH_MODE field in CH_C_QOS */ 144 enum gsi_prefetch_mode { 145 USE_PREFETCH_BUFS = 0, 146 ESCAPE_BUF_ONLY = 1, 147 SMART_PREFETCH = 2, 148 FREE_PREFETCH = 3, 149 }; 150 151 /* EV_CH_E_CNTXT_0 register */ 152 enum gsi_reg_ch_c_ev_ch_e_cntxt_0_field_id { 153 EV_CHTYPE, /* enum gsi_channel_type */ 154 EV_EE, /* enum gsi_ee_id; always GSI_EE_AP for us */ 155 EV_EVCHID, 156 EV_INTYPE, 157 EV_CHSTATE, 158 EV_ELEMENT_SIZE, 159 }; 160 161 /* EV_CH_E_CNTXT_1 register */ 162 enum gsi_reg_ev_ch_c_cntxt_1_field_id { 163 R_LENGTH, 164 }; 165 166 /* EV_CH_E_CNTXT_8 register */ 167 enum gsi_reg_ch_c_ev_ch_e_cntxt_8_field_id { 168 EV_MODT, 169 EV_MODC, 170 EV_MOD_CNT, 171 }; 172 173 /* GSI_STATUS register */ 174 enum gsi_reg_gsi_status_field_id { 175 ENABLED, 176 }; 177 178 /* CH_CMD register */ 179 enum gsi_reg_gsi_ch_cmd_field_id { 180 CH_CHID, 181 CH_OPCODE, 182 }; 183 184 /** enum gsi_ch_cmd_opcode - CH_OPCODE field values in CH_CMD */ 185 enum gsi_ch_cmd_opcode { 186 GSI_CH_ALLOCATE = 0x0, 187 GSI_CH_START = 0x1, 188 GSI_CH_STOP = 0x2, 189 GSI_CH_RESET = 0x9, 190 GSI_CH_DE_ALLOC = 0xa, 191 GSI_CH_DB_STOP = 0xb, 192 }; 193 194 /* EV_CH_CMD register */ 195 enum gsi_ev_ch_cmd_field_id { 196 EV_CHID, 197 EV_OPCODE, 198 }; 199 200 /** enum gsi_evt_cmd_opcode - EV_OPCODE field values in EV_CH_CMD */ 201 enum gsi_evt_cmd_opcode { 202 GSI_EVT_ALLOCATE = 0x0, 203 GSI_EVT_RESET = 0x9, 204 GSI_EVT_DE_ALLOC = 0xa, 205 }; 206 207 /* GENERIC_CMD register */ 208 enum gsi_generic_cmd_field_id { 209 GENERIC_OPCODE, 210 GENERIC_CHID, 211 GENERIC_EE, 212 GENERIC_PARAMS, /* IPA v4.11+ */ 213 }; 214 215 /** enum gsi_generic_cmd_opcode - GENERIC_OPCODE field values in GENERIC_CMD */ 216 enum gsi_generic_cmd_opcode { 217 GSI_GENERIC_HALT_CHANNEL = 0x1, 218 GSI_GENERIC_ALLOCATE_CHANNEL = 0x2, 219 GSI_GENERIC_ENABLE_FLOW_CONTROL = 0x3, /* IPA v4.2+ */ 220 GSI_GENERIC_DISABLE_FLOW_CONTROL = 0x4, /* IPA v4.2+ */ 221 GSI_GENERIC_QUERY_FLOW_CONTROL = 0x5, /* IPA v4.11+ */ 222 }; 223 224 /* HW_PARAM_2 register */ /* IPA v3.5.1+ */ 225 enum gsi_hw_param_2_field_id { 226 IRAM_SIZE, 227 NUM_CH_PER_EE, 228 NUM_EV_PER_EE, /* Not IPA v5.0+ */ 229 GSI_CH_PEND_TRANSLATE, 230 GSI_CH_FULL_LOGIC, 231 GSI_USE_SDMA, /* IPA v4.0+ */ 232 GSI_SDMA_N_INT, /* IPA v4.0+ */ 233 GSI_SDMA_MAX_BURST, /* IPA v4.0+ */ 234 GSI_SDMA_N_IOVEC, /* IPA v4.0+ */ 235 GSI_USE_RD_WR_ENG, /* IPA v4.2+ */ 236 GSI_USE_INTER_EE, /* IPA v4.2+ */ 237 }; 238 239 /** enum gsi_iram_size - IRAM_SIZE field values in HW_PARAM_2 */ 240 enum gsi_iram_size { 241 IRAM_SIZE_ONE_KB = 0x0, 242 IRAM_SIZE_TWO_KB = 0x1, 243 /* The next two values are available for IPA v4.0 and above */ 244 IRAM_SIZE_TWO_N_HALF_KB = 0x2, 245 IRAM_SIZE_THREE_KB = 0x3, 246 /* The next two values are available for IPA v4.5 and above */ 247 IRAM_SIZE_THREE_N_HALF_KB = 0x4, 248 IRAM_SIZE_FOUR_KB = 0x5, 249 }; 250 251 /* HW_PARAM_4 register */ /* IPA v5.0+ */ 252 enum gsi_hw_param_4_field_id { 253 EV_PER_EE, 254 IRAM_PROTOCOL_COUNT, 255 }; 256 257 /** 258 * enum gsi_irq_type_id: GSI IRQ types 259 * @GSI_CH_CTRL: Channel allocation, deallocation, etc. 260 * @GSI_EV_CTRL: Event ring allocation, deallocation, etc. 261 * @GSI_GLOB_EE: Global/general event 262 * @GSI_IEOB: Transfer (TRE) completion 263 * @GSI_INTER_EE_CH_CTRL: Remote-issued stop/reset (unused) 264 * @GSI_INTER_EE_EV_CTRL: Remote-issued event reset (unused) 265 * @GSI_GENERAL: General hardware event (bus error, etc.) 266 */ 267 enum gsi_irq_type_id { 268 GSI_CH_CTRL = BIT(0), 269 GSI_EV_CTRL = BIT(1), 270 GSI_GLOB_EE = BIT(2), 271 GSI_IEOB = BIT(3), 272 GSI_INTER_EE_CH_CTRL = BIT(4), 273 GSI_INTER_EE_EV_CTRL = BIT(5), 274 GSI_GENERAL = BIT(6), 275 /* IRQ types 7-31 (and their bit values) are reserved */ 276 }; 277 278 /** enum gsi_global_irq_id: Global GSI interrupt events */ 279 enum gsi_global_irq_id { 280 ERROR_INT = BIT(0), 281 GP_INT1 = BIT(1), 282 GP_INT2 = BIT(2), 283 GP_INT3 = BIT(3), 284 /* Global IRQ types 4-31 (and their bit values) are reserved */ 285 }; 286 287 /** enum gsi_general_irq_id: GSI general IRQ conditions */ 288 enum gsi_general_irq_id { 289 BREAK_POINT = BIT(0), 290 BUS_ERROR = BIT(1), 291 CMD_FIFO_OVRFLOW = BIT(2), 292 MCS_STACK_OVRFLOW = BIT(3), 293 /* General IRQ types 4-31 (and their bit values) are reserved */ 294 }; 295 296 /* CNTXT_INTSET register */ 297 enum gsi_cntxt_intset_field_id { 298 INTYPE, 299 }; 300 301 /* ERROR_LOG register */ 302 enum gsi_error_log_field_id { 303 ERR_ARG3, 304 ERR_ARG2, 305 ERR_ARG1, 306 ERR_CODE, 307 ERR_VIRT_IDX, 308 ERR_TYPE, 309 ERR_EE, 310 }; 311 312 /** enum gsi_err_code - ERR_CODE field values in EE_ERR_LOG */ 313 enum gsi_err_code { 314 GSI_INVALID_TRE = 0x1, 315 GSI_OUT_OF_BUFFERS = 0x2, 316 GSI_OUT_OF_RESOURCES = 0x3, 317 GSI_UNSUPPORTED_INTER_EE_OP = 0x4, 318 GSI_EVT_RING_EMPTY = 0x5, 319 GSI_NON_ALLOCATED_EVT_ACCESS = 0x6, 320 /* 7 is not assigned */ 321 GSI_HWO_1 = 0x8, 322 }; 323 324 /** enum gsi_err_type - ERR_TYPE field values in EE_ERR_LOG */ 325 enum gsi_err_type { 326 GSI_ERR_TYPE_GLOB = 0x1, 327 GSI_ERR_TYPE_CHAN = 0x2, 328 GSI_ERR_TYPE_EVT = 0x3, 329 }; 330 331 /* CNTXT_SCRATCH_0 register */ 332 enum gsi_cntxt_scratch_0_field_id { 333 INTER_EE_RESULT, 334 GENERIC_EE_RESULT, 335 }; 336 337 /** enum gsi_generic_ee_result - GENERIC_EE_RESULT field values in SCRATCH_0 */ 338 enum gsi_generic_ee_result { 339 GENERIC_EE_SUCCESS = 0x1, 340 GENERIC_EE_INCORRECT_CHANNEL_STATE = 0x2, 341 GENERIC_EE_INCORRECT_DIRECTION = 0x3, 342 GENERIC_EE_INCORRECT_CHANNEL_TYPE = 0x4, 343 GENERIC_EE_INCORRECT_CHANNEL = 0x5, 344 GENERIC_EE_RETRY = 0x6, 345 GENERIC_EE_NO_RESOURCES = 0x7, 346 }; 347 348 extern const struct regs gsi_regs_v3_1; 349 extern const struct regs gsi_regs_v3_5_1; 350 extern const struct regs gsi_regs_v4_0; 351 extern const struct regs gsi_regs_v4_5; 352 extern const struct regs gsi_regs_v4_9; 353 extern const struct regs gsi_regs_v4_11; 354 355 /** 356 * gsi_reg() - Return the structure describing a GSI register 357 * @gsi: GSI pointer 358 * @reg_id: GSI register ID 359 */ 360 const struct reg *gsi_reg(struct gsi *gsi, enum gsi_reg_id reg_id); 361 362 /** 363 * gsi_reg_init() - Perform GSI register initialization 364 * @gsi: GSI pointer 365 * @pdev: GSI (IPA) platform device 366 * 367 * Initialize GSI registers, including looking up and I/O mapping 368 * the "gsi" memory space. 369 */ 370 int gsi_reg_init(struct gsi *gsi, struct platform_device *pdev); 371 372 /** 373 * gsi_reg_exit() - Inverse of gsi_reg_init() 374 * @gsi: GSI pointer 375 */ 376 void gsi_reg_exit(struct gsi *gsi); 377 378 #endif /* _GSI_REG_H_ */ 379