1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2014  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "../core.h"
6 #include "../pci.h"
7 #include "reg.h"
8 #include "def.h"
9 #include "phy.h"
10 #include "dm.h"
11 #include "hw.h"
12 #include "fw.h"
13 #include "trx.h"
14 #include "led.h"
15 #include "table.h"
16 
17 #include "../btcoexist/rtl_btc.h"
18 
19 #include <linux/vmalloc.h>
20 #include <linux/module.h>
21 
rtl92ee_init_aspm_vars(struct ieee80211_hw * hw)22 static void rtl92ee_init_aspm_vars(struct ieee80211_hw *hw)
23 {
24 	struct rtl_priv *rtlpriv = rtl_priv(hw);
25 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
26 
27 	/*close ASPM for AMD defaultly */
28 	rtlpci->const_amdpci_aspm = 0;
29 
30 	/**
31 	 * ASPM PS mode.
32 	 * 0 - Disable ASPM,
33 	 * 1 - Enable ASPM without Clock Req,
34 	 * 2 - Enable ASPM with Clock Req,
35 	 * 3 - Alwyas Enable ASPM with Clock Req,
36 	 * 4 - Always Enable ASPM without Clock Req.
37 	 * set defult to RTL8192CE:3 RTL8192E:2
38 	 */
39 	rtlpci->const_pci_aspm = 3;
40 
41 	/*Setting for PCI-E device */
42 	rtlpci->const_devicepci_aspm_setting = 0x03;
43 
44 	/*Setting for PCI-E bridge */
45 	rtlpci->const_hostpci_aspm_setting = 0x02;
46 
47 	/**
48 	 * In Hw/Sw Radio Off situation.
49 	 * 0 - Default,
50 	 * 1 - From ASPM setting without low Mac Pwr,
51 	 * 2 - From ASPM setting with low Mac Pwr,
52 	 * 3 - Bus D3
53 	 * set default to RTL8192CE:0 RTL8192SE:2
54 	 */
55 	rtlpci->const_hwsw_rfoff_d3 = 0;
56 
57 	/**
58 	 * This setting works for those device with
59 	 * backdoor ASPM setting such as EPHY setting.
60 	 * 0 - Not support ASPM,
61 	 * 1 - Support ASPM,
62 	 * 2 - According to chipset.
63 	 */
64 	rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
65 }
66 
rtl92ee_init_sw_vars(struct ieee80211_hw * hw)67 static int rtl92ee_init_sw_vars(struct ieee80211_hw *hw)
68 {
69 	struct rtl_priv *rtlpriv = rtl_priv(hw);
70 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
71 	int err = 0;
72 	char *fw_name;
73 
74 	rtl92ee_bt_reg_init(hw);
75 	rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
76 	rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
77 
78 	rtlpriv->dm.dm_initialgain_enable = true;
79 	rtlpriv->dm.dm_flag = 0;
80 	rtlpriv->dm.disable_framebursting = false;
81 	rtlpci->transmit_config = CFENDFORM | BIT(15);
82 
83 	/*just 2.4G band*/
84 	rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
85 	rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
86 	rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
87 
88 	rtlpci->receive_config = (RCR_APPFCS			|
89 				  RCR_APP_MIC			|
90 				  RCR_APP_ICV			|
91 				  RCR_APP_PHYST_RXFF		|
92 				  RCR_HTC_LOC_CTRL		|
93 				  RCR_AMF			|
94 				  RCR_ACF			|
95 				  RCR_ACRC32			|
96 				  RCR_AB			|
97 				  RCR_AM			|
98 				  RCR_APM			|
99 				  0);
100 
101 	rtlpci->irq_mask[0] = (u32)(IMR_PSTIMEOUT		|
102 				     IMR_C2HCMD			|
103 				     IMR_HIGHDOK		|
104 				     IMR_MGNTDOK		|
105 				     IMR_BKDOK			|
106 				     IMR_BEDOK			|
107 				     IMR_VIDOK			|
108 				     IMR_VODOK			|
109 				     IMR_RDU			|
110 				     IMR_ROK			|
111 				     0);
112 	rtlpci->irq_mask[1] = (u32)(IMR_RXFOVW | 0);
113 
114 	/* for LPS & IPS */
115 	rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
116 	rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
117 	rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
118 	rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
119 	if (rtlpriv->cfg->mod_params->disable_watchdog)
120 		pr_info("watchdog disabled\n");
121 	rtlpriv->psc.reg_fwctrl_lps = 3;
122 	rtlpriv->psc.reg_max_lps_awakeintvl = 5;
123 	/* for ASPM, you can close aspm through
124 	 * set const_support_pciaspm = 0
125 	 */
126 	rtl92ee_init_aspm_vars(hw);
127 
128 	if (rtlpriv->psc.reg_fwctrl_lps == 1)
129 		rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
130 	else if (rtlpriv->psc.reg_fwctrl_lps == 2)
131 		rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
132 	else if (rtlpriv->psc.reg_fwctrl_lps == 3)
133 		rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
134 
135 	/* for early mode */
136 	rtlpriv->rtlhal.earlymode_enable = false;
137 
138 	/*low power */
139 	rtlpriv->psc.low_power_enable = false;
140 
141 	/* for firmware buf */
142 	rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
143 	if (!rtlpriv->rtlhal.pfirmware) {
144 		pr_err("Can't alloc buffer for fw\n");
145 		return 1;
146 	}
147 
148 	/* request fw */
149 	fw_name = "rtlwifi/rtl8192eefw.bin";
150 
151 	rtlpriv->max_fw_size = 0x8000;
152 	pr_info("Using firmware %s\n", fw_name);
153 	err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
154 				      rtlpriv->io.dev, GFP_KERNEL, hw,
155 				      rtl_fw_cb);
156 	if (err) {
157 		pr_err("Failed to request firmware!\n");
158 		vfree(rtlpriv->rtlhal.pfirmware);
159 		rtlpriv->rtlhal.pfirmware = NULL;
160 		return 1;
161 	}
162 
163 	return 0;
164 }
165 
rtl92ee_deinit_sw_vars(struct ieee80211_hw * hw)166 static void rtl92ee_deinit_sw_vars(struct ieee80211_hw *hw)
167 {
168 	struct rtl_priv *rtlpriv = rtl_priv(hw);
169 
170 	if (rtlpriv->rtlhal.pfirmware) {
171 		vfree(rtlpriv->rtlhal.pfirmware);
172 		rtlpriv->rtlhal.pfirmware = NULL;
173 	}
174 }
175 
176 /* get bt coexist status */
rtl92ee_get_btc_status(void)177 static bool rtl92ee_get_btc_status(void)
178 {
179 	return true;
180 }
181 
182 static struct rtl_hal_ops rtl8192ee_hal_ops = {
183 	.init_sw_vars = rtl92ee_init_sw_vars,
184 	.deinit_sw_vars = rtl92ee_deinit_sw_vars,
185 	.read_eeprom_info = rtl92ee_read_eeprom_info,
186 	.interrupt_recognized = rtl92ee_interrupt_recognized,/*need check*/
187 	.hw_init = rtl92ee_hw_init,
188 	.hw_disable = rtl92ee_card_disable,
189 	.hw_suspend = rtl92ee_suspend,
190 	.hw_resume = rtl92ee_resume,
191 	.enable_interrupt = rtl92ee_enable_interrupt,
192 	.disable_interrupt = rtl92ee_disable_interrupt,
193 	.set_network_type = rtl92ee_set_network_type,
194 	.set_chk_bssid = rtl92ee_set_check_bssid,
195 	.set_qos = rtl92ee_set_qos,
196 	.set_bcn_reg = rtl92ee_set_beacon_related_registers,
197 	.set_bcn_intv = rtl92ee_set_beacon_interval,
198 	.update_interrupt_mask = rtl92ee_update_interrupt_mask,
199 	.get_hw_reg = rtl92ee_get_hw_reg,
200 	.set_hw_reg = rtl92ee_set_hw_reg,
201 	.update_rate_tbl = rtl92ee_update_hal_rate_tbl,
202 	.pre_fill_tx_bd_desc = rtl92ee_pre_fill_tx_bd_desc,
203 	.rx_desc_buff_remained_cnt = rtl92ee_rx_desc_buff_remained_cnt,
204 	.rx_check_dma_ok = rtl92ee_rx_check_dma_ok,
205 	.fill_tx_desc = rtl92ee_tx_fill_desc,
206 	.fill_tx_cmddesc = rtl92ee_tx_fill_cmddesc,
207 	.query_rx_desc = rtl92ee_rx_query_desc,
208 	.set_channel_access = rtl92ee_update_channel_access_setting,
209 	.radio_onoff_checking = rtl92ee_gpio_radio_on_off_checking,
210 	.set_bw_mode = rtl92ee_phy_set_bw_mode,
211 	.switch_channel = rtl92ee_phy_sw_chnl,
212 	.dm_watchdog = rtl92ee_dm_watchdog,
213 	.scan_operation_backup = rtl92ee_phy_scan_operation_backup,
214 	.set_rf_power_state = rtl92ee_phy_set_rf_power_state,
215 	.led_control = rtl92ee_led_control,
216 	.set_desc = rtl92ee_set_desc,
217 	.get_desc = rtl92ee_get_desc,
218 	.is_tx_desc_closed = rtl92ee_is_tx_desc_closed,
219 	.get_available_desc = rtl92ee_get_available_desc,
220 	.tx_polling = rtl92ee_tx_polling,
221 	.enable_hw_sec = rtl92ee_enable_hw_security_config,
222 	.set_key = rtl92ee_set_key,
223 	.init_sw_leds = rtl92ee_init_sw_leds,
224 	.get_bbreg = rtl92ee_phy_query_bb_reg,
225 	.set_bbreg = rtl92ee_phy_set_bb_reg,
226 	.get_rfreg = rtl92ee_phy_query_rf_reg,
227 	.set_rfreg = rtl92ee_phy_set_rf_reg,
228 	.fill_h2c_cmd = rtl92ee_fill_h2c_cmd,
229 	.get_btc_status = rtl92ee_get_btc_status,
230 	.c2h_ra_report_handler = rtl92ee_c2h_ra_report_handler,
231 };
232 
233 static struct rtl_mod_params rtl92ee_mod_params = {
234 	.sw_crypto = false,
235 	.inactiveps = true,
236 	.swctrl_lps = false,
237 	.fwctrl_lps = true,
238 	.msi_support = true,
239 	.dma64 = false,
240 	.aspm_support = 1,
241 	.debug_level = 0,
242 	.debug_mask = 0,
243 };
244 
245 static const struct rtl_hal_cfg rtl92ee_hal_cfg = {
246 	.bar_id = 2,
247 	.write_readback = true,
248 	.name = "rtl92ee_pci",
249 	.ops = &rtl8192ee_hal_ops,
250 	.mod_params = &rtl92ee_mod_params,
251 
252 	.maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
253 	.maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
254 	.maps[SYS_CLK] = REG_SYS_CLKR,
255 	.maps[MAC_RCR_AM] = AM,
256 	.maps[MAC_RCR_AB] = AB,
257 	.maps[MAC_RCR_ACRC32] = ACRC32,
258 	.maps[MAC_RCR_ACF] = ACF,
259 	.maps[MAC_RCR_AAP] = AAP,
260 	.maps[MAC_HIMR] = REG_HIMR,
261 	.maps[MAC_HIMRE] = REG_HIMRE,
262 
263 	.maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
264 
265 	.maps[EFUSE_TEST] = REG_EFUSE_TEST,
266 	.maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
267 	.maps[EFUSE_CLK] = 0,
268 	.maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
269 	.maps[EFUSE_PWC_EV12V] = PWC_EV12V,
270 	.maps[EFUSE_FEN_ELDR] = FEN_ELDR,
271 	.maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
272 	.maps[EFUSE_ANA8M] = ANA8M,
273 	.maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
274 	.maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
275 	.maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
276 	.maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
277 
278 	.maps[RWCAM] = REG_CAMCMD,
279 	.maps[WCAMI] = REG_CAMWRITE,
280 	.maps[RCAMO] = REG_CAMREAD,
281 	.maps[CAMDBG] = REG_CAMDBG,
282 	.maps[SECR] = REG_SECCFG,
283 	.maps[SEC_CAM_NONE] = CAM_NONE,
284 	.maps[SEC_CAM_WEP40] = CAM_WEP40,
285 	.maps[SEC_CAM_TKIP] = CAM_TKIP,
286 	.maps[SEC_CAM_AES] = CAM_AES,
287 	.maps[SEC_CAM_WEP104] = CAM_WEP104,
288 
289 	.maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
290 	.maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
291 	.maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
292 	.maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
293 	.maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
294 	.maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
295 	.maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
296 	.maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
297 	.maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
298 	.maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
299 	.maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
300 	.maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
301 	.maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
302 
303 	.maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
304 	.maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
305 	.maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
306 	.maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
307 	.maps[RTL_IMR_RDU] = IMR_RDU,
308 	.maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
309 	.maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
310 	.maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
311 	.maps[RTL_IMR_TBDER] = IMR_TBDER,
312 	.maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
313 	.maps[RTL_IMR_TBDOK] = IMR_TBDOK,
314 	.maps[RTL_IMR_BKDOK] = IMR_BKDOK,
315 	.maps[RTL_IMR_BEDOK] = IMR_BEDOK,
316 	.maps[RTL_IMR_VIDOK] = IMR_VIDOK,
317 	.maps[RTL_IMR_VODOK] = IMR_VODOK,
318 	.maps[RTL_IMR_ROK] = IMR_ROK,
319 	.maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
320 
321 	.maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
322 	.maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
323 	.maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
324 	.maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
325 	.maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
326 	.maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
327 	.maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
328 	.maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
329 	.maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
330 	.maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
331 	.maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
332 	.maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
333 
334 	.maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
335 	.maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
336 };
337 
338 static const struct pci_device_id rtl92ee_pci_ids[] = {
339 	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x818B, rtl92ee_hal_cfg)},
340 	{},
341 };
342 
343 MODULE_DEVICE_TABLE(pci, rtl92ee_pci_ids);
344 
345 MODULE_AUTHOR("Realtek WlanFAE	<wlanfae@realtek.com>");
346 MODULE_AUTHOR("Larry Finger	<Larry.Finger@lwfinger.net>");
347 MODULE_LICENSE("GPL");
348 MODULE_DESCRIPTION("Realtek 8192EE 802.11n PCI wireless");
349 MODULE_FIRMWARE("rtlwifi/rtl8192eefw.bin");
350 
351 module_param_named(swenc, rtl92ee_mod_params.sw_crypto, bool, 0444);
352 module_param_named(debug_level, rtl92ee_mod_params.debug_level, int, 0644);
353 module_param_named(debug_mask, rtl92ee_mod_params.debug_mask, ullong, 0644);
354 module_param_named(ips, rtl92ee_mod_params.inactiveps, bool, 0444);
355 module_param_named(swlps, rtl92ee_mod_params.swctrl_lps, bool, 0444);
356 module_param_named(fwlps, rtl92ee_mod_params.fwctrl_lps, bool, 0444);
357 module_param_named(msi, rtl92ee_mod_params.msi_support, bool, 0444);
358 module_param_named(dma64, rtl92ee_mod_params.dma64, bool, 0444);
359 module_param_named(aspm, rtl92ee_mod_params.aspm_support, int, 0444);
360 module_param_named(disable_watchdog, rtl92ee_mod_params.disable_watchdog,
361 		   bool, 0444);
362 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
363 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
364 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
365 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
366 MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
367 MODULE_PARM_DESC(dma64, "Set to 1 to use DMA 64 (default 0)\n");
368 MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
369 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
370 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
371 MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
372 
373 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
374 
375 static struct pci_driver rtl92ee_driver = {
376 	.name = KBUILD_MODNAME,
377 	.id_table = rtl92ee_pci_ids,
378 	.probe = rtl_pci_probe,
379 	.remove = rtl_pci_disconnect,
380 	.driver.pm = &rtlwifi_pm_ops,
381 };
382 
383 module_pci_driver(rtl92ee_driver);
384