1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_PHY_H__
6 #define __RTW89_PHY_H__
7
8 #include "core.h"
9
10 #define RTW89_PHY_ADDR_OFFSET 0x10000
11 #define RTW89_RF_ADDR_ADSEL_MASK BIT(16)
12
13 #define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr)
14 #define PHY_HEADLINE_VALID 0xf
15 #define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr)
16 #define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \
17 FIELD_PREP(GENMASK(7, 0), cv))
18
19 #define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr)
20 #define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr)
21 #define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr)
22 #define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr)
23 #define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; })
24 #define PHY_COND_BRANCH_IF 0x8
25 #define PHY_COND_BRANCH_ELIF 0x9
26 #define PHY_COND_BRANCH_ELSE 0xa
27 #define PHY_COND_BRANCH_END 0xb
28 #define PHY_COND_CHECK 0x4
29 #define PHY_COND_DONT_CARE 0xff
30
31 #define RA_MASK_CCK_RATES GENMASK_ULL(3, 0)
32 #define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4)
33 #define RA_MASK_SUBCCK_RATES 0x5ULL
34 #define RA_MASK_SUBOFDM_RATES 0x10ULL
35 #define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12)
36 #define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24)
37 #define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36)
38 #define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48)
39 #define RA_MASK_HT_RATES GENMASK_ULL(55, 12)
40 #define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12)
41 #define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24)
42 #define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36)
43 #define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48)
44 #define RA_MASK_VHT_RATES GENMASK_ULL(57, 12)
45 #define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12)
46 #define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24)
47 #define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36)
48 #define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48)
49 #define RA_MASK_HE_RATES GENMASK_ULL(59, 12)
50
51 #define CFO_TRK_ENABLE_TH (2 << 2)
52 #define CFO_TRK_STOP_TH_4 (30 << 2)
53 #define CFO_TRK_STOP_TH_3 (20 << 2)
54 #define CFO_TRK_STOP_TH_2 (10 << 2)
55 #define CFO_TRK_STOP_TH_1 (00 << 2)
56 #define CFO_TRK_STOP_TH (2 << 2)
57 #define CFO_SW_COMP_FINE_TUNE (2 << 2)
58 #define CFO_PERIOD_CNT 15
59 #define CFO_BOUND 64
60 #define CFO_TP_UPPER 100
61 #define CFO_TP_LOWER 50
62 #define CFO_COMP_PERIOD 250
63 #define CFO_COMP_WEIGHT 8
64 #define MAX_CFO_TOLERANCE 30
65 #define CFO_TF_CNT_TH 300
66
67 #define UL_TB_TF_CNT_L2H_TH 100
68 #define UL_TB_TF_CNT_H2L_TH 70
69
70 #define CCX_MAX_PERIOD 2097
71 #define CCX_MAX_PERIOD_UNIT 32
72 #define MS_TO_4US_RATIO 250
73 #define ENV_MNTR_FAIL_DWORD 0xffffffff
74 #define ENV_MNTR_IFSCLM_HIS_MAX 127
75 #define PERMIL 1000
76 #define PERCENT 100
77 #define IFS_CLM_TH0_UPPER 64
78 #define IFS_CLM_TH_MUL 4
79 #define IFS_CLM_TH_START_IDX 0
80
81 #define TIA0_GAIN_A 12
82 #define TIA0_GAIN_G 16
83 #define LNA0_GAIN (-24)
84 #define U4_MAX_BIT 3
85 #define U8_MAX_BIT 7
86 #define DIG_GAIN_SHIFT 2
87 #define DIG_GAIN 8
88
89 #define LNA_IDX_MAX 6
90 #define LNA_IDX_MIN 0
91 #define TIA_IDX_MAX 1
92 #define TIA_IDX_MIN 0
93 #define RXB_IDX_MAX 31
94 #define RXB_IDX_MIN 0
95
96 #define IGI_RSSI_MAX 110
97 #define PD_TH_MAX_RSSI 70
98 #define PD_TH_MIN_RSSI 8
99 #define CCKPD_TH_MIN_RSSI (-18)
100 #define PD_TH_BW160_CMP_VAL 9
101 #define PD_TH_BW80_CMP_VAL 6
102 #define PD_TH_BW40_CMP_VAL 3
103 #define PD_TH_BW20_CMP_VAL 0
104 #define PD_TH_CMP_VAL 3
105 #define PD_TH_SB_FLTR_CMP_VAL 7
106
107 #define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT)
108 #define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL)
109 #define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA)
110 #define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD)
111 #define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA)
112
113 enum rtw89_phy_c2h_ra_func {
114 RTW89_PHY_C2H_FUNC_STS_RPT,
115 RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT,
116 RTW89_PHY_C2H_FUNC_TXSTS,
117 RTW89_PHY_C2H_FUNC_RA_MAX,
118 };
119
120 enum rtw89_phy_c2h_dm_func {
121 RTW89_PHY_C2H_DM_FUNC_FW_TEST,
122 RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT,
123 RTW89_PHY_C2H_DM_FUNC_SIGB,
124 RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY,
125 RTW89_PHY_C2H_DM_FUNC_MCC_DIG,
126 RTW89_PHY_C2H_DM_FUNC_NUM,
127 };
128
129 enum rtw89_phy_c2h_class {
130 RTW89_PHY_C2H_CLASS_RUA,
131 RTW89_PHY_C2H_CLASS_RA,
132 RTW89_PHY_C2H_CLASS_DM,
133 RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10,
134 RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17,
135 RTW89_PHY_C2H_CLASS_MAX,
136 };
137
138 enum rtw89_env_monitor_result_level {
139 RTW89_PHY_ENV_MON_CCX_FAIL = 0,
140 RTW89_PHY_ENV_MON_NHM = BIT(0),
141 RTW89_PHY_ENV_MON_CLM = BIT(1),
142 RTW89_PHY_ENV_MON_FAHM = BIT(2),
143 RTW89_PHY_ENV_MON_IFS_CLM = BIT(3),
144 RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4),
145 };
146
147 #define CCX_US_BASE_RATIO 4
148 enum rtw89_ccx_unit {
149 RTW89_CCX_4_US = 0,
150 RTW89_CCX_8_US = 1,
151 RTW89_CCX_16_US = 2,
152 RTW89_CCX_32_US = 3
153 };
154
155 enum rtw89_phy_status_ie_type {
156 RTW89_PHYSTS_IE00_CMN_CCK = 0,
157 RTW89_PHYSTS_IE01_CMN_OFDM = 1,
158 RTW89_PHYSTS_IE02_CMN_EXT_AX = 2,
159 RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3,
160 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4,
161 RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5,
162 RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6,
163 RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7,
164 RTW89_PHYSTS_IE08_FTR_CH = 8,
165 RTW89_PHYSTS_IE09_FTR_0 = 9,
166 RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10,
167 RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11,
168 RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12,
169 RTW89_PHYSTS_IE13_DL_MU_DEF = 13,
170 RTW89_PHYSTS_IE14_TB_UL_CQI = 14,
171 RTW89_PHYSTS_IE15_TB_UL_DEF = 15,
172 RTW89_PHYSTS_IE16_RSVD16 = 16,
173 RTW89_PHYSTS_IE17_TB_UL_CTRL = 17,
174 RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18,
175 RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19,
176 RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20,
177 RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21,
178 RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22,
179 RTW89_PHYSTS_IE23_RSVD23 = 23,
180 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A = 24,
181 RTW89_PHYSTS_IE25_OFDM_TD_PATH_B = 25,
182 RTW89_PHYSTS_IE26_OFDM_TD_PATH_C = 26,
183 RTW89_PHYSTS_IE27_OFDM_TD_PATH_D = 27,
184 RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28,
185 RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29,
186 RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30,
187 RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31,
188
189 /* keep last */
190 RTW89_PHYSTS_IE_NUM,
191 RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1
192 };
193
194 enum rtw89_phy_status_bitmap {
195 RTW89_TD_SEARCH_FAIL = 0,
196 RTW89_BRK_BY_TX_PKT = 1,
197 RTW89_CCA_SPOOF = 2,
198 RTW89_OFDM_BRK = 3,
199 RTW89_CCK_BRK = 4,
200 RTW89_DL_MU_SPOOFING = 5,
201 RTW89_HE_MU = 6,
202 RTW89_VHT_MU = 7,
203 RTW89_UL_TB_SPOOFING = 8,
204 RTW89_RSVD_9 = 9,
205 RTW89_TRIG_BASE_PPDU = 10,
206 RTW89_CCK_PKT = 11,
207 RTW89_LEGACY_OFDM_PKT = 12,
208 RTW89_HT_PKT = 13,
209 RTW89_VHT_PKT = 14,
210 RTW89_HE_PKT = 15,
211
212 RTW89_PHYSTS_BITMAP_NUM
213 };
214
215 enum rtw89_dig_gain_type {
216 RTW89_DIG_GAIN_LNA_G = 0,
217 RTW89_DIG_GAIN_TIA_G = 1,
218 RTW89_DIG_GAIN_LNA_A = 2,
219 RTW89_DIG_GAIN_TIA_A = 3,
220 RTW89_DIG_GAIN_MAX = 4
221 };
222
223 enum rtw89_dig_gain_lna_idx {
224 RTW89_DIG_GAIN_LNA_IDX1 = 1,
225 RTW89_DIG_GAIN_LNA_IDX2 = 2,
226 RTW89_DIG_GAIN_LNA_IDX3 = 3,
227 RTW89_DIG_GAIN_LNA_IDX4 = 4,
228 RTW89_DIG_GAIN_LNA_IDX5 = 5,
229 RTW89_DIG_GAIN_LNA_IDX6 = 6
230 };
231
232 enum rtw89_dig_gain_tia_idx {
233 RTW89_DIG_GAIN_TIA_IDX0 = 0,
234 RTW89_DIG_GAIN_TIA_IDX1 = 1
235 };
236
237 enum rtw89_tssi_bandedge_cfg {
238 RTW89_TSSI_BANDEDGE_FLAT,
239 RTW89_TSSI_BANDEDGE_LOW,
240 RTW89_TSSI_BANDEDGE_MID,
241 RTW89_TSSI_BANDEDGE_HIGH,
242
243 RTW89_TSSI_CFG_NUM,
244 };
245
246 enum rtw89_tssi_sbw_idx {
247 RTW89_TSSI_SBW20,
248 RTW89_TSSI_SBW40_0,
249 RTW89_TSSI_SBW40_1,
250 RTW89_TSSI_SBW80_0,
251 RTW89_TSSI_SBW80_1,
252 RTW89_TSSI_SBW80_2,
253 RTW89_TSSI_SBW80_3,
254 RTW89_TSSI_SBW160_0,
255 RTW89_TSSI_SBW160_1,
256 RTW89_TSSI_SBW160_2,
257 RTW89_TSSI_SBW160_3,
258 RTW89_TSSI_SBW160_4,
259 RTW89_TSSI_SBW160_5,
260 RTW89_TSSI_SBW160_6,
261 RTW89_TSSI_SBW160_7,
262
263 RTW89_TSSI_SBW_NUM,
264 };
265
266 struct rtw89_txpwr_byrate_cfg {
267 enum rtw89_band band;
268 enum rtw89_nss nss;
269 enum rtw89_rate_section rs;
270 u8 shf;
271 u8 len;
272 u32 data;
273 };
274
275 #define DELTA_SWINGIDX_SIZE 30
276
277 struct rtw89_txpwr_track_cfg {
278 const s8 (*delta_swingidx_6gb_n)[DELTA_SWINGIDX_SIZE];
279 const s8 (*delta_swingidx_6gb_p)[DELTA_SWINGIDX_SIZE];
280 const s8 (*delta_swingidx_6ga_n)[DELTA_SWINGIDX_SIZE];
281 const s8 (*delta_swingidx_6ga_p)[DELTA_SWINGIDX_SIZE];
282 const s8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE];
283 const s8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE];
284 const s8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE];
285 const s8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE];
286 const s8 *delta_swingidx_2gb_n;
287 const s8 *delta_swingidx_2gb_p;
288 const s8 *delta_swingidx_2ga_n;
289 const s8 *delta_swingidx_2ga_p;
290 const s8 *delta_swingidx_2g_cck_b_n;
291 const s8 *delta_swingidx_2g_cck_b_p;
292 const s8 *delta_swingidx_2g_cck_a_n;
293 const s8 *delta_swingidx_2g_cck_a_p;
294 };
295
296 struct rtw89_phy_dig_gain_cfg {
297 const struct rtw89_reg_def *table;
298 u8 size;
299 };
300
301 struct rtw89_phy_dig_gain_table {
302 const struct rtw89_phy_dig_gain_cfg *cfg_lna_g;
303 const struct rtw89_phy_dig_gain_cfg *cfg_tia_g;
304 const struct rtw89_phy_dig_gain_cfg *cfg_lna_a;
305 const struct rtw89_phy_dig_gain_cfg *cfg_tia_a;
306 };
307
308 struct rtw89_phy_tssi_dbw_table {
309 u32 data[RTW89_TSSI_CFG_NUM][RTW89_TSSI_SBW_NUM];
310 };
311
312 struct rtw89_phy_reg3_tbl {
313 const struct rtw89_reg3_def *reg3;
314 int size;
315 };
316
317 #define DECLARE_PHY_REG3_TBL(_name) \
318 const struct rtw89_phy_reg3_tbl _name ## _tbl = { \
319 .reg3 = _name, \
320 .size = ARRAY_SIZE(_name), \
321 }
322
323 struct rtw89_nbi_reg_def {
324 struct rtw89_reg_def notch1_idx;
325 struct rtw89_reg_def notch1_frac_idx;
326 struct rtw89_reg_def notch1_en;
327 struct rtw89_reg_def notch2_idx;
328 struct rtw89_reg_def notch2_frac_idx;
329 struct rtw89_reg_def notch2_en;
330 };
331
rtw89_phy_write8(struct rtw89_dev * rtwdev,u32 addr,u8 data)332 static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev,
333 u32 addr, u8 data)
334 {
335 rtw89_write8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data);
336 }
337
rtw89_phy_write16(struct rtw89_dev * rtwdev,u32 addr,u16 data)338 static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev,
339 u32 addr, u16 data)
340 {
341 rtw89_write16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data);
342 }
343
rtw89_phy_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data)344 static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev,
345 u32 addr, u32 data)
346 {
347 rtw89_write32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data);
348 }
349
rtw89_phy_write32_set(struct rtw89_dev * rtwdev,u32 addr,u32 bits)350 static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev,
351 u32 addr, u32 bits)
352 {
353 rtw89_write32_set(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits);
354 }
355
rtw89_phy_write32_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bits)356 static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev,
357 u32 addr, u32 bits)
358 {
359 rtw89_write32_clr(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits);
360 }
361
rtw89_phy_write32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data)362 static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev,
363 u32 addr, u32 mask, u32 data)
364 {
365 rtw89_write32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask, data);
366 }
367
rtw89_phy_read8(struct rtw89_dev * rtwdev,u32 addr)368 static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr)
369 {
370 return rtw89_read8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET);
371 }
372
rtw89_phy_read16(struct rtw89_dev * rtwdev,u32 addr)373 static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr)
374 {
375 return rtw89_read16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET);
376 }
377
rtw89_phy_read32(struct rtw89_dev * rtwdev,u32 addr)378 static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr)
379 {
380 return rtw89_read32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET);
381 }
382
rtw89_phy_read32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)383 static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev,
384 u32 addr, u32 mask)
385 {
386 return rtw89_read32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask);
387 }
388
389 static inline
rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband)390 enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband)
391 {
392 switch (subband) {
393 default:
394 case RTW89_CH_2G:
395 return RTW89_GAIN_OFFSET_2G_OFDM;
396 case RTW89_CH_5G_BAND_1:
397 return RTW89_GAIN_OFFSET_5G_LOW;
398 case RTW89_CH_5G_BAND_3:
399 return RTW89_GAIN_OFFSET_5G_MID;
400 case RTW89_CH_5G_BAND_4:
401 return RTW89_GAIN_OFFSET_5G_HIGH;
402 }
403 }
404
405 static inline
rtw89_subband_to_bb_gain_band(enum rtw89_subband subband)406 enum rtw89_phy_bb_gain_band rtw89_subband_to_bb_gain_band(enum rtw89_subband subband)
407 {
408 switch (subband) {
409 default:
410 case RTW89_CH_2G:
411 return RTW89_BB_GAIN_BAND_2G;
412 case RTW89_CH_5G_BAND_1:
413 return RTW89_BB_GAIN_BAND_5G_L;
414 case RTW89_CH_5G_BAND_3:
415 return RTW89_BB_GAIN_BAND_5G_M;
416 case RTW89_CH_5G_BAND_4:
417 return RTW89_BB_GAIN_BAND_5G_H;
418 case RTW89_CH_6G_BAND_IDX0:
419 case RTW89_CH_6G_BAND_IDX1:
420 return RTW89_BB_GAIN_BAND_6G_L;
421 case RTW89_CH_6G_BAND_IDX2:
422 case RTW89_CH_6G_BAND_IDX3:
423 return RTW89_BB_GAIN_BAND_6G_M;
424 case RTW89_CH_6G_BAND_IDX4:
425 case RTW89_CH_6G_BAND_IDX5:
426 return RTW89_BB_GAIN_BAND_6G_H;
427 case RTW89_CH_6G_BAND_IDX6:
428 case RTW89_CH_6G_BAND_IDX7:
429 return RTW89_BB_GAIN_BAND_6G_UH;
430 }
431 }
432
433 enum rtw89_rfk_flag {
434 RTW89_RFK_F_WRF = 0,
435 RTW89_RFK_F_WM = 1,
436 RTW89_RFK_F_WS = 2,
437 RTW89_RFK_F_WC = 3,
438 RTW89_RFK_F_DELAY = 4,
439 RTW89_RFK_F_NUM,
440 };
441
442 struct rtw89_rfk_tbl {
443 const struct rtw89_reg5_def *defs;
444 u32 size;
445 };
446
447 #define RTW89_DECLARE_RFK_TBL(_name) \
448 const struct rtw89_rfk_tbl _name ## _tbl = { \
449 .defs = _name, \
450 .size = ARRAY_SIZE(_name), \
451 }
452
453 #define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data) \
454 {.flag = RTW89_RFK_F_WRF, \
455 .path = _path, \
456 .addr = _addr, \
457 .mask = _mask, \
458 .data = _data,}
459
460 #define RTW89_DECL_RFK_WM(_addr, _mask, _data) \
461 {.flag = RTW89_RFK_F_WM, \
462 .addr = _addr, \
463 .mask = _mask, \
464 .data = _data,}
465
466 #define RTW89_DECL_RFK_WS(_addr, _mask) \
467 {.flag = RTW89_RFK_F_WS, \
468 .addr = _addr, \
469 .mask = _mask,}
470
471 #define RTW89_DECL_RFK_WC(_addr, _mask) \
472 {.flag = RTW89_RFK_F_WC, \
473 .addr = _addr, \
474 .mask = _mask,}
475
476 #define RTW89_DECL_RFK_DELAY(_data) \
477 {.flag = RTW89_RFK_F_DELAY, \
478 .data = _data,}
479
480 void
481 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl);
482
483 #define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f) \
484 do { \
485 typeof(dev) __dev = (dev); \
486 if (cond) \
487 rtw89_rfk_parser(__dev, (tbl_t)); \
488 else \
489 rtw89_rfk_parser(__dev, (tbl_f)); \
490 } while (0)
491
492 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
493 const struct rtw89_phy_reg3_tbl *tbl);
494 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
495 const struct rtw89_chan *chan,
496 enum rtw89_bandwidth dbw);
497 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
498 u32 addr, u32 mask);
499 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
500 u32 addr, u32 mask);
501 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
502 u32 addr, u32 mask, u32 data);
503 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
504 u32 addr, u32 mask, u32 data);
505 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev);
506 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio);
507 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
508 const struct rtw89_reg2_def *reg,
509 enum rtw89_rf_path rf_path,
510 void *extra_data);
511 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev);
512 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
513 u32 data, enum rtw89_phy_idx phy_idx);
514 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
515 enum rtw89_phy_idx phy_idx);
516 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
517 const struct rtw89_txpwr_table *tbl);
518 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
519 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch);
520 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev,
521 const struct rtw89_chan *chan,
522 enum rtw89_phy_idx phy_idx);
523 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev,
524 const struct rtw89_chan *chan,
525 enum rtw89_phy_idx phy_idx);
526 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev,
527 const struct rtw89_chan *chan,
528 enum rtw89_phy_idx phy_idx);
529 void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,
530 const struct rtw89_chan *chan,
531 enum rtw89_phy_idx phy_idx);
532 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta);
533 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev);
534 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,
535 u32 changed);
536 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
537 struct ieee80211_vif *vif,
538 const struct cfg80211_bitrate_mask *mask);
539 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
540 u32 len, u8 class, u8 func);
541 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev);
542 void rtw89_phy_cfo_track_work(struct work_struct *work);
543 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
544 struct rtw89_rx_phy_ppdu *phy_ppdu);
545 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev);
546 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev);
547 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
548 u32 val);
549 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev);
550 void rtw89_phy_dig(struct rtw89_dev *rtwdev);
551 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev);
552 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
553 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
554 enum rtw89_mac_idx mac_idx,
555 enum rtw89_tssi_bandedge_cfg bandedge_cfg);
556 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
557 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev);
558
559 #endif
560