1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Intel IXP4xx Network Processor Engine driver for Linux
4  *
5  * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
6  *
7  * The code is based on publicly available information:
8  * - Intel IXP4xx Developer's Manual and other e-papers
9  * - Intel IXP400 Access Library Software (BSD license)
10  * - previous works by Christian Hohnstaedt <chohnstaedt@innominate.com>
11  *   Thanks, Christian.
12  */
13 
14 #include <linux/delay.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/firmware.h>
17 #include <linux/io.h>
18 #include <linux/kernel.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/of_platform.h>
23 #include <linux/platform_device.h>
24 #include <linux/soc/ixp4xx/npe.h>
25 #include <linux/soc/ixp4xx/cpu.h>
26 
27 #define DEBUG_MSG			0
28 #define DEBUG_FW			0
29 
30 #define NPE_COUNT			3
31 #define MAX_RETRIES			1000	/* microseconds */
32 #define NPE_42X_DATA_SIZE		0x800	/* in dwords */
33 #define NPE_46X_DATA_SIZE		0x1000
34 #define NPE_A_42X_INSTR_SIZE		0x1000
35 #define NPE_B_AND_C_42X_INSTR_SIZE	0x800
36 #define NPE_46X_INSTR_SIZE		0x1000
37 #define REGS_SIZE			0x1000
38 
39 #define NPE_PHYS_REG			32
40 
41 #define FW_MAGIC			0xFEEDF00D
42 #define FW_BLOCK_TYPE_INSTR		0x0
43 #define FW_BLOCK_TYPE_DATA		0x1
44 #define FW_BLOCK_TYPE_EOF		0xF
45 
46 /* NPE exec status (read) and command (write) */
47 #define CMD_NPE_STEP			0x01
48 #define CMD_NPE_START			0x02
49 #define CMD_NPE_STOP			0x03
50 #define CMD_NPE_CLR_PIPE		0x04
51 #define CMD_CLR_PROFILE_CNT		0x0C
52 #define CMD_RD_INS_MEM			0x10 /* instruction memory */
53 #define CMD_WR_INS_MEM			0x11
54 #define CMD_RD_DATA_MEM			0x12 /* data memory */
55 #define CMD_WR_DATA_MEM			0x13
56 #define CMD_RD_ECS_REG			0x14 /* exec access register */
57 #define CMD_WR_ECS_REG			0x15
58 
59 #define STAT_RUN			0x80000000
60 #define STAT_STOP			0x40000000
61 #define STAT_CLEAR			0x20000000
62 #define STAT_ECS_K			0x00800000 /* pipeline clean */
63 
64 #define NPE_STEVT			0x1B
65 #define NPE_STARTPC			0x1C
66 #define NPE_REGMAP			0x1E
67 #define NPE_CINDEX			0x1F
68 
69 #define INSTR_WR_REG_SHORT		0x0000C000
70 #define INSTR_WR_REG_BYTE		0x00004000
71 #define INSTR_RD_FIFO			0x0F888220
72 #define INSTR_RESET_MBOX		0x0FAC8210
73 
74 #define ECS_BG_CTXT_REG_0		0x00 /* Background Executing Context */
75 #define ECS_BG_CTXT_REG_1		0x01 /*		Stack level */
76 #define ECS_BG_CTXT_REG_2		0x02
77 #define ECS_PRI_1_CTXT_REG_0		0x04 /* Priority 1 Executing Context */
78 #define ECS_PRI_1_CTXT_REG_1		0x05 /*		Stack level */
79 #define ECS_PRI_1_CTXT_REG_2		0x06
80 #define ECS_PRI_2_CTXT_REG_0		0x08 /* Priority 2 Executing Context */
81 #define ECS_PRI_2_CTXT_REG_1		0x09 /*		Stack level */
82 #define ECS_PRI_2_CTXT_REG_2		0x0A
83 #define ECS_DBG_CTXT_REG_0		0x0C /* Debug Executing Context */
84 #define ECS_DBG_CTXT_REG_1		0x0D /*		Stack level */
85 #define ECS_DBG_CTXT_REG_2		0x0E
86 #define ECS_INSTRUCT_REG		0x11 /* NPE Instruction Register */
87 
88 #define ECS_REG_0_ACTIVE		0x80000000 /* all levels */
89 #define ECS_REG_0_NEXTPC_MASK		0x1FFF0000 /* BG/PRI1/PRI2 levels */
90 #define ECS_REG_0_LDUR_BITS		8
91 #define ECS_REG_0_LDUR_MASK		0x00000700 /* all levels */
92 #define ECS_REG_1_CCTXT_BITS		16
93 #define ECS_REG_1_CCTXT_MASK		0x000F0000 /* all levels */
94 #define ECS_REG_1_SELCTXT_BITS		0
95 #define ECS_REG_1_SELCTXT_MASK		0x0000000F /* all levels */
96 #define ECS_DBG_REG_2_IF		0x00100000 /* debug level */
97 #define ECS_DBG_REG_2_IE		0x00080000 /* debug level */
98 
99 /* NPE watchpoint_fifo register bit */
100 #define WFIFO_VALID			0x80000000
101 
102 /* NPE messaging_status register bit definitions */
103 #define MSGSTAT_OFNE	0x00010000 /* OutFifoNotEmpty */
104 #define MSGSTAT_IFNF	0x00020000 /* InFifoNotFull */
105 #define MSGSTAT_OFNF	0x00040000 /* OutFifoNotFull */
106 #define MSGSTAT_IFNE	0x00080000 /* InFifoNotEmpty */
107 #define MSGSTAT_MBINT	0x00100000 /* Mailbox interrupt */
108 #define MSGSTAT_IFINT	0x00200000 /* InFifo interrupt */
109 #define MSGSTAT_OFINT	0x00400000 /* OutFifo interrupt */
110 #define MSGSTAT_WFINT	0x00800000 /* WatchFifo interrupt */
111 
112 /* NPE messaging_control register bit definitions */
113 #define MSGCTL_OUT_FIFO			0x00010000 /* enable output FIFO */
114 #define MSGCTL_IN_FIFO			0x00020000 /* enable input FIFO */
115 #define MSGCTL_OUT_FIFO_WRITE		0x01000000 /* enable FIFO + WRITE */
116 #define MSGCTL_IN_FIFO_WRITE		0x02000000
117 
118 /* NPE mailbox_status value for reset */
119 #define RESET_MBOX_STAT			0x0000F0F0
120 
121 #define NPE_A_FIRMWARE "NPE-A"
122 #define NPE_B_FIRMWARE "NPE-B"
123 #define NPE_C_FIRMWARE "NPE-C"
124 
125 const char *npe_names[] = { NPE_A_FIRMWARE, NPE_B_FIRMWARE, NPE_C_FIRMWARE };
126 
127 #define print_npe(pri, npe, fmt, ...)					\
128 	printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__)
129 
130 #if DEBUG_MSG
131 #define debug_msg(npe, fmt, ...)					\
132 	print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__)
133 #else
134 #define debug_msg(npe, fmt, ...)
135 #endif
136 
137 static struct {
138 	u32 reg, val;
139 } ecs_reset[] = {
140 	{ ECS_BG_CTXT_REG_0,	0xA0000000 },
141 	{ ECS_BG_CTXT_REG_1,	0x01000000 },
142 	{ ECS_BG_CTXT_REG_2,	0x00008000 },
143 	{ ECS_PRI_1_CTXT_REG_0,	0x20000080 },
144 	{ ECS_PRI_1_CTXT_REG_1,	0x01000000 },
145 	{ ECS_PRI_1_CTXT_REG_2,	0x00008000 },
146 	{ ECS_PRI_2_CTXT_REG_0,	0x20000080 },
147 	{ ECS_PRI_2_CTXT_REG_1,	0x01000000 },
148 	{ ECS_PRI_2_CTXT_REG_2,	0x00008000 },
149 	{ ECS_DBG_CTXT_REG_0,	0x20000000 },
150 	{ ECS_DBG_CTXT_REG_1,	0x00000000 },
151 	{ ECS_DBG_CTXT_REG_2,	0x001E0000 },
152 	{ ECS_INSTRUCT_REG,	0x1003C00F },
153 };
154 
155 static struct npe npe_tab[NPE_COUNT] = {
156 	{
157 		.id	= 0,
158 	}, {
159 		.id	= 1,
160 	}, {
161 		.id	= 2,
162 	}
163 };
164 
npe_running(struct npe * npe)165 int npe_running(struct npe *npe)
166 {
167 	return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0;
168 }
169 
npe_cmd_write(struct npe * npe,u32 addr,int cmd,u32 data)170 static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data)
171 {
172 	__raw_writel(data, &npe->regs->exec_data);
173 	__raw_writel(addr, &npe->regs->exec_addr);
174 	__raw_writel(cmd, &npe->regs->exec_status_cmd);
175 }
176 
npe_cmd_read(struct npe * npe,u32 addr,int cmd)177 static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd)
178 {
179 	__raw_writel(addr, &npe->regs->exec_addr);
180 	__raw_writel(cmd, &npe->regs->exec_status_cmd);
181 	/* Iintroduce extra read cycles after issuing read command to NPE
182 	   so that we read the register after the NPE has updated it.
183 	   This is to overcome race condition between XScale and NPE */
184 	__raw_readl(&npe->regs->exec_data);
185 	__raw_readl(&npe->regs->exec_data);
186 	return __raw_readl(&npe->regs->exec_data);
187 }
188 
npe_clear_active(struct npe * npe,u32 reg)189 static void npe_clear_active(struct npe *npe, u32 reg)
190 {
191 	u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG);
192 	npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE);
193 }
194 
npe_start(struct npe * npe)195 static void npe_start(struct npe *npe)
196 {
197 	/* ensure only Background Context Stack Level is active */
198 	npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0);
199 	npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0);
200 	npe_clear_active(npe, ECS_DBG_CTXT_REG_0);
201 
202 	__raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
203 	__raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd);
204 }
205 
npe_stop(struct npe * npe)206 static void npe_stop(struct npe *npe)
207 {
208 	__raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd);
209 	__raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/
210 }
211 
npe_debug_instr(struct npe * npe,u32 instr,u32 ctx,u32 ldur)212 static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx,
213 					u32 ldur)
214 {
215 	u32 wc;
216 	int i;
217 
218 	/* set the Active bit, and the LDUR, in the debug level */
219 	npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG,
220 		      ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS));
221 
222 	/* set CCTXT at ECS DEBUG L3 to specify in which context to execute
223 	   the instruction, and set SELCTXT at ECS DEBUG Level to specify
224 	   which context store to access.
225 	   Debug ECS Level Reg 1 has form 0x000n000n, where n = context number
226 	*/
227 	npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG,
228 		      (ctx << ECS_REG_1_CCTXT_BITS) |
229 		      (ctx << ECS_REG_1_SELCTXT_BITS));
230 
231 	/* clear the pipeline */
232 	__raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
233 
234 	/* load NPE instruction into the instruction register */
235 	npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr);
236 
237 	/* we need this value later to wait for completion of NPE execution
238 	   step */
239 	wc = __raw_readl(&npe->regs->watch_count);
240 
241 	/* issue a Step One command via the Execution Control register */
242 	__raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd);
243 
244 	/* Watch Count register increments when NPE completes an instruction */
245 	for (i = 0; i < MAX_RETRIES; i++) {
246 		if (wc != __raw_readl(&npe->regs->watch_count))
247 			return 0;
248 		udelay(1);
249 	}
250 
251 	print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n");
252 	return -ETIMEDOUT;
253 }
254 
npe_logical_reg_write8(struct npe * npe,u32 addr,u8 val,u32 ctx)255 static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr,
256 					       u8 val, u32 ctx)
257 {
258 	/* here we build the NPE assembler instruction: mov8 d0, #0 */
259 	u32 instr = INSTR_WR_REG_BYTE |	/* OpCode */
260 		addr << 9 |		/* base Operand */
261 		(val & 0x1F) << 4 |	/* lower 5 bits to immediate data */
262 		(val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */
263 	return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
264 }
265 
npe_logical_reg_write16(struct npe * npe,u32 addr,u16 val,u32 ctx)266 static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr,
267 						u16 val, u32 ctx)
268 {
269 	/* here we build the NPE assembler instruction: mov16 d0, #0 */
270 	u32 instr = INSTR_WR_REG_SHORT | /* OpCode */
271 		addr << 9 |		/* base Operand */
272 		(val & 0x1F) << 4 |	/* lower 5 bits to immediate data */
273 		(val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */
274 	return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
275 }
276 
npe_logical_reg_write32(struct npe * npe,u32 addr,u32 val,u32 ctx)277 static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr,
278 						u32 val, u32 ctx)
279 {
280 	/* write in 16 bit steps first the high and then the low value */
281 	if (npe_logical_reg_write16(npe, addr, val >> 16, ctx))
282 		return -ETIMEDOUT;
283 	return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx);
284 }
285 
npe_reset(struct npe * npe)286 static int npe_reset(struct npe *npe)
287 {
288 	u32 reset_bit = (IXP4XX_FEATURE_RESET_NPEA << npe->id);
289 	u32 val, ctl, exec_count, ctx_reg2;
290 	int i;
291 
292 	ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) &
293 		0x3F3FFFFF;
294 
295 	/* disable parity interrupt */
296 	__raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control);
297 
298 	/* pre exec - debug instruction */
299 	/* turn off the halt bit by clearing Execution Count register. */
300 	exec_count = __raw_readl(&npe->regs->exec_count);
301 	__raw_writel(0, &npe->regs->exec_count);
302 	/* ensure that IF and IE are on (temporarily), so that we don't end up
303 	   stepping forever */
304 	ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG);
305 	npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 |
306 		      ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE);
307 
308 	/* clear the FIFOs */
309 	while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID)
310 		;
311 	while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE)
312 		/* read from the outFIFO until empty */
313 		print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n",
314 			  __raw_readl(&npe->regs->in_out_fifo));
315 
316 	while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)
317 		/* step execution of the NPE intruction to read inFIFO using
318 		   the Debug Executing Context stack */
319 		if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0))
320 			return -ETIMEDOUT;
321 
322 	/* reset the mailbox reg from the XScale side */
323 	__raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status);
324 	/* from NPE side */
325 	if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0))
326 		return -ETIMEDOUT;
327 
328 	/* Reset the physical registers in the NPE register file */
329 	for (val = 0; val < NPE_PHYS_REG; val++) {
330 		if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0))
331 			return -ETIMEDOUT;
332 		/* address is either 0 or 4 */
333 		if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0))
334 			return -ETIMEDOUT;
335 	}
336 
337 	/* Reset the context store = each context's Context Store registers */
338 
339 	/* Context 0 has no STARTPC. Instead, this value is used to set NextPC
340 	   for Background ECS, to set where NPE starts executing code */
341 	val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG);
342 	val &= ~ECS_REG_0_NEXTPC_MASK;
343 	val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK;
344 	npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val);
345 
346 	for (i = 0; i < 16; i++) {
347 		if (i) {	/* Context 0 has no STEVT nor STARTPC */
348 			/* STEVT = off, 0x80 */
349 			if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i))
350 				return -ETIMEDOUT;
351 			if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i))
352 				return -ETIMEDOUT;
353 		}
354 		/* REGMAP = d0->p0, d8->p2, d16->p4 */
355 		if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i))
356 			return -ETIMEDOUT;
357 		if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i))
358 			return -ETIMEDOUT;
359 	}
360 
361 	/* post exec */
362 	/* clear active bit in debug level */
363 	npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0);
364 	/* clear the pipeline */
365 	__raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
366 	/* restore previous values */
367 	__raw_writel(exec_count, &npe->regs->exec_count);
368 	npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2);
369 
370 	/* write reset values to Execution Context Stack registers */
371 	for (val = 0; val < ARRAY_SIZE(ecs_reset); val++)
372 		npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG,
373 			      ecs_reset[val].val);
374 
375 	/* clear the profile counter */
376 	__raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd);
377 
378 	__raw_writel(0, &npe->regs->exec_count);
379 	__raw_writel(0, &npe->regs->action_points[0]);
380 	__raw_writel(0, &npe->regs->action_points[1]);
381 	__raw_writel(0, &npe->regs->action_points[2]);
382 	__raw_writel(0, &npe->regs->action_points[3]);
383 	__raw_writel(0, &npe->regs->watch_count);
384 
385 	/*
386 	 * We need to work on cached values here because the register
387 	 * will read inverted but needs to be written non-inverted.
388 	 */
389 	val = cpu_ixp4xx_features(npe->rmap);
390 	/* reset the NPE */
391 	regmap_write(npe->rmap, IXP4XX_EXP_CNFG2, val & ~reset_bit);
392 	/* deassert reset */
393 	regmap_write(npe->rmap, IXP4XX_EXP_CNFG2, val | reset_bit);
394 
395 	for (i = 0; i < MAX_RETRIES; i++) {
396 		val = cpu_ixp4xx_features(npe->rmap);
397 		if (val & reset_bit)
398 			break;	/* NPE is back alive */
399 		udelay(1);
400 	}
401 	if (i == MAX_RETRIES)
402 		return -ETIMEDOUT;
403 
404 	npe_stop(npe);
405 
406 	/* restore NPE configuration bus Control Register - parity settings */
407 	__raw_writel(ctl, &npe->regs->messaging_control);
408 	return 0;
409 }
410 
411 
npe_send_message(struct npe * npe,const void * msg,const char * what)412 int npe_send_message(struct npe *npe, const void *msg, const char *what)
413 {
414 	const u32 *send = msg;
415 	int cycles = 0;
416 
417 	debug_msg(npe, "Trying to send message %s [%08X:%08X]\n",
418 		  what, send[0], send[1]);
419 
420 	if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) {
421 		debug_msg(npe, "NPE input FIFO not empty\n");
422 		return -EIO;
423 	}
424 
425 	__raw_writel(send[0], &npe->regs->in_out_fifo);
426 
427 	if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) {
428 		debug_msg(npe, "NPE input FIFO full\n");
429 		return -EIO;
430 	}
431 
432 	__raw_writel(send[1], &npe->regs->in_out_fifo);
433 
434 	while ((cycles < MAX_RETRIES) &&
435 	       (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) {
436 		udelay(1);
437 		cycles++;
438 	}
439 
440 	if (cycles == MAX_RETRIES) {
441 		debug_msg(npe, "Timeout sending message\n");
442 		return -ETIMEDOUT;
443 	}
444 
445 #if DEBUG_MSG > 1
446 	debug_msg(npe, "Sending a message took %i cycles\n", cycles);
447 #endif
448 	return 0;
449 }
450 
npe_recv_message(struct npe * npe,void * msg,const char * what)451 int npe_recv_message(struct npe *npe, void *msg, const char *what)
452 {
453 	u32 *recv = msg;
454 	int cycles = 0, cnt = 0;
455 
456 	debug_msg(npe, "Trying to receive message %s\n", what);
457 
458 	while (cycles < MAX_RETRIES) {
459 		if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) {
460 			recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo);
461 			if (cnt == 2)
462 				break;
463 		} else {
464 			udelay(1);
465 			cycles++;
466 		}
467 	}
468 
469 	switch(cnt) {
470 	case 1:
471 		debug_msg(npe, "Received [%08X]\n", recv[0]);
472 		break;
473 	case 2:
474 		debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]);
475 		break;
476 	}
477 
478 	if (cycles == MAX_RETRIES) {
479 		debug_msg(npe, "Timeout waiting for message\n");
480 		return -ETIMEDOUT;
481 	}
482 
483 #if DEBUG_MSG > 1
484 	debug_msg(npe, "Receiving a message took %i cycles\n", cycles);
485 #endif
486 	return 0;
487 }
488 
npe_send_recv_message(struct npe * npe,void * msg,const char * what)489 int npe_send_recv_message(struct npe *npe, void *msg, const char *what)
490 {
491 	int result;
492 	u32 *send = msg, recv[2];
493 
494 	if ((result = npe_send_message(npe, msg, what)) != 0)
495 		return result;
496 	if ((result = npe_recv_message(npe, recv, what)) != 0)
497 		return result;
498 
499 	if ((recv[0] != send[0]) || (recv[1] != send[1])) {
500 		debug_msg(npe, "Message %s: unexpected message received\n",
501 			  what);
502 		return -EIO;
503 	}
504 	return 0;
505 }
506 
507 
npe_load_firmware(struct npe * npe,const char * name,struct device * dev)508 int npe_load_firmware(struct npe *npe, const char *name, struct device *dev)
509 {
510 	const struct firmware *fw_entry;
511 
512 	struct dl_block {
513 		u32 type;
514 		u32 offset;
515 	} *blk;
516 
517 	struct dl_image {
518 		u32 magic;
519 		u32 id;
520 		u32 size;
521 		union {
522 			DECLARE_FLEX_ARRAY(u32, data);
523 			DECLARE_FLEX_ARRAY(struct dl_block, blocks);
524 		};
525 	} *image;
526 
527 	struct dl_codeblock {
528 		u32 npe_addr;
529 		u32 size;
530 		u32 data[];
531 	} *cb;
532 
533 	int i, j, err, data_size, instr_size, blocks, table_end;
534 	u32 cmd;
535 
536 	if ((err = request_firmware(&fw_entry, name, dev)) != 0)
537 		return err;
538 
539 	err = -EINVAL;
540 	if (fw_entry->size < sizeof(struct dl_image)) {
541 		print_npe(KERN_ERR, npe, "incomplete firmware file\n");
542 		goto err;
543 	}
544 	image = (struct dl_image*)fw_entry->data;
545 
546 #if DEBUG_FW
547 	print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n",
548 		  image->magic, image->id, image->size, image->size * 4);
549 #endif
550 
551 	if (image->magic == swab32(FW_MAGIC)) { /* swapped file */
552 		image->id = swab32(image->id);
553 		image->size = swab32(image->size);
554 	} else if (image->magic != FW_MAGIC) {
555 		print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n",
556 			  image->magic);
557 		goto err;
558 	}
559 	if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) {
560 		print_npe(KERN_ERR, npe,
561 			  "inconsistent size of firmware file\n");
562 		goto err;
563 	}
564 	if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) {
565 		print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n");
566 		goto err;
567 	}
568 	if (image->magic == swab32(FW_MAGIC))
569 		for (i = 0; i < image->size; i++)
570 			image->data[i] = swab32(image->data[i]);
571 
572 	if (cpu_is_ixp42x() && ((image->id >> 28) & 0xF /* device ID */)) {
573 		print_npe(KERN_INFO, npe, "IXP43x/IXP46x firmware ignored on "
574 			  "IXP42x\n");
575 		goto err;
576 	}
577 
578 	if (npe_running(npe)) {
579 		print_npe(KERN_INFO, npe, "unable to load firmware, NPE is "
580 			  "already running\n");
581 		err = -EBUSY;
582 		goto err;
583 	}
584 #if 0
585 	npe_stop(npe);
586 	npe_reset(npe);
587 #endif
588 
589 	print_npe(KERN_INFO, npe, "firmware functionality 0x%X, "
590 		  "revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
591 		  (image->id >> 8) & 0xFF, image->id & 0xFF);
592 
593 	if (cpu_is_ixp42x()) {
594 		if (!npe->id)
595 			instr_size = NPE_A_42X_INSTR_SIZE;
596 		else
597 			instr_size = NPE_B_AND_C_42X_INSTR_SIZE;
598 		data_size = NPE_42X_DATA_SIZE;
599 	} else {
600 		instr_size = NPE_46X_INSTR_SIZE;
601 		data_size = NPE_46X_DATA_SIZE;
602 	}
603 
604 	for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size;
605 	     blocks++)
606 		if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF)
607 			break;
608 	if (blocks * sizeof(struct dl_block) / 4 >= image->size) {
609 		print_npe(KERN_INFO, npe, "firmware EOF block marker not "
610 			  "found\n");
611 		goto err;
612 	}
613 
614 #if DEBUG_FW
615 	print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks);
616 #endif
617 
618 	table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */;
619 	for (i = 0, blk = image->blocks; i < blocks; i++, blk++) {
620 		if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4
621 		    || blk->offset < table_end) {
622 			print_npe(KERN_INFO, npe, "invalid offset 0x%X of "
623 				  "firmware block #%i\n", blk->offset, i);
624 			goto err;
625 		}
626 
627 		cb = (struct dl_codeblock*)&image->data[blk->offset];
628 		if (blk->type == FW_BLOCK_TYPE_INSTR) {
629 			if (cb->npe_addr + cb->size > instr_size)
630 				goto too_big;
631 			cmd = CMD_WR_INS_MEM;
632 		} else if (blk->type == FW_BLOCK_TYPE_DATA) {
633 			if (cb->npe_addr + cb->size > data_size)
634 				goto too_big;
635 			cmd = CMD_WR_DATA_MEM;
636 		} else {
637 			print_npe(KERN_INFO, npe, "invalid firmware block #%i "
638 				  "type 0x%X\n", i, blk->type);
639 			goto err;
640 		}
641 		if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) {
642 			print_npe(KERN_INFO, npe, "firmware block #%i doesn't "
643 				  "fit in firmware image: type %c, start 0x%X,"
644 				  " length 0x%X\n", i,
645 				  blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
646 				  cb->npe_addr, cb->size);
647 			goto err;
648 		}
649 
650 		for (j = 0; j < cb->size; j++)
651 			npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]);
652 	}
653 
654 	npe_start(npe);
655 	if (!npe_running(npe))
656 		print_npe(KERN_ERR, npe, "unable to start\n");
657 	release_firmware(fw_entry);
658 	return 0;
659 
660 too_big:
661 	print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE "
662 		  "memory: type %c, start 0x%X, length 0x%X\n", i,
663 		  blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
664 		  cb->npe_addr, cb->size);
665 err:
666 	release_firmware(fw_entry);
667 	return err;
668 }
669 
670 
npe_request(unsigned id)671 struct npe *npe_request(unsigned id)
672 {
673 	if (id < NPE_COUNT)
674 		if (npe_tab[id].valid)
675 			if (try_module_get(THIS_MODULE))
676 				return &npe_tab[id];
677 	return NULL;
678 }
679 
npe_release(struct npe * npe)680 void npe_release(struct npe *npe)
681 {
682 	module_put(THIS_MODULE);
683 }
684 
ixp4xx_npe_probe(struct platform_device * pdev)685 static int ixp4xx_npe_probe(struct platform_device *pdev)
686 {
687 	int i, found = 0;
688 	struct device *dev = &pdev->dev;
689 	struct device_node *np = dev->of_node;
690 	struct resource *res;
691 	struct regmap *rmap;
692 	u32 val;
693 
694 	/* This system has only one syscon, so fetch it */
695 	rmap = syscon_regmap_lookup_by_compatible("syscon");
696 	if (IS_ERR(rmap))
697 		return dev_err_probe(dev, PTR_ERR(rmap),
698 				     "failed to look up syscon\n");
699 
700 	for (i = 0; i < NPE_COUNT; i++) {
701 		struct npe *npe = &npe_tab[i];
702 
703 		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
704 		if (!res)
705 			return -ENODEV;
706 
707 		val = cpu_ixp4xx_features(rmap);
708 
709 		if (!(val & (IXP4XX_FEATURE_RESET_NPEA << i))) {
710 			dev_info(dev, "NPE%d at %pR not available\n",
711 				 i, res);
712 			continue; /* NPE already disabled or not present */
713 		}
714 		npe->regs = devm_ioremap_resource(dev, res);
715 		if (IS_ERR(npe->regs))
716 			return PTR_ERR(npe->regs);
717 		npe->rmap = rmap;
718 
719 		if (npe_reset(npe)) {
720 			dev_info(dev, "NPE%d at %pR does not reset\n",
721 				 i, res);
722 			continue;
723 		}
724 		npe->valid = 1;
725 		dev_info(dev, "NPE%d at %pR registered\n", i, res);
726 		found++;
727 	}
728 
729 	if (!found)
730 		return -ENODEV;
731 
732 	/* Spawn crypto subdevice if using device tree */
733 	if (IS_ENABLED(CONFIG_OF) && np)
734 		devm_of_platform_populate(dev);
735 
736 	return 0;
737 }
738 
ixp4xx_npe_remove(struct platform_device * pdev)739 static int ixp4xx_npe_remove(struct platform_device *pdev)
740 {
741 	int i;
742 
743 	for (i = 0; i < NPE_COUNT; i++)
744 		if (npe_tab[i].regs) {
745 			npe_reset(&npe_tab[i]);
746 		}
747 
748 	return 0;
749 }
750 
751 static const struct of_device_id ixp4xx_npe_of_match[] = {
752 	{
753 		.compatible = "intel,ixp4xx-network-processing-engine",
754         },
755 	{},
756 };
757 
758 static struct platform_driver ixp4xx_npe_driver = {
759 	.driver = {
760 		.name           = "ixp4xx-npe",
761 		.of_match_table = ixp4xx_npe_of_match,
762 	},
763 	.probe = ixp4xx_npe_probe,
764 	.remove = ixp4xx_npe_remove,
765 };
766 module_platform_driver(ixp4xx_npe_driver);
767 
768 MODULE_AUTHOR("Krzysztof Halasa");
769 MODULE_LICENSE("GPL v2");
770 MODULE_FIRMWARE(NPE_A_FIRMWARE);
771 MODULE_FIRMWARE(NPE_B_FIRMWARE);
772 MODULE_FIRMWARE(NPE_C_FIRMWARE);
773 
774 EXPORT_SYMBOL(npe_names);
775 EXPORT_SYMBOL(npe_running);
776 EXPORT_SYMBOL(npe_request);
777 EXPORT_SYMBOL(npe_release);
778 EXPORT_SYMBOL(npe_load_firmware);
779 EXPORT_SYMBOL(npe_send_message);
780 EXPORT_SYMBOL(npe_recv_message);
781 EXPORT_SYMBOL(npe_send_recv_message);
782