1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: James Liao <jamesjj.liao@mediatek.com>
5 */
6
7 #include <linux/delay.h>
8 #include <linux/device.h>
9 #include <linux/io.h>
10 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <linux/reset-controller.h>
14 #include <linux/soc/mediatek/mtk-mmsys.h>
15
16 #include "mtk-mmsys.h"
17 #include "mt8167-mmsys.h"
18 #include "mt8183-mmsys.h"
19 #include "mt8186-mmsys.h"
20 #include "mt8188-mmsys.h"
21 #include "mt8192-mmsys.h"
22 #include "mt8195-mmsys.h"
23 #include "mt8365-mmsys.h"
24
25 #define MMSYS_SW_RESET_PER_REG 32
26
27 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
28 .clk_driver = "clk-mt2701-mm",
29 .routes = mmsys_default_routing_table,
30 .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
31 };
32
33 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
34 .clk_driver = "clk-mt2712-mm",
35 .routes = mmsys_default_routing_table,
36 .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
37 };
38
39 static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
40 .clk_driver = "clk-mt6779-mm",
41 };
42
43 static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
44 .clk_driver = "clk-mt6797-mm",
45 };
46
47 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
48 .clk_driver = "clk-mt8167-mm",
49 .routes = mt8167_mmsys_routing_table,
50 .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
51 };
52
53 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
54 .clk_driver = "clk-mt8173-mm",
55 .routes = mmsys_default_routing_table,
56 .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
57 .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
58 .num_resets = 32,
59 };
60
61 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
62 .clk_driver = "clk-mt8183-mm",
63 .routes = mmsys_mt8183_routing_table,
64 .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
65 .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
66 .num_resets = 32,
67 };
68
69 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
70 .clk_driver = "clk-mt8186-mm",
71 .routes = mmsys_mt8186_routing_table,
72 .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
73 .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
74 .num_resets = 32,
75 };
76
77 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
78 .clk_driver = "clk-mt8188-vdo0",
79 .routes = mmsys_mt8188_routing_table,
80 .num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
81 };
82
83 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
84 .clk_driver = "clk-mt8192-mm",
85 .routes = mmsys_mt8192_routing_table,
86 .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
87 .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
88 .num_resets = 32,
89 };
90
91 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
92 .clk_driver = "clk-mt8195-vdo0",
93 .routes = mmsys_mt8195_routing_table,
94 .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
95 };
96
97 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
98 .clk_driver = "clk-mt8195-vdo1",
99 .routes = mmsys_mt8195_vdo1_routing_table,
100 .num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table),
101 .sw0_rst_offset = MT8195_VDO1_SW0_RST_B,
102 .num_resets = 64,
103 };
104
105 static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data = {
106 .clk_driver = "clk-mt8195-vpp0",
107 .is_vppsys = true,
108 };
109
110 static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = {
111 .clk_driver = "clk-mt8195-vpp1",
112 .is_vppsys = true,
113 };
114
115 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
116 .clk_driver = "clk-mt8365-mm",
117 .routes = mt8365_mmsys_routing_table,
118 .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
119 };
120
121 struct mtk_mmsys {
122 void __iomem *regs;
123 const struct mtk_mmsys_driver_data *data;
124 spinlock_t lock; /* protects mmsys_sw_rst_b reg */
125 struct reset_controller_dev rcdev;
126 struct cmdq_client_reg cmdq_base;
127 };
128
mtk_mmsys_update_bits(struct mtk_mmsys * mmsys,u32 offset,u32 mask,u32 val,struct cmdq_pkt * cmdq_pkt)129 static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val,
130 struct cmdq_pkt *cmdq_pkt)
131 {
132 u32 tmp;
133
134 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
135 if (cmdq_pkt) {
136 if (mmsys->cmdq_base.size == 0) {
137 pr_err("mmsys lose gce property, failed to update mmsys bits with cmdq");
138 return;
139 }
140 cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
141 mmsys->cmdq_base.offset + offset, val,
142 mask);
143 return;
144 }
145 #endif
146
147 tmp = readl_relaxed(mmsys->regs + offset);
148 tmp = (tmp & ~mask) | (val & mask);
149 writel_relaxed(tmp, mmsys->regs + offset);
150 }
151
mtk_mmsys_ddp_connect(struct device * dev,enum mtk_ddp_comp_id cur,enum mtk_ddp_comp_id next)152 void mtk_mmsys_ddp_connect(struct device *dev,
153 enum mtk_ddp_comp_id cur,
154 enum mtk_ddp_comp_id next)
155 {
156 struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
157 const struct mtk_mmsys_routes *routes = mmsys->data->routes;
158 int i;
159
160 for (i = 0; i < mmsys->data->num_routes; i++)
161 if (cur == routes[i].from_comp && next == routes[i].to_comp)
162 mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask,
163 routes[i].val, NULL);
164 }
165 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
166
mtk_mmsys_ddp_disconnect(struct device * dev,enum mtk_ddp_comp_id cur,enum mtk_ddp_comp_id next)167 void mtk_mmsys_ddp_disconnect(struct device *dev,
168 enum mtk_ddp_comp_id cur,
169 enum mtk_ddp_comp_id next)
170 {
171 struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
172 const struct mtk_mmsys_routes *routes = mmsys->data->routes;
173 int i;
174
175 for (i = 0; i < mmsys->data->num_routes; i++)
176 if (cur == routes[i].from_comp && next == routes[i].to_comp)
177 mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 0, NULL);
178 }
179 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
180
mtk_mmsys_merge_async_config(struct device * dev,int idx,int width,int height,struct cmdq_pkt * cmdq_pkt)181 void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height,
182 struct cmdq_pkt *cmdq_pkt)
183 {
184 mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx,
185 ~0, height << 16 | width, cmdq_pkt);
186 }
187 EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config);
188
mtk_mmsys_hdr_config(struct device * dev,int be_width,int be_height,struct cmdq_pkt * cmdq_pkt)189 void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height,
190 struct cmdq_pkt *cmdq_pkt)
191 {
192 mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0,
193 be_height << 16 | be_width, cmdq_pkt);
194 }
195 EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_config);
196
mtk_mmsys_mixer_in_config(struct device * dev,int idx,bool alpha_sel,u16 alpha,u8 mode,u32 biwidth,struct cmdq_pkt * cmdq_pkt)197 void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha,
198 u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt)
199 {
200 struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
201
202 mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, ~0,
203 alpha << 16 | alpha, cmdq_pkt);
204 mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx),
205 alpha_sel << (19 + idx), cmdq_pkt);
206 mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
207 GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode, cmdq_pkt);
208 }
209 EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);
210
mtk_mmsys_mixer_in_channel_swap(struct device * dev,int idx,bool channel_swap,struct cmdq_pkt * cmdq_pkt)211 void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap,
212 struct cmdq_pkt *cmdq_pkt)
213 {
214 mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
215 BIT(4), channel_swap << 4, cmdq_pkt);
216 }
217 EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap);
218
mtk_mmsys_ddp_dpi_fmt_config(struct device * dev,u32 val)219 void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
220 {
221 struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
222
223 switch (val) {
224 case MTK_DPI_RGB888_SDR_CON:
225 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
226 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_SDR_CON, NULL);
227 break;
228 case MTK_DPI_RGB565_SDR_CON:
229 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
230 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_SDR_CON, NULL);
231 break;
232 case MTK_DPI_RGB565_DDR_CON:
233 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
234 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_DDR_CON, NULL);
235 break;
236 case MTK_DPI_RGB888_DDR_CON:
237 default:
238 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
239 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_DDR_CON, NULL);
240 break;
241 }
242 }
243 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config);
244
mtk_mmsys_reset_update(struct reset_controller_dev * rcdev,unsigned long id,bool assert)245 static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
246 bool assert)
247 {
248 struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
249 unsigned long flags;
250 u32 offset;
251 u32 reg;
252
253 offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
254 id = id % MMSYS_SW_RESET_PER_REG;
255 reg = mmsys->data->sw0_rst_offset + offset;
256
257 spin_lock_irqsave(&mmsys->lock, flags);
258
259 if (assert)
260 mtk_mmsys_update_bits(mmsys, reg, BIT(id), 0, NULL);
261 else
262 mtk_mmsys_update_bits(mmsys, reg, BIT(id), BIT(id), NULL);
263
264 spin_unlock_irqrestore(&mmsys->lock, flags);
265
266 return 0;
267 }
268
mtk_mmsys_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)269 static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
270 {
271 return mtk_mmsys_reset_update(rcdev, id, true);
272 }
273
mtk_mmsys_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)274 static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
275 {
276 return mtk_mmsys_reset_update(rcdev, id, false);
277 }
278
mtk_mmsys_reset(struct reset_controller_dev * rcdev,unsigned long id)279 static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id)
280 {
281 int ret;
282
283 ret = mtk_mmsys_reset_assert(rcdev, id);
284 if (ret)
285 return ret;
286
287 usleep_range(1000, 1100);
288
289 return mtk_mmsys_reset_deassert(rcdev, id);
290 }
291
292 static const struct reset_control_ops mtk_mmsys_reset_ops = {
293 .assert = mtk_mmsys_reset_assert,
294 .deassert = mtk_mmsys_reset_deassert,
295 .reset = mtk_mmsys_reset,
296 };
297
mtk_mmsys_probe(struct platform_device * pdev)298 static int mtk_mmsys_probe(struct platform_device *pdev)
299 {
300 struct device *dev = &pdev->dev;
301 struct platform_device *clks;
302 struct platform_device *drm;
303 struct mtk_mmsys *mmsys;
304 int ret;
305
306 mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
307 if (!mmsys)
308 return -ENOMEM;
309
310 mmsys->regs = devm_platform_ioremap_resource(pdev, 0);
311 if (IS_ERR(mmsys->regs)) {
312 ret = PTR_ERR(mmsys->regs);
313 dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
314 return ret;
315 }
316
317 mmsys->data = of_device_get_match_data(&pdev->dev);
318
319 if (mmsys->data->num_resets > 0) {
320 spin_lock_init(&mmsys->lock);
321
322 mmsys->rcdev.owner = THIS_MODULE;
323 mmsys->rcdev.nr_resets = mmsys->data->num_resets;
324 mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
325 mmsys->rcdev.of_node = pdev->dev.of_node;
326 ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
327 if (ret) {
328 dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
329 return ret;
330 }
331 }
332
333 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
334 ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
335 if (ret)
336 dev_dbg(dev, "No mediatek,gce-client-reg!\n");
337 #endif
338
339 platform_set_drvdata(pdev, mmsys);
340
341 clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
342 PLATFORM_DEVID_AUTO, NULL, 0);
343 if (IS_ERR(clks))
344 return PTR_ERR(clks);
345
346 if (mmsys->data->is_vppsys)
347 goto out_probe_done;
348
349 drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
350 PLATFORM_DEVID_AUTO, NULL, 0);
351 if (IS_ERR(drm)) {
352 platform_device_unregister(clks);
353 return PTR_ERR(drm);
354 }
355
356 out_probe_done:
357 return 0;
358 }
359
360 static const struct of_device_id of_match_mtk_mmsys[] = {
361 {
362 .compatible = "mediatek,mt2701-mmsys",
363 .data = &mt2701_mmsys_driver_data,
364 },
365 {
366 .compatible = "mediatek,mt2712-mmsys",
367 .data = &mt2712_mmsys_driver_data,
368 },
369 {
370 .compatible = "mediatek,mt6779-mmsys",
371 .data = &mt6779_mmsys_driver_data,
372 },
373 {
374 .compatible = "mediatek,mt6797-mmsys",
375 .data = &mt6797_mmsys_driver_data,
376 },
377 {
378 .compatible = "mediatek,mt8167-mmsys",
379 .data = &mt8167_mmsys_driver_data,
380 },
381 {
382 .compatible = "mediatek,mt8173-mmsys",
383 .data = &mt8173_mmsys_driver_data,
384 },
385 {
386 .compatible = "mediatek,mt8183-mmsys",
387 .data = &mt8183_mmsys_driver_data,
388 },
389 {
390 .compatible = "mediatek,mt8186-mmsys",
391 .data = &mt8186_mmsys_driver_data,
392 },
393 {
394 .compatible = "mediatek,mt8188-vdosys0",
395 .data = &mt8188_vdosys0_driver_data,
396 },
397 {
398 .compatible = "mediatek,mt8192-mmsys",
399 .data = &mt8192_mmsys_driver_data,
400 },
401 { /* deprecated compatible */
402 .compatible = "mediatek,mt8195-mmsys",
403 .data = &mt8195_vdosys0_driver_data,
404 },
405 {
406 .compatible = "mediatek,mt8195-vdosys0",
407 .data = &mt8195_vdosys0_driver_data,
408 },
409 {
410 .compatible = "mediatek,mt8195-vdosys1",
411 .data = &mt8195_vdosys1_driver_data,
412 },
413 {
414 .compatible = "mediatek,mt8195-vppsys0",
415 .data = &mt8195_vppsys0_driver_data,
416 },
417 {
418 .compatible = "mediatek,mt8195-vppsys1",
419 .data = &mt8195_vppsys1_driver_data,
420 },
421 {
422 .compatible = "mediatek,mt8365-mmsys",
423 .data = &mt8365_mmsys_driver_data,
424 },
425 { }
426 };
427
428 static struct platform_driver mtk_mmsys_drv = {
429 .driver = {
430 .name = "mtk-mmsys",
431 .of_match_table = of_match_mtk_mmsys,
432 },
433 .probe = mtk_mmsys_probe,
434 };
435
mtk_mmsys_init(void)436 static int __init mtk_mmsys_init(void)
437 {
438 return platform_driver_register(&mtk_mmsys_drv);
439 }
440
mtk_mmsys_exit(void)441 static void __exit mtk_mmsys_exit(void)
442 {
443 platform_driver_unregister(&mtk_mmsys_drv);
444 }
445
446 module_init(mtk_mmsys_init);
447 module_exit(mtk_mmsys_exit);
448
449 MODULE_AUTHOR("Yongqiang Niu <yongqiang.niu@mediatek.com>");
450 MODULE_DESCRIPTION("MediaTek SoC MMSYS driver");
451 MODULE_LICENSE("GPL");
452