1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Synopsys DesignWare 8250 library header file. */
3 
4 #include <linux/io.h>
5 #include <linux/notifier.h>
6 #include <linux/types.h>
7 #include <linux/workqueue.h>
8 
9 #include "8250.h"
10 
11 struct clk;
12 struct reset_control;
13 
14 struct dw8250_port_data {
15 	/* Port properties */
16 	int			line;
17 
18 	/* DMA operations */
19 	struct uart_8250_dma	dma;
20 
21 	/* Hardware configuration */
22 	u8			dlf_size;
23 
24 	/* RS485 variables */
25 	bool			hw_rs485_support;
26 };
27 
28 struct dw8250_platform_data {
29 	u8 usr_reg;
30 	u32 cpr_val;
31 	unsigned int quirks;
32 };
33 
34 struct dw8250_data {
35 	struct dw8250_port_data	data;
36 	const struct dw8250_platform_data *pdata;
37 
38 	int			msr_mask_on;
39 	int			msr_mask_off;
40 	struct clk		*clk;
41 	struct clk		*pclk;
42 	struct notifier_block	clk_notifier;
43 	struct work_struct	clk_work;
44 	struct reset_control	*rst;
45 
46 	unsigned int		skip_autocfg:1;
47 	unsigned int		uart_16550_compatible:1;
48 };
49 
50 void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios, const struct ktermios *old);
51 void dw8250_setup_port(struct uart_port *p);
52 
to_dw8250_data(struct dw8250_port_data * data)53 static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
54 {
55 	return container_of(data, struct dw8250_data, data);
56 }
57 
dw8250_readl_ext(struct uart_port * p,int offset)58 static inline u32 dw8250_readl_ext(struct uart_port *p, int offset)
59 {
60 	if (p->iotype == UPIO_MEM32BE)
61 		return ioread32be(p->membase + offset);
62 	return readl(p->membase + offset);
63 }
64 
dw8250_writel_ext(struct uart_port * p,int offset,u32 reg)65 static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg)
66 {
67 	if (p->iotype == UPIO_MEM32BE)
68 		iowrite32be(reg, p->membase + offset);
69 	else
70 		writel(reg, p->membase + offset);
71 }
72