1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
4 * Copyright (C) 2015 Imagination Technologies
5 *
6 * Ingenic SoC UART support
7 */
8
9 #include <linux/clk.h>
10 #include <linux/console.h>
11 #include <linux/io.h>
12 #include <linux/libfdt.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_fdt.h>
16 #include <linux/of_device.h>
17 #include <linux/platform_device.h>
18 #include <linux/serial_8250.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial_reg.h>
21
22 #include "8250.h"
23
24 /** ingenic_uart_config: SOC specific config data. */
25 struct ingenic_uart_config {
26 int tx_loadsz;
27 int fifosize;
28 };
29
30 struct ingenic_uart_data {
31 struct clk *clk_module;
32 struct clk *clk_baud;
33 int line;
34 };
35
36 static const struct of_device_id of_match[];
37
38 #define UART_FCR_UME BIT(4)
39
40 #define UART_MCR_MDCE BIT(7)
41 #define UART_MCR_FCM BIT(6)
42
43 static struct earlycon_device *early_device;
44
early_in(struct uart_port * port,int offset)45 static uint8_t early_in(struct uart_port *port, int offset)
46 {
47 return readl(port->membase + (offset << 2));
48 }
49
early_out(struct uart_port * port,int offset,uint8_t value)50 static void early_out(struct uart_port *port, int offset, uint8_t value)
51 {
52 writel(value, port->membase + (offset << 2));
53 }
54
ingenic_early_console_putc(struct uart_port * port,unsigned char c)55 static void ingenic_early_console_putc(struct uart_port *port, unsigned char c)
56 {
57 u16 lsr;
58
59 do {
60 lsr = early_in(port, UART_LSR);
61 } while ((lsr & UART_LSR_TEMT) == 0);
62
63 early_out(port, UART_TX, c);
64 }
65
ingenic_early_console_write(struct console * console,const char * s,unsigned int count)66 static void ingenic_early_console_write(struct console *console,
67 const char *s, unsigned int count)
68 {
69 uart_console_write(&early_device->port, s, count,
70 ingenic_early_console_putc);
71 }
72
ingenic_early_console_setup_clock(struct earlycon_device * dev)73 static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev)
74 {
75 void *fdt = initial_boot_params;
76 const __be32 *prop;
77 int offset;
78
79 offset = fdt_path_offset(fdt, "/ext");
80 if (offset < 0)
81 return;
82
83 prop = fdt_getprop(fdt, offset, "clock-frequency", NULL);
84 if (!prop)
85 return;
86
87 dev->port.uartclk = be32_to_cpup(prop);
88 }
89
ingenic_earlycon_setup_tail(struct earlycon_device * dev,const char * opt)90 static int __init ingenic_earlycon_setup_tail(struct earlycon_device *dev,
91 const char *opt)
92 {
93 struct uart_port *port = &dev->port;
94 unsigned int divisor;
95 int baud = 115200;
96
97 if (!dev->port.membase)
98 return -ENODEV;
99
100 if (opt) {
101 unsigned int parity, bits, flow; /* unused for now */
102
103 uart_parse_options(opt, &baud, &parity, &bits, &flow);
104 }
105
106 if (dev->baud)
107 baud = dev->baud;
108 divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * baud);
109
110 early_out(port, UART_IER, 0);
111 early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
112 early_out(port, UART_DLL, 0);
113 early_out(port, UART_DLM, 0);
114 early_out(port, UART_LCR, UART_LCR_WLEN8);
115 early_out(port, UART_FCR, UART_FCR_UME | UART_FCR_CLEAR_XMIT |
116 UART_FCR_CLEAR_RCVR | UART_FCR_ENABLE_FIFO);
117 early_out(port, UART_MCR, UART_MCR_RTS | UART_MCR_DTR);
118
119 early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
120 early_out(port, UART_DLL, divisor & 0xff);
121 early_out(port, UART_DLM, (divisor >> 8) & 0xff);
122 early_out(port, UART_LCR, UART_LCR_WLEN8);
123
124 early_device = dev;
125 dev->con->write = ingenic_early_console_write;
126
127 return 0;
128 }
129
ingenic_early_console_setup(struct earlycon_device * dev,const char * opt)130 static int __init ingenic_early_console_setup(struct earlycon_device *dev,
131 const char *opt)
132 {
133 ingenic_early_console_setup_clock(dev);
134
135 return ingenic_earlycon_setup_tail(dev, opt);
136 }
137
jz4750_early_console_setup(struct earlycon_device * dev,const char * opt)138 static int __init jz4750_early_console_setup(struct earlycon_device *dev,
139 const char *opt)
140 {
141 /*
142 * JZ4750/55/60 have an optional /2 divider between the EXT
143 * oscillator and some peripherals including UART, which will
144 * be enabled if using a 24 MHz oscillator, and disabled when
145 * using a 12 MHz oscillator.
146 */
147 ingenic_early_console_setup_clock(dev);
148 if (dev->port.uartclk >= 16000000)
149 dev->port.uartclk /= 2;
150
151 return ingenic_earlycon_setup_tail(dev, opt);
152 }
153
154 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
155 ingenic_early_console_setup);
156
157 OF_EARLYCON_DECLARE(jz4750_uart, "ingenic,jz4750-uart",
158 jz4750_early_console_setup);
159
160 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
161 ingenic_early_console_setup);
162
163 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
164 ingenic_early_console_setup);
165
166 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
167 ingenic_early_console_setup);
168
169 OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
170 ingenic_early_console_setup);
171
ingenic_uart_serial_out(struct uart_port * p,int offset,int value)172 static void ingenic_uart_serial_out(struct uart_port *p, int offset, int value)
173 {
174 int ier;
175
176 switch (offset) {
177 case UART_FCR:
178 /* UART module enable */
179 value |= UART_FCR_UME;
180 break;
181
182 case UART_IER:
183 /*
184 * Enable receive timeout interrupt with the receive line
185 * status interrupt.
186 */
187 value |= (value & 0x4) << 2;
188 break;
189
190 case UART_MCR:
191 /*
192 * If we have enabled modem status IRQs we should enable
193 * modem mode.
194 */
195 ier = p->serial_in(p, UART_IER);
196
197 if (ier & UART_IER_MSI)
198 value |= UART_MCR_MDCE | UART_MCR_FCM;
199 else
200 value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
201 break;
202
203 default:
204 break;
205 }
206
207 writeb(value, p->membase + (offset << p->regshift));
208 }
209
ingenic_uart_serial_in(struct uart_port * p,int offset)210 static unsigned int ingenic_uart_serial_in(struct uart_port *p, int offset)
211 {
212 unsigned int value;
213
214 value = readb(p->membase + (offset << p->regshift));
215
216 /* Hide non-16550 compliant bits from higher levels */
217 switch (offset) {
218 case UART_FCR:
219 value &= ~UART_FCR_UME;
220 break;
221
222 case UART_MCR:
223 value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
224 break;
225
226 default:
227 break;
228 }
229 return value;
230 }
231
ingenic_uart_probe(struct platform_device * pdev)232 static int ingenic_uart_probe(struct platform_device *pdev)
233 {
234 struct uart_8250_port uart = {};
235 struct ingenic_uart_data *data;
236 const struct ingenic_uart_config *cdata;
237 struct resource *regs;
238 int irq, err, line;
239
240 cdata = of_device_get_match_data(&pdev->dev);
241 if (!cdata) {
242 dev_err(&pdev->dev, "Error: No device match found\n");
243 return -ENODEV;
244 }
245
246 irq = platform_get_irq(pdev, 0);
247 if (irq < 0)
248 return irq;
249
250 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
251 if (!regs) {
252 dev_err(&pdev->dev, "no registers defined\n");
253 return -EINVAL;
254 }
255
256 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
257 if (!data)
258 return -ENOMEM;
259
260 spin_lock_init(&uart.port.lock);
261 uart.port.type = PORT_16550A;
262 uart.port.flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE;
263 uart.port.iotype = UPIO_MEM;
264 uart.port.mapbase = regs->start;
265 uart.port.regshift = 2;
266 uart.port.serial_out = ingenic_uart_serial_out;
267 uart.port.serial_in = ingenic_uart_serial_in;
268 uart.port.irq = irq;
269 uart.port.dev = &pdev->dev;
270 uart.port.fifosize = cdata->fifosize;
271 uart.tx_loadsz = cdata->tx_loadsz;
272 uart.capabilities = UART_CAP_FIFO | UART_CAP_RTOIE;
273
274 /* Check for a fixed line number */
275 line = of_alias_get_id(pdev->dev.of_node, "serial");
276 if (line >= 0)
277 uart.port.line = line;
278
279 uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
280 resource_size(regs));
281 if (!uart.port.membase)
282 return -ENOMEM;
283
284 data->clk_module = devm_clk_get(&pdev->dev, "module");
285 if (IS_ERR(data->clk_module))
286 return dev_err_probe(&pdev->dev, PTR_ERR(data->clk_module),
287 "unable to get module clock\n");
288
289 data->clk_baud = devm_clk_get(&pdev->dev, "baud");
290 if (IS_ERR(data->clk_baud))
291 return dev_err_probe(&pdev->dev, PTR_ERR(data->clk_baud),
292 "unable to get baud clock\n");
293
294 err = clk_prepare_enable(data->clk_module);
295 if (err) {
296 dev_err(&pdev->dev, "could not enable module clock: %d\n", err);
297 goto out;
298 }
299
300 err = clk_prepare_enable(data->clk_baud);
301 if (err) {
302 dev_err(&pdev->dev, "could not enable baud clock: %d\n", err);
303 goto out_disable_moduleclk;
304 }
305 uart.port.uartclk = clk_get_rate(data->clk_baud);
306
307 data->line = serial8250_register_8250_port(&uart);
308 if (data->line < 0) {
309 err = data->line;
310 goto out_disable_baudclk;
311 }
312
313 platform_set_drvdata(pdev, data);
314 return 0;
315
316 out_disable_baudclk:
317 clk_disable_unprepare(data->clk_baud);
318 out_disable_moduleclk:
319 clk_disable_unprepare(data->clk_module);
320 out:
321 return err;
322 }
323
ingenic_uart_remove(struct platform_device * pdev)324 static int ingenic_uart_remove(struct platform_device *pdev)
325 {
326 struct ingenic_uart_data *data = platform_get_drvdata(pdev);
327
328 serial8250_unregister_port(data->line);
329 clk_disable_unprepare(data->clk_module);
330 clk_disable_unprepare(data->clk_baud);
331 return 0;
332 }
333
334 static const struct ingenic_uart_config jz4740_uart_config = {
335 .tx_loadsz = 8,
336 .fifosize = 16,
337 };
338
339 static const struct ingenic_uart_config jz4760_uart_config = {
340 .tx_loadsz = 16,
341 .fifosize = 32,
342 };
343
344 static const struct ingenic_uart_config jz4780_uart_config = {
345 .tx_loadsz = 32,
346 .fifosize = 64,
347 };
348
349 static const struct ingenic_uart_config x1000_uart_config = {
350 .tx_loadsz = 32,
351 .fifosize = 64,
352 };
353
354 static const struct of_device_id of_match[] = {
355 { .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config },
356 { .compatible = "ingenic,jz4750-uart", .data = &jz4760_uart_config },
357 { .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config },
358 { .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config },
359 { .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },
360 { .compatible = "ingenic,jz4780-uart", .data = &jz4780_uart_config },
361 { .compatible = "ingenic,x1000-uart", .data = &x1000_uart_config },
362 { /* sentinel */ }
363 };
364 MODULE_DEVICE_TABLE(of, of_match);
365
366 static struct platform_driver ingenic_uart_platform_driver = {
367 .driver = {
368 .name = "ingenic-uart",
369 .of_match_table = of_match,
370 },
371 .probe = ingenic_uart_probe,
372 .remove = ingenic_uart_remove,
373 };
374
375 module_platform_driver(ingenic_uart_platform_driver);
376
377 MODULE_AUTHOR("Paul Burton");
378 MODULE_LICENSE("GPL");
379 MODULE_DESCRIPTION("Ingenic SoC UART driver");
380