1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3  * Apple SoC Watchdog driver
4  *
5  * Copyright (C) The Asahi Linux Contributors
6  */
7 
8 #include <linux/bits.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/limits.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/platform_device.h>
17 #include <linux/watchdog.h>
18 
19 /*
20  * Apple Watchdog MMIO registers
21  *
22  * This HW block has three separate watchdogs. WD0 resets the machine
23  * to recovery mode and is not very useful for us. WD1 and WD2 trigger a normal
24  * machine reset. WD0 additionally supports a configurable interrupt.
25  * This information can be used to implement pretimeout support at a later time.
26  *
27  * APPLE_WDT_WDx_CUR_TIME is a simple counter incremented for each tick of the
28  * reference clock. It can also be overwritten to any value.
29  * Whenever APPLE_WDT_CTRL_RESET_EN is set in APPLE_WDT_WDx_CTRL and
30  * APPLE_WDT_WDx_CUR_TIME >= APPLE_WDT_WDx_BITE_TIME the entire machine is
31  * reset.
32  * Whenever APPLE_WDT_CTRL_IRQ_EN is set and APPLE_WDTx_WD1_CUR_TIME >=
33  * APPLE_WDTx_WD1_BARK_TIME an interrupt is triggered and
34  * APPLE_WDT_CTRL_IRQ_STATUS is set. The interrupt can be cleared by writing
35  * 1 to APPLE_WDT_CTRL_IRQ_STATUS.
36  */
37 #define APPLE_WDT_WD0_CUR_TIME		0x00
38 #define APPLE_WDT_WD0_BITE_TIME		0x04
39 #define APPLE_WDT_WD0_BARK_TIME		0x08
40 #define APPLE_WDT_WD0_CTRL		0x0c
41 
42 #define APPLE_WDT_WD1_CUR_TIME		0x10
43 #define APPLE_WDT_WD1_BITE_TIME		0x14
44 #define APPLE_WDT_WD1_CTRL		0x1c
45 
46 #define APPLE_WDT_WD2_CUR_TIME		0x20
47 #define APPLE_WDT_WD2_BITE_TIME		0x24
48 #define APPLE_WDT_WD2_CTRL		0x2c
49 
50 #define APPLE_WDT_CTRL_IRQ_EN		BIT(0)
51 #define APPLE_WDT_CTRL_IRQ_STATUS	BIT(1)
52 #define APPLE_WDT_CTRL_RESET_EN		BIT(2)
53 
54 #define APPLE_WDT_TIMEOUT_DEFAULT	30
55 
56 struct apple_wdt {
57 	struct watchdog_device wdd;
58 	void __iomem *regs;
59 	unsigned long clk_rate;
60 };
61 
to_apple_wdt(struct watchdog_device * wdd)62 static struct apple_wdt *to_apple_wdt(struct watchdog_device *wdd)
63 {
64 	return container_of(wdd, struct apple_wdt, wdd);
65 }
66 
apple_wdt_start(struct watchdog_device * wdd)67 static int apple_wdt_start(struct watchdog_device *wdd)
68 {
69 	struct apple_wdt *wdt = to_apple_wdt(wdd);
70 
71 	writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
72 	writel_relaxed(APPLE_WDT_CTRL_RESET_EN, wdt->regs + APPLE_WDT_WD1_CTRL);
73 
74 	return 0;
75 }
76 
apple_wdt_stop(struct watchdog_device * wdd)77 static int apple_wdt_stop(struct watchdog_device *wdd)
78 {
79 	struct apple_wdt *wdt = to_apple_wdt(wdd);
80 
81 	writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CTRL);
82 
83 	return 0;
84 }
85 
apple_wdt_ping(struct watchdog_device * wdd)86 static int apple_wdt_ping(struct watchdog_device *wdd)
87 {
88 	struct apple_wdt *wdt = to_apple_wdt(wdd);
89 
90 	writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
91 
92 	return 0;
93 }
94 
apple_wdt_set_timeout(struct watchdog_device * wdd,unsigned int s)95 static int apple_wdt_set_timeout(struct watchdog_device *wdd, unsigned int s)
96 {
97 	struct apple_wdt *wdt = to_apple_wdt(wdd);
98 
99 	writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
100 	writel_relaxed(wdt->clk_rate * s, wdt->regs + APPLE_WDT_WD1_BITE_TIME);
101 
102 	wdd->timeout = s;
103 
104 	return 0;
105 }
106 
apple_wdt_get_timeleft(struct watchdog_device * wdd)107 static unsigned int apple_wdt_get_timeleft(struct watchdog_device *wdd)
108 {
109 	struct apple_wdt *wdt = to_apple_wdt(wdd);
110 	u32 cur_time, reset_time;
111 
112 	cur_time = readl_relaxed(wdt->regs + APPLE_WDT_WD1_CUR_TIME);
113 	reset_time = readl_relaxed(wdt->regs + APPLE_WDT_WD1_BITE_TIME);
114 
115 	return (reset_time - cur_time) / wdt->clk_rate;
116 }
117 
apple_wdt_restart(struct watchdog_device * wdd,unsigned long mode,void * cmd)118 static int apple_wdt_restart(struct watchdog_device *wdd, unsigned long mode,
119 			     void *cmd)
120 {
121 	struct apple_wdt *wdt = to_apple_wdt(wdd);
122 
123 	writel_relaxed(APPLE_WDT_CTRL_RESET_EN, wdt->regs + APPLE_WDT_WD1_CTRL);
124 	writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_BITE_TIME);
125 	writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
126 
127 	/*
128 	 * Flush writes and then wait for the SoC to reset. Even though the
129 	 * reset is queued almost immediately experiments have shown that it
130 	 * can take up to ~20-25ms until the SoC is actually reset. Just wait
131 	 * 50ms here to be safe.
132 	 */
133 	(void)readl_relaxed(wdt->regs + APPLE_WDT_WD1_CUR_TIME);
134 	mdelay(50);
135 
136 	return 0;
137 }
138 
139 static struct watchdog_ops apple_wdt_ops = {
140 	.owner = THIS_MODULE,
141 	.start = apple_wdt_start,
142 	.stop = apple_wdt_stop,
143 	.ping = apple_wdt_ping,
144 	.set_timeout = apple_wdt_set_timeout,
145 	.get_timeleft = apple_wdt_get_timeleft,
146 	.restart = apple_wdt_restart,
147 };
148 
149 static struct watchdog_info apple_wdt_info = {
150 	.identity = "Apple SoC Watchdog",
151 	.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
152 };
153 
apple_wdt_probe(struct platform_device * pdev)154 static int apple_wdt_probe(struct platform_device *pdev)
155 {
156 	struct device *dev = &pdev->dev;
157 	struct apple_wdt *wdt;
158 	struct clk *clk;
159 	u32 wdt_ctrl;
160 
161 	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
162 	if (!wdt)
163 		return -ENOMEM;
164 
165 	wdt->regs = devm_platform_ioremap_resource(pdev, 0);
166 	if (IS_ERR(wdt->regs))
167 		return PTR_ERR(wdt->regs);
168 
169 	clk = devm_clk_get_enabled(dev, NULL);
170 	if (IS_ERR(clk))
171 		return PTR_ERR(clk);
172 	wdt->clk_rate = clk_get_rate(clk);
173 	if (!wdt->clk_rate)
174 		return -EINVAL;
175 
176 	wdt->wdd.ops = &apple_wdt_ops;
177 	wdt->wdd.info = &apple_wdt_info;
178 	wdt->wdd.max_timeout = U32_MAX / wdt->clk_rate;
179 	wdt->wdd.timeout = APPLE_WDT_TIMEOUT_DEFAULT;
180 
181 	wdt_ctrl = readl_relaxed(wdt->regs + APPLE_WDT_WD1_CTRL);
182 	if (wdt_ctrl & APPLE_WDT_CTRL_RESET_EN)
183 		set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
184 
185 	watchdog_init_timeout(&wdt->wdd, 0, dev);
186 	apple_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout);
187 	watchdog_stop_on_unregister(&wdt->wdd);
188 	watchdog_set_restart_priority(&wdt->wdd, 128);
189 
190 	return devm_watchdog_register_device(dev, &wdt->wdd);
191 }
192 
193 static const struct of_device_id apple_wdt_of_match[] = {
194 	{ .compatible = "apple,wdt" },
195 	{},
196 };
197 MODULE_DEVICE_TABLE(of, apple_wdt_of_match);
198 
199 static struct platform_driver apple_wdt_driver = {
200 	.driver = {
201 		.name = "apple-watchdog",
202 		.of_match_table = apple_wdt_of_match,
203 	},
204 	.probe = apple_wdt_probe,
205 };
206 module_platform_driver(apple_wdt_driver);
207 
208 MODULE_DESCRIPTION("Apple SoC watchdog driver");
209 MODULE_AUTHOR("Sven Peter <sven@svenpeter.dev>");
210 MODULE_LICENSE("Dual MIT/GPL");
211