1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2012, The Linux Foundation. All rights reserved.
4 */
5
6 #ifndef _LINUX_CORESIGHT_H
7 #define _LINUX_CORESIGHT_H
8
9 #include <linux/device.h>
10 #include <linux/io.h>
11 #include <linux/perf_event.h>
12 #include <linux/sched.h>
13
14 /* Peripheral id registers (0xFD0-0xFEC) */
15 #define CORESIGHT_PERIPHIDR4 0xfd0
16 #define CORESIGHT_PERIPHIDR5 0xfd4
17 #define CORESIGHT_PERIPHIDR6 0xfd8
18 #define CORESIGHT_PERIPHIDR7 0xfdC
19 #define CORESIGHT_PERIPHIDR0 0xfe0
20 #define CORESIGHT_PERIPHIDR1 0xfe4
21 #define CORESIGHT_PERIPHIDR2 0xfe8
22 #define CORESIGHT_PERIPHIDR3 0xfeC
23 /* Component id registers (0xFF0-0xFFC) */
24 #define CORESIGHT_COMPIDR0 0xff0
25 #define CORESIGHT_COMPIDR1 0xff4
26 #define CORESIGHT_COMPIDR2 0xff8
27 #define CORESIGHT_COMPIDR3 0xffC
28
29 #define ETM_ARCH_V3_3 0x23
30 #define ETM_ARCH_V3_5 0x25
31 #define PFT_ARCH_V1_0 0x30
32 #define PFT_ARCH_V1_1 0x31
33
34 #define CORESIGHT_UNLOCK 0xc5acce55
35
36 extern struct bus_type coresight_bustype;
37
38 enum coresight_dev_type {
39 CORESIGHT_DEV_TYPE_SINK,
40 CORESIGHT_DEV_TYPE_LINK,
41 CORESIGHT_DEV_TYPE_LINKSINK,
42 CORESIGHT_DEV_TYPE_SOURCE,
43 CORESIGHT_DEV_TYPE_HELPER,
44 CORESIGHT_DEV_TYPE_ECT,
45 };
46
47 enum coresight_dev_subtype_sink {
48 CORESIGHT_DEV_SUBTYPE_SINK_PORT,
49 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
50 CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
51 CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,
52 };
53
54 enum coresight_dev_subtype_link {
55 CORESIGHT_DEV_SUBTYPE_LINK_MERG,
56 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
57 CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
58 };
59
60 enum coresight_dev_subtype_source {
61 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
62 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
63 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
64 CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS,
65 };
66
67 enum coresight_dev_subtype_helper {
68 CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
69 };
70
71 /* Embedded Cross Trigger (ECT) sub-types */
72 enum coresight_dev_subtype_ect {
73 CORESIGHT_DEV_SUBTYPE_ECT_NONE,
74 CORESIGHT_DEV_SUBTYPE_ECT_CTI,
75 };
76
77 /**
78 * union coresight_dev_subtype - further characterisation of a type
79 * @sink_subtype: type of sink this component is, as defined
80 * by @coresight_dev_subtype_sink.
81 * @link_subtype: type of link this component is, as defined
82 * by @coresight_dev_subtype_link.
83 * @source_subtype: type of source this component is, as defined
84 * by @coresight_dev_subtype_source.
85 * @helper_subtype: type of helper this component is, as defined
86 * by @coresight_dev_subtype_helper.
87 * @ect_subtype: type of cross trigger this component is, as
88 * defined by @coresight_dev_subtype_ect
89 */
90 union coresight_dev_subtype {
91 /* We have some devices which acts as LINK and SINK */
92 struct {
93 enum coresight_dev_subtype_sink sink_subtype;
94 enum coresight_dev_subtype_link link_subtype;
95 };
96 enum coresight_dev_subtype_source source_subtype;
97 enum coresight_dev_subtype_helper helper_subtype;
98 enum coresight_dev_subtype_ect ect_subtype;
99 };
100
101 /**
102 * struct coresight_platform_data - data harvested from the firmware
103 * specification.
104 *
105 * @nr_inport: Number of elements for the input connections.
106 * @nr_outport: Number of elements for the output connections.
107 * @conns: Sparse array of nr_outport connections from this component.
108 */
109 struct coresight_platform_data {
110 int nr_inport;
111 int nr_outport;
112 struct coresight_connection *conns;
113 };
114
115 /**
116 * struct csdev_access - Abstraction of a CoreSight device access.
117 *
118 * @io_mem : True if the device has memory mapped I/O
119 * @base : When io_mem == true, base address of the component
120 * @read : Read from the given "offset" of the given instance.
121 * @write : Write "val" to the given "offset".
122 */
123 struct csdev_access {
124 bool io_mem;
125 union {
126 void __iomem *base;
127 struct {
128 u64 (*read)(u32 offset, bool relaxed, bool _64bit);
129 void (*write)(u64 val, u32 offset, bool relaxed,
130 bool _64bit);
131 };
132 };
133 };
134
135 #define CSDEV_ACCESS_IOMEM(_addr) \
136 ((struct csdev_access) { \
137 .io_mem = true, \
138 .base = (_addr), \
139 })
140
141 /**
142 * struct coresight_desc - description of a component required from drivers
143 * @type: as defined by @coresight_dev_type.
144 * @subtype: as defined by @coresight_dev_subtype.
145 * @ops: generic operations for this component, as defined
146 * by @coresight_ops.
147 * @pdata: platform data collected from DT.
148 * @dev: The device entity associated to this component.
149 * @groups: operations specific to this component. These will end up
150 * in the component's sysfs sub-directory.
151 * @name: name for the coresight device, also shown under sysfs.
152 * @access: Describe access to the device
153 */
154 struct coresight_desc {
155 enum coresight_dev_type type;
156 union coresight_dev_subtype subtype;
157 const struct coresight_ops *ops;
158 struct coresight_platform_data *pdata;
159 struct device *dev;
160 const struct attribute_group **groups;
161 const char *name;
162 struct csdev_access access;
163 };
164
165 /**
166 * struct coresight_connection - representation of a single connection
167 * @outport: a connection's output port number.
168 * @child_port: remote component's port number @output is connected to.
169 * @chid_fwnode: remote component's fwnode handle.
170 * @child_dev: a @coresight_device representation of the component
171 connected to @outport.
172 * @link: Representation of the connection as a sysfs link.
173 */
174 struct coresight_connection {
175 int outport;
176 int child_port;
177 struct fwnode_handle *child_fwnode;
178 struct coresight_device *child_dev;
179 struct coresight_sysfs_link *link;
180 };
181
182 /**
183 * struct coresight_sysfs_link - representation of a connection in sysfs.
184 * @orig: Originating (master) coresight device for the link.
185 * @orig_name: Name to use for the link orig->target.
186 * @target: Target (slave) coresight device for the link.
187 * @target_name: Name to use for the link target->orig.
188 */
189 struct coresight_sysfs_link {
190 struct coresight_device *orig;
191 const char *orig_name;
192 struct coresight_device *target;
193 const char *target_name;
194 };
195
196 /**
197 * struct coresight_device - representation of a device as used by the framework
198 * @pdata: Platform data with device connections associated to this device.
199 * @type: as defined by @coresight_dev_type.
200 * @subtype: as defined by @coresight_dev_subtype.
201 * @ops: generic operations for this component, as defined
202 * by @coresight_ops.
203 * @access: Device i/o access abstraction for this device.
204 * @dev: The device entity associated to this component.
205 * @refcnt: keep track of what is in use.
206 * @orphan: true if the component has connections that haven't been linked.
207 * @enable: 'true' if component is currently part of an active path.
208 * @activated: 'true' only if a _sink_ has been activated. A sink can be
209 * activated but not yet enabled. Enabling for a _sink_
210 * happens when a source has been selected and a path is enabled
211 * from source to that sink.
212 * @ea: Device attribute for sink representation under PMU directory.
213 * @def_sink: cached reference to default sink found for this device.
214 * @ect_dev: Associated cross trigger device. Not part of the trace data
215 * path or connections.
216 * @nr_links: number of sysfs links created to other components from this
217 * device. These will appear in the "connections" group.
218 * @has_conns_grp: Have added a "connections" group for sysfs links.
219 * @feature_csdev_list: List of complex feature programming added to the device.
220 * @config_csdev_list: List of system configurations added to the device.
221 * @cscfg_csdev_lock: Protect the lists of configurations and features.
222 * @active_cscfg_ctxt: Context information for current active system configuration.
223 */
224 struct coresight_device {
225 struct coresight_platform_data *pdata;
226 enum coresight_dev_type type;
227 union coresight_dev_subtype subtype;
228 const struct coresight_ops *ops;
229 struct csdev_access access;
230 struct device dev;
231 atomic_t *refcnt;
232 bool orphan;
233 bool enable; /* true only if configured as part of a path */
234 /* sink specific fields */
235 bool activated; /* true only if a sink is part of a path */
236 struct dev_ext_attribute *ea;
237 struct coresight_device *def_sink;
238 /* cross trigger handling */
239 struct coresight_device *ect_dev;
240 /* sysfs links between components */
241 int nr_links;
242 bool has_conns_grp;
243 bool ect_enabled; /* true only if associated ect device is enabled */
244 /* system configuration and feature lists */
245 struct list_head feature_csdev_list;
246 struct list_head config_csdev_list;
247 spinlock_t cscfg_csdev_lock;
248 void *active_cscfg_ctxt;
249 };
250
251 /*
252 * coresight_dev_list - Mapping for devices to "name" index for device
253 * names.
254 *
255 * @nr_idx: Number of entries already allocated.
256 * @pfx: Prefix pattern for device name.
257 * @fwnode_list: Array of fwnode_handles associated with each allocated
258 * index, upto nr_idx entries.
259 */
260 struct coresight_dev_list {
261 int nr_idx;
262 const char *pfx;
263 struct fwnode_handle **fwnode_list;
264 };
265
266 #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \
267 static struct coresight_dev_list (var) = { \
268 .pfx = dev_pfx, \
269 .nr_idx = 0, \
270 .fwnode_list = NULL, \
271 }
272
273 #define to_coresight_device(d) container_of(d, struct coresight_device, dev)
274
275 #define source_ops(csdev) csdev->ops->source_ops
276 #define sink_ops(csdev) csdev->ops->sink_ops
277 #define link_ops(csdev) csdev->ops->link_ops
278 #define helper_ops(csdev) csdev->ops->helper_ops
279 #define ect_ops(csdev) csdev->ops->ect_ops
280
281 /**
282 * struct coresight_ops_sink - basic operations for a sink
283 * Operations available for sinks
284 * @enable: enables the sink.
285 * @disable: disables the sink.
286 * @alloc_buffer: initialises perf's ring buffer for trace collection.
287 * @free_buffer: release memory allocated in @get_config.
288 * @update_buffer: update buffer pointers after a trace session.
289 */
290 struct coresight_ops_sink {
291 int (*enable)(struct coresight_device *csdev, u32 mode, void *data);
292 int (*disable)(struct coresight_device *csdev);
293 void *(*alloc_buffer)(struct coresight_device *csdev,
294 struct perf_event *event, void **pages,
295 int nr_pages, bool overwrite);
296 void (*free_buffer)(void *config);
297 unsigned long (*update_buffer)(struct coresight_device *csdev,
298 struct perf_output_handle *handle,
299 void *sink_config);
300 };
301
302 /**
303 * struct coresight_ops_link - basic operations for a link
304 * Operations available for links.
305 * @enable: enables flow between iport and oport.
306 * @disable: disables flow between iport and oport.
307 */
308 struct coresight_ops_link {
309 int (*enable)(struct coresight_device *csdev, int iport, int oport);
310 void (*disable)(struct coresight_device *csdev, int iport, int oport);
311 };
312
313 /**
314 * struct coresight_ops_source - basic operations for a source
315 * Operations available for sources.
316 * @cpu_id: returns the value of the CPU number this component
317 * is associated to.
318 * @enable: enables tracing for a source.
319 * @disable: disables tracing for a source.
320 */
321 struct coresight_ops_source {
322 int (*cpu_id)(struct coresight_device *csdev);
323 int (*enable)(struct coresight_device *csdev,
324 struct perf_event *event, u32 mode);
325 void (*disable)(struct coresight_device *csdev,
326 struct perf_event *event);
327 };
328
329 /**
330 * struct coresight_ops_helper - Operations for a helper device.
331 *
332 * All operations could pass in a device specific data, which could
333 * help the helper device to determine what to do.
334 *
335 * @enable : Enable the device
336 * @disable : Disable the device
337 */
338 struct coresight_ops_helper {
339 int (*enable)(struct coresight_device *csdev, void *data);
340 int (*disable)(struct coresight_device *csdev, void *data);
341 };
342
343 /**
344 * struct coresight_ops_ect - Ops for an embedded cross trigger device
345 *
346 * @enable : Enable the device
347 * @disable : Disable the device
348 */
349 struct coresight_ops_ect {
350 int (*enable)(struct coresight_device *csdev);
351 int (*disable)(struct coresight_device *csdev);
352 };
353
354 struct coresight_ops {
355 const struct coresight_ops_sink *sink_ops;
356 const struct coresight_ops_link *link_ops;
357 const struct coresight_ops_source *source_ops;
358 const struct coresight_ops_helper *helper_ops;
359 const struct coresight_ops_ect *ect_ops;
360 };
361
362 #if IS_ENABLED(CONFIG_CORESIGHT)
363
csdev_access_relaxed_read32(struct csdev_access * csa,u32 offset)364 static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,
365 u32 offset)
366 {
367 if (likely(csa->io_mem))
368 return readl_relaxed(csa->base + offset);
369
370 return csa->read(offset, true, false);
371 }
372
csdev_access_relaxed_read_pair(struct csdev_access * csa,u32 lo_offset,u32 hi_offset)373 static inline u64 csdev_access_relaxed_read_pair(struct csdev_access *csa,
374 u32 lo_offset, u32 hi_offset)
375 {
376 if (likely(csa->io_mem)) {
377 return readl_relaxed(csa->base + lo_offset) |
378 ((u64)readl_relaxed(csa->base + hi_offset) << 32);
379 }
380
381 return csa->read(lo_offset, true, false) | (csa->read(hi_offset, true, false) << 32);
382 }
383
csdev_access_relaxed_write_pair(struct csdev_access * csa,u64 val,u32 lo_offset,u32 hi_offset)384 static inline void csdev_access_relaxed_write_pair(struct csdev_access *csa, u64 val,
385 u32 lo_offset, u32 hi_offset)
386 {
387 if (likely(csa->io_mem)) {
388 writel_relaxed((u32)val, csa->base + lo_offset);
389 writel_relaxed((u32)(val >> 32), csa->base + hi_offset);
390 } else {
391 csa->write((u32)val, lo_offset, true, false);
392 csa->write((u32)(val >> 32), hi_offset, true, false);
393 }
394 }
395
csdev_access_read32(struct csdev_access * csa,u32 offset)396 static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset)
397 {
398 if (likely(csa->io_mem))
399 return readl(csa->base + offset);
400
401 return csa->read(offset, false, false);
402 }
403
csdev_access_relaxed_write32(struct csdev_access * csa,u32 val,u32 offset)404 static inline void csdev_access_relaxed_write32(struct csdev_access *csa,
405 u32 val, u32 offset)
406 {
407 if (likely(csa->io_mem))
408 writel_relaxed(val, csa->base + offset);
409 else
410 csa->write(val, offset, true, false);
411 }
412
csdev_access_write32(struct csdev_access * csa,u32 val,u32 offset)413 static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset)
414 {
415 if (likely(csa->io_mem))
416 writel(val, csa->base + offset);
417 else
418 csa->write(val, offset, false, false);
419 }
420
421 #ifdef CONFIG_64BIT
422
csdev_access_relaxed_read64(struct csdev_access * csa,u32 offset)423 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
424 u32 offset)
425 {
426 if (likely(csa->io_mem))
427 return readq_relaxed(csa->base + offset);
428
429 return csa->read(offset, true, true);
430 }
431
csdev_access_read64(struct csdev_access * csa,u32 offset)432 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
433 {
434 if (likely(csa->io_mem))
435 return readq(csa->base + offset);
436
437 return csa->read(offset, false, true);
438 }
439
csdev_access_relaxed_write64(struct csdev_access * csa,u64 val,u32 offset)440 static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
441 u64 val, u32 offset)
442 {
443 if (likely(csa->io_mem))
444 writeq_relaxed(val, csa->base + offset);
445 else
446 csa->write(val, offset, true, true);
447 }
448
csdev_access_write64(struct csdev_access * csa,u64 val,u32 offset)449 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
450 {
451 if (likely(csa->io_mem))
452 writeq(val, csa->base + offset);
453 else
454 csa->write(val, offset, false, true);
455 }
456
457 #else /* !CONFIG_64BIT */
458
csdev_access_relaxed_read64(struct csdev_access * csa,u32 offset)459 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
460 u32 offset)
461 {
462 WARN_ON(1);
463 return 0;
464 }
465
csdev_access_read64(struct csdev_access * csa,u32 offset)466 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
467 {
468 WARN_ON(1);
469 return 0;
470 }
471
csdev_access_relaxed_write64(struct csdev_access * csa,u64 val,u32 offset)472 static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
473 u64 val, u32 offset)
474 {
475 WARN_ON(1);
476 }
477
csdev_access_write64(struct csdev_access * csa,u64 val,u32 offset)478 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
479 {
480 WARN_ON(1);
481 }
482 #endif /* CONFIG_64BIT */
483
coresight_is_percpu_source(struct coresight_device * csdev)484 static inline bool coresight_is_percpu_source(struct coresight_device *csdev)
485 {
486 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) &&
487 (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC);
488 }
489
coresight_is_percpu_sink(struct coresight_device * csdev)490 static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
491 {
492 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
493 (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM);
494 }
495
496 extern struct coresight_device *
497 coresight_register(struct coresight_desc *desc);
498 extern void coresight_unregister(struct coresight_device *csdev);
499 extern int coresight_enable(struct coresight_device *csdev);
500 extern void coresight_disable(struct coresight_device *csdev);
501 extern int coresight_timeout(struct csdev_access *csa, u32 offset,
502 int position, int value);
503
504 extern int coresight_claim_device(struct coresight_device *csdev);
505 extern int coresight_claim_device_unlocked(struct coresight_device *csdev);
506
507 extern void coresight_disclaim_device(struct coresight_device *csdev);
508 extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev);
509 extern char *coresight_alloc_device_name(struct coresight_dev_list *devs,
510 struct device *dev);
511
512 extern bool coresight_loses_context_with_cpu(struct device *dev);
513
514 u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset);
515 u32 coresight_read32(struct coresight_device *csdev, u32 offset);
516 void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset);
517 void coresight_relaxed_write32(struct coresight_device *csdev,
518 u32 val, u32 offset);
519 u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset);
520 u64 coresight_read64(struct coresight_device *csdev, u32 offset);
521 void coresight_relaxed_write64(struct coresight_device *csdev,
522 u64 val, u32 offset);
523 void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset);
524
525 #else
526 static inline struct coresight_device *
coresight_register(struct coresight_desc * desc)527 coresight_register(struct coresight_desc *desc) { return NULL; }
coresight_unregister(struct coresight_device * csdev)528 static inline void coresight_unregister(struct coresight_device *csdev) {}
529 static inline int
coresight_enable(struct coresight_device * csdev)530 coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
coresight_disable(struct coresight_device * csdev)531 static inline void coresight_disable(struct coresight_device *csdev) {}
532
coresight_timeout(struct csdev_access * csa,u32 offset,int position,int value)533 static inline int coresight_timeout(struct csdev_access *csa, u32 offset,
534 int position, int value)
535 {
536 return 1;
537 }
538
coresight_claim_device_unlocked(struct coresight_device * csdev)539 static inline int coresight_claim_device_unlocked(struct coresight_device *csdev)
540 {
541 return -EINVAL;
542 }
543
coresight_claim_device(struct coresight_device * csdev)544 static inline int coresight_claim_device(struct coresight_device *csdev)
545 {
546 return -EINVAL;
547 }
548
coresight_disclaim_device(struct coresight_device * csdev)549 static inline void coresight_disclaim_device(struct coresight_device *csdev) {}
coresight_disclaim_device_unlocked(struct coresight_device * csdev)550 static inline void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {}
551
coresight_loses_context_with_cpu(struct device * dev)552 static inline bool coresight_loses_context_with_cpu(struct device *dev)
553 {
554 return false;
555 }
556
coresight_relaxed_read32(struct coresight_device * csdev,u32 offset)557 static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset)
558 {
559 WARN_ON_ONCE(1);
560 return 0;
561 }
562
coresight_read32(struct coresight_device * csdev,u32 offset)563 static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset)
564 {
565 WARN_ON_ONCE(1);
566 return 0;
567 }
568
coresight_write32(struct coresight_device * csdev,u32 val,u32 offset)569 static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset)
570 {
571 }
572
coresight_relaxed_write32(struct coresight_device * csdev,u32 val,u32 offset)573 static inline void coresight_relaxed_write32(struct coresight_device *csdev,
574 u32 val, u32 offset)
575 {
576 }
577
coresight_relaxed_read64(struct coresight_device * csdev,u32 offset)578 static inline u64 coresight_relaxed_read64(struct coresight_device *csdev,
579 u32 offset)
580 {
581 WARN_ON_ONCE(1);
582 return 0;
583 }
584
coresight_read64(struct coresight_device * csdev,u32 offset)585 static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset)
586 {
587 WARN_ON_ONCE(1);
588 return 0;
589 }
590
coresight_relaxed_write64(struct coresight_device * csdev,u64 val,u32 offset)591 static inline void coresight_relaxed_write64(struct coresight_device *csdev,
592 u64 val, u32 offset)
593 {
594 }
595
coresight_write64(struct coresight_device * csdev,u64 val,u32 offset)596 static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset)
597 {
598 }
599
600 #endif /* IS_ENABLED(CONFIG_CORESIGHT) */
601
602 extern int coresight_get_cpu(struct device *dev);
603
604 struct coresight_platform_data *coresight_get_platform_data(struct device *dev);
605
606 #endif /* _LINUX_COREISGHT_H */
607