1 /***************************************************************************
2 
3    Copyright Echo Digital Audio Corporation (c) 1998 - 2004
4    All rights reserved
5    www.echoaudio.com
6 
7    This file is part of Echo Digital Audio's generic driver library.
8 
9    Echo Digital Audio's generic driver library is free software;
10    you can redistribute it and/or modify it under the terms of
11    the GNU General Public License as published by the Free Software
12    Foundation.
13 
14    This program is distributed in the hope that it will be useful,
15    but WITHOUT ANY WARRANTY; without even the implied warranty of
16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17    GNU General Public License for more details.
18 
19    You should have received a copy of the GNU General Public License
20    along with this program; if not, write to the Free Software
21    Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22    MA  02111-1307, USA.
23 
24    *************************************************************************
25 
26  Translation from C++ and adaptation for use in ALSA-Driver
27  were made by Giuliano Pochini <pochini@shiny.it>
28 
29 ****************************************************************************/
30 
31 
init_hw(struct echoaudio * chip,u16 device_id,u16 subdevice_id)32 static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
33 {
34 	int err;
35 
36 	if (snd_BUG_ON((subdevice_id & 0xfff0) != DARLA24))
37 		return -ENODEV;
38 
39 	err = init_dsp_comm_page(chip);
40 	if (err) {
41 		dev_err(chip->card->dev,
42 			"init_hw: could not initialize DSP comm page\n");
43 		return err;
44 	}
45 
46 	chip->device_id = device_id;
47 	chip->subdevice_id = subdevice_id;
48 	chip->bad_board = true;
49 	chip->dsp_code_to_load = FW_DARLA24_DSP;
50 	/* Since this card has no ASIC, mark it as loaded so everything
51 	   works OK */
52 	chip->asic_loaded = true;
53 	chip->input_clock_types = ECHO_CLOCK_BIT_INTERNAL |
54 		ECHO_CLOCK_BIT_ESYNC;
55 
56 	err = load_firmware(chip);
57 	if (err < 0)
58 		return err;
59 	chip->bad_board = false;
60 
61 	return err;
62 }
63 
64 
65 
set_mixer_defaults(struct echoaudio * chip)66 static int set_mixer_defaults(struct echoaudio *chip)
67 {
68 	return init_line_levels(chip);
69 }
70 
71 
72 
detect_input_clocks(const struct echoaudio * chip)73 static u32 detect_input_clocks(const struct echoaudio *chip)
74 {
75 	u32 clocks_from_dsp, clock_bits;
76 
77 	/* Map the DSP clock detect bits to the generic driver clock
78 	   detect bits */
79 	clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
80 
81 	clock_bits = ECHO_CLOCK_BIT_INTERNAL;
82 
83 	if (clocks_from_dsp & GLDM_CLOCK_DETECT_BIT_ESYNC)
84 		clock_bits |= ECHO_CLOCK_BIT_ESYNC;
85 
86 	return clock_bits;
87 }
88 
89 
90 
91 /* The Darla24 has no ASIC. Just do nothing */
load_asic(struct echoaudio * chip)92 static int load_asic(struct echoaudio *chip)
93 {
94 	return 0;
95 }
96 
97 
98 
set_sample_rate(struct echoaudio * chip,u32 rate)99 static int set_sample_rate(struct echoaudio *chip, u32 rate)
100 {
101 	u8 clock;
102 
103 	switch (rate) {
104 	case 96000:
105 		clock = GD24_96000;
106 		break;
107 	case 88200:
108 		clock = GD24_88200;
109 		break;
110 	case 48000:
111 		clock = GD24_48000;
112 		break;
113 	case 44100:
114 		clock = GD24_44100;
115 		break;
116 	case 32000:
117 		clock = GD24_32000;
118 		break;
119 	case 22050:
120 		clock = GD24_22050;
121 		break;
122 	case 16000:
123 		clock = GD24_16000;
124 		break;
125 	case 11025:
126 		clock = GD24_11025;
127 		break;
128 	case 8000:
129 		clock = GD24_8000;
130 		break;
131 	default:
132 		dev_err(chip->card->dev,
133 			"set_sample_rate: Error, invalid sample rate %d\n",
134 			rate);
135 		return -EINVAL;
136 	}
137 
138 	if (wait_handshake(chip))
139 		return -EIO;
140 
141 	dev_dbg(chip->card->dev,
142 		"set_sample_rate: %d clock %d\n", rate, clock);
143 	chip->sample_rate = rate;
144 
145 	/* Override the sample rate if this card is set to Echo sync. */
146 	if (chip->input_clock == ECHO_CLOCK_ESYNC)
147 		clock = GD24_EXT_SYNC;
148 
149 	chip->comm_page->sample_rate = cpu_to_le32(rate);	/* ignored by the DSP ? */
150 	chip->comm_page->gd_clock_state = clock;
151 	clear_handshake(chip);
152 	return send_vector(chip, DSP_VC_SET_GD_AUDIO_STATE);
153 }
154 
155 
156 
set_input_clock(struct echoaudio * chip,u16 clock)157 static int set_input_clock(struct echoaudio *chip, u16 clock)
158 {
159 	if (snd_BUG_ON(clock != ECHO_CLOCK_INTERNAL &&
160 		       clock != ECHO_CLOCK_ESYNC))
161 		return -EINVAL;
162 	chip->input_clock = clock;
163 	return set_sample_rate(chip, chip->sample_rate);
164 }
165 
166