1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 *
4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
6 *
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
21 */
22
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/mutex.h>
33 #include <linux/io.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clocksource.h>
36 #include <linux/time.h>
37 #include <linux/completion.h>
38 #include <linux/acpi.h>
39 #include <linux/pgtable.h>
40
41 #ifdef CONFIG_X86
42 /* for snoop control */
43 #include <asm/set_memory.h>
44 #include <asm/cpufeature.h>
45 #endif
46 #include <sound/core.h>
47 #include <sound/initval.h>
48 #include <sound/hdaudio.h>
49 #include <sound/hda_i915.h>
50 #include <sound/intel-dsp-config.h>
51 #include <linux/vgaarb.h>
52 #include <linux/vga_switcheroo.h>
53 #include <linux/apple-gmux.h>
54 #include <linux/firmware.h>
55 #include <sound/hda_codec.h>
56 #include "hda_controller.h"
57 #include "hda_intel.h"
58
59 #define CREATE_TRACE_POINTS
60 #include "hda_intel_trace.h"
61
62 /* position fix mode */
63 enum {
64 POS_FIX_AUTO,
65 POS_FIX_LPIB,
66 POS_FIX_POSBUF,
67 POS_FIX_VIACOMBO,
68 POS_FIX_COMBO,
69 POS_FIX_SKL,
70 POS_FIX_FIFO,
71 };
72
73 /* Defines for ATI HD Audio support in SB450 south bridge */
74 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
75 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
76
77 /* Defines for Nvidia HDA support */
78 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
79 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
80 #define NVIDIA_HDA_ISTRM_COH 0x4d
81 #define NVIDIA_HDA_OSTRM_COH 0x4c
82 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
83
84 /* Defines for Intel SCH HDA snoop control */
85 #define INTEL_HDA_CGCTL 0x48
86 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
87 #define INTEL_SCH_HDA_DEVC 0x78
88 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
89
90 /* max number of SDs */
91 /* ICH, ATI and VIA have 4 playback and 4 capture */
92 #define ICH6_NUM_CAPTURE 4
93 #define ICH6_NUM_PLAYBACK 4
94
95 /* ULI has 6 playback and 5 capture */
96 #define ULI_NUM_CAPTURE 5
97 #define ULI_NUM_PLAYBACK 6
98
99 /* ATI HDMI may have up to 8 playbacks and 0 capture */
100 #define ATIHDMI_NUM_CAPTURE 0
101 #define ATIHDMI_NUM_PLAYBACK 8
102
103
104 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
105 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
106 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
107 static char *model[SNDRV_CARDS];
108 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
109 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
110 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
111 static int probe_only[SNDRV_CARDS];
112 static int jackpoll_ms[SNDRV_CARDS];
113 static int single_cmd = -1;
114 static int enable_msi = -1;
115 #ifdef CONFIG_SND_HDA_PATCH_LOADER
116 static char *patch[SNDRV_CARDS];
117 #endif
118 #ifdef CONFIG_SND_HDA_INPUT_BEEP
119 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
120 CONFIG_SND_HDA_INPUT_BEEP_MODE};
121 #endif
122 static bool dmic_detect = 1;
123 static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0;
124
125 module_param_array(index, int, NULL, 0444);
126 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
127 module_param_array(id, charp, NULL, 0444);
128 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
129 module_param_array(enable, bool, NULL, 0444);
130 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
131 module_param_array(model, charp, NULL, 0444);
132 MODULE_PARM_DESC(model, "Use the given board model.");
133 module_param_array(position_fix, int, NULL, 0444);
134 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
135 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
136 module_param_array(bdl_pos_adj, int, NULL, 0644);
137 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
138 module_param_array(probe_mask, int, NULL, 0444);
139 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
140 module_param_array(probe_only, int, NULL, 0444);
141 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
142 module_param_array(jackpoll_ms, int, NULL, 0444);
143 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
144 module_param(single_cmd, bint, 0444);
145 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
146 "(for debugging only).");
147 module_param(enable_msi, bint, 0444);
148 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
149 #ifdef CONFIG_SND_HDA_PATCH_LOADER
150 module_param_array(patch, charp, NULL, 0444);
151 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
152 #endif
153 #ifdef CONFIG_SND_HDA_INPUT_BEEP
154 module_param_array(beep_mode, bool, NULL, 0444);
155 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
156 "(0=off, 1=on) (default=1).");
157 #endif
158 module_param(dmic_detect, bool, 0444);
159 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
160 "(0=off, 1=on) (default=1); "
161 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
162 module_param(ctl_dev_id, bool, 0444);
163 MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address).");
164
165 #ifdef CONFIG_PM
166 static int param_set_xint(const char *val, const struct kernel_param *kp);
167 static const struct kernel_param_ops param_ops_xint = {
168 .set = param_set_xint,
169 .get = param_get_int,
170 };
171 #define param_check_xint param_check_int
172
173 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
174 module_param(power_save, xint, 0644);
175 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
176 "(in second, 0 = disable).");
177
178 static bool pm_blacklist = true;
179 module_param(pm_blacklist, bool, 0644);
180 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
181
182 /* reset the HD-audio controller in power save mode.
183 * this may give more power-saving, but will take longer time to
184 * wake up.
185 */
186 static bool power_save_controller = 1;
187 module_param(power_save_controller, bool, 0644);
188 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
189 #else
190 #define power_save 0
191 #endif /* CONFIG_PM */
192
193 static int align_buffer_size = -1;
194 module_param(align_buffer_size, bint, 0644);
195 MODULE_PARM_DESC(align_buffer_size,
196 "Force buffer and period sizes to be multiple of 128 bytes.");
197
198 #ifdef CONFIG_X86
199 static int hda_snoop = -1;
200 module_param_named(snoop, hda_snoop, bint, 0444);
201 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
202 #else
203 #define hda_snoop true
204 #endif
205
206
207 MODULE_LICENSE("GPL");
208 MODULE_DESCRIPTION("Intel HDA driver");
209
210 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
211 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
212 #define SUPPORT_VGA_SWITCHEROO
213 #endif
214 #endif
215
216
217 /*
218 */
219
220 /* driver types */
221 enum {
222 AZX_DRIVER_ICH,
223 AZX_DRIVER_PCH,
224 AZX_DRIVER_SCH,
225 AZX_DRIVER_SKL,
226 AZX_DRIVER_HDMI,
227 AZX_DRIVER_ATI,
228 AZX_DRIVER_ATIHDMI,
229 AZX_DRIVER_ATIHDMI_NS,
230 AZX_DRIVER_VIA,
231 AZX_DRIVER_SIS,
232 AZX_DRIVER_ULI,
233 AZX_DRIVER_NVIDIA,
234 AZX_DRIVER_TERA,
235 AZX_DRIVER_CTX,
236 AZX_DRIVER_CTHDA,
237 AZX_DRIVER_CMEDIA,
238 AZX_DRIVER_ZHAOXIN,
239 AZX_DRIVER_GENERIC,
240 AZX_NUM_DRIVERS, /* keep this as last entry */
241 };
242
243 #define azx_get_snoop_type(chip) \
244 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
245 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
246
247 /* quirks for old Intel chipsets */
248 #define AZX_DCAPS_INTEL_ICH \
249 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
250
251 /* quirks for Intel PCH */
252 #define AZX_DCAPS_INTEL_PCH_BASE \
253 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
254 AZX_DCAPS_SNOOP_TYPE(SCH))
255
256 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
257 #define AZX_DCAPS_INTEL_PCH_NOPM \
258 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
259
260 /* PCH for HSW/BDW; with runtime PM */
261 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
262 #define AZX_DCAPS_INTEL_PCH \
263 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
264
265 /* HSW HDMI */
266 #define AZX_DCAPS_INTEL_HASWELL \
267 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
268 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
269 AZX_DCAPS_SNOOP_TYPE(SCH))
270
271 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
272 #define AZX_DCAPS_INTEL_BROADWELL \
273 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
274 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
275 AZX_DCAPS_SNOOP_TYPE(SCH))
276
277 #define AZX_DCAPS_INTEL_BAYTRAIL \
278 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
279
280 #define AZX_DCAPS_INTEL_BRASWELL \
281 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
282 AZX_DCAPS_I915_COMPONENT)
283
284 #define AZX_DCAPS_INTEL_SKYLAKE \
285 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
286 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
287
288 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
289
290 /* quirks for ATI SB / AMD Hudson */
291 #define AZX_DCAPS_PRESET_ATI_SB \
292 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
293 AZX_DCAPS_SNOOP_TYPE(ATI))
294
295 /* quirks for ATI/AMD HDMI */
296 #define AZX_DCAPS_PRESET_ATI_HDMI \
297 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
298 AZX_DCAPS_NO_MSI64)
299
300 /* quirks for ATI HDMI with snoop off */
301 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
302 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
303
304 /* quirks for AMD SB */
305 #define AZX_DCAPS_PRESET_AMD_SB \
306 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
307 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
308 AZX_DCAPS_RETRY_PROBE)
309
310 /* quirks for Nvidia */
311 #define AZX_DCAPS_PRESET_NVIDIA \
312 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
313 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
314
315 #define AZX_DCAPS_PRESET_CTHDA \
316 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
317 AZX_DCAPS_NO_64BIT |\
318 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
319
320 /*
321 * vga_switcheroo support
322 */
323 #ifdef SUPPORT_VGA_SWITCHEROO
324 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
325 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
326 #else
327 #define use_vga_switcheroo(chip) 0
328 #define needs_eld_notify_link(chip) false
329 #endif
330
331 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
332 ((pci)->device == 0x0c0c) || \
333 ((pci)->device == 0x0d0c) || \
334 ((pci)->device == 0x160c) || \
335 ((pci)->device == 0x490d) || \
336 ((pci)->device == 0x4f90) || \
337 ((pci)->device == 0x4f91) || \
338 ((pci)->device == 0x4f92))
339
340 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
341
342 static const char * const driver_short_names[] = {
343 [AZX_DRIVER_ICH] = "HDA Intel",
344 [AZX_DRIVER_PCH] = "HDA Intel PCH",
345 [AZX_DRIVER_SCH] = "HDA Intel MID",
346 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
347 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
348 [AZX_DRIVER_ATI] = "HDA ATI SB",
349 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
350 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
351 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
352 [AZX_DRIVER_SIS] = "HDA SIS966",
353 [AZX_DRIVER_ULI] = "HDA ULI M5461",
354 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
355 [AZX_DRIVER_TERA] = "HDA Teradici",
356 [AZX_DRIVER_CTX] = "HDA Creative",
357 [AZX_DRIVER_CTHDA] = "HDA Creative",
358 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
359 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
360 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
361 };
362
363 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
364 static void set_default_power_save(struct azx *chip);
365
366 /*
367 * initialize the PCI registers
368 */
369 /* update bits in a PCI register byte */
update_pci_byte(struct pci_dev * pci,unsigned int reg,unsigned char mask,unsigned char val)370 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
371 unsigned char mask, unsigned char val)
372 {
373 unsigned char data;
374
375 pci_read_config_byte(pci, reg, &data);
376 data &= ~mask;
377 data |= (val & mask);
378 pci_write_config_byte(pci, reg, data);
379 }
380
azx_init_pci(struct azx * chip)381 static void azx_init_pci(struct azx *chip)
382 {
383 int snoop_type = azx_get_snoop_type(chip);
384
385 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
386 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
387 * Ensuring these bits are 0 clears playback static on some HD Audio
388 * codecs.
389 * The PCI register TCSEL is defined in the Intel manuals.
390 */
391 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
392 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
393 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
394 }
395
396 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
397 * we need to enable snoop.
398 */
399 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
400 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
401 azx_snoop(chip));
402 update_pci_byte(chip->pci,
403 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
404 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
405 }
406
407 /* For NVIDIA HDA, enable snoop */
408 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
409 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
410 azx_snoop(chip));
411 update_pci_byte(chip->pci,
412 NVIDIA_HDA_TRANSREG_ADDR,
413 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
414 update_pci_byte(chip->pci,
415 NVIDIA_HDA_ISTRM_COH,
416 0x01, NVIDIA_HDA_ENABLE_COHBIT);
417 update_pci_byte(chip->pci,
418 NVIDIA_HDA_OSTRM_COH,
419 0x01, NVIDIA_HDA_ENABLE_COHBIT);
420 }
421
422 /* Enable SCH/PCH snoop if needed */
423 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
424 unsigned short snoop;
425 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
426 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
427 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
428 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
429 if (!azx_snoop(chip))
430 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
431 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
432 pci_read_config_word(chip->pci,
433 INTEL_SCH_HDA_DEVC, &snoop);
434 }
435 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
436 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
437 "Disabled" : "Enabled");
438 }
439 }
440
441 /*
442 * In BXT-P A0, HD-Audio DMA requests is later than expected,
443 * and makes an audio stream sensitive to system latencies when
444 * 24/32 bits are playing.
445 * Adjusting threshold of DMA fifo to force the DMA request
446 * sooner to improve latency tolerance at the expense of power.
447 */
bxt_reduce_dma_latency(struct azx * chip)448 static void bxt_reduce_dma_latency(struct azx *chip)
449 {
450 u32 val;
451
452 val = azx_readl(chip, VS_EM4L);
453 val &= (0x3 << 20);
454 azx_writel(chip, VS_EM4L, val);
455 }
456
457 /*
458 * ML_LCAP bits:
459 * bit 0: 6 MHz Supported
460 * bit 1: 12 MHz Supported
461 * bit 2: 24 MHz Supported
462 * bit 3: 48 MHz Supported
463 * bit 4: 96 MHz Supported
464 * bit 5: 192 MHz Supported
465 */
intel_get_lctl_scf(struct azx * chip)466 static int intel_get_lctl_scf(struct azx *chip)
467 {
468 struct hdac_bus *bus = azx_bus(chip);
469 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
470 u32 val, t;
471 int i;
472
473 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
474
475 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
476 t = preferred_bits[i];
477 if (val & (1 << t))
478 return t;
479 }
480
481 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
482 return 0;
483 }
484
intel_ml_lctl_set_power(struct azx * chip,int state)485 static int intel_ml_lctl_set_power(struct azx *chip, int state)
486 {
487 struct hdac_bus *bus = azx_bus(chip);
488 u32 val;
489 int timeout;
490
491 /*
492 * Changes to LCTL.SCF are only needed for the first multi-link dealing
493 * with external codecs
494 */
495 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
496 val &= ~AZX_ML_LCTL_SPA;
497 val |= state << AZX_ML_LCTL_SPA_SHIFT;
498 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
499 /* wait for CPA */
500 timeout = 50;
501 while (timeout) {
502 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
503 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT))
504 return 0;
505 timeout--;
506 udelay(10);
507 }
508
509 return -1;
510 }
511
intel_init_lctl(struct azx * chip)512 static void intel_init_lctl(struct azx *chip)
513 {
514 struct hdac_bus *bus = azx_bus(chip);
515 u32 val;
516 int ret;
517
518 /* 0. check lctl register value is correct or not */
519 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
520 /* only perform additional configurations if the SCF is initially based on 6MHz */
521 if ((val & AZX_ML_LCTL_SCF) != 0)
522 return;
523
524 /*
525 * Before operating on SPA, CPA must match SPA.
526 * Any deviation may result in undefined behavior.
527 */
528 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) !=
529 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT))
530 return;
531
532 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
533 ret = intel_ml_lctl_set_power(chip, 0);
534 udelay(100);
535 if (ret)
536 goto set_spa;
537
538 /* 2. update SCF to select an audio clock different from 6MHz */
539 val &= ~AZX_ML_LCTL_SCF;
540 val |= intel_get_lctl_scf(chip);
541 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
542
543 set_spa:
544 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
545 intel_ml_lctl_set_power(chip, 1);
546 udelay(100);
547 }
548
hda_intel_init_chip(struct azx * chip,bool full_reset)549 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
550 {
551 struct hdac_bus *bus = azx_bus(chip);
552 struct pci_dev *pci = chip->pci;
553 u32 val;
554
555 snd_hdac_set_codec_wakeup(bus, true);
556 if (chip->driver_type == AZX_DRIVER_SKL) {
557 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
558 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
559 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
560 }
561 azx_init_chip(chip, full_reset);
562 if (chip->driver_type == AZX_DRIVER_SKL) {
563 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
564 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
565 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
566 }
567
568 snd_hdac_set_codec_wakeup(bus, false);
569
570 /* reduce dma latency to avoid noise */
571 if (IS_BXT(pci))
572 bxt_reduce_dma_latency(chip);
573
574 if (bus->mlcap != NULL)
575 intel_init_lctl(chip);
576 }
577
578 /* calculate runtime delay from LPIB */
azx_get_delay_from_lpib(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)579 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
580 unsigned int pos)
581 {
582 struct snd_pcm_substream *substream = azx_dev->core.substream;
583 int stream = substream->stream;
584 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
585 int delay;
586
587 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
588 delay = pos - lpib_pos;
589 else
590 delay = lpib_pos - pos;
591 if (delay < 0) {
592 if (delay >= azx_dev->core.delay_negative_threshold)
593 delay = 0;
594 else
595 delay += azx_dev->core.bufsize;
596 }
597
598 if (delay >= azx_dev->core.period_bytes) {
599 dev_info(chip->card->dev,
600 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
601 delay, azx_dev->core.period_bytes);
602 delay = 0;
603 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
604 chip->get_delay[stream] = NULL;
605 }
606
607 return bytes_to_frames(substream->runtime, delay);
608 }
609
610 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
611
612 /* called from IRQ */
azx_position_check(struct azx * chip,struct azx_dev * azx_dev)613 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
614 {
615 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
616 int ok;
617
618 ok = azx_position_ok(chip, azx_dev);
619 if (ok == 1) {
620 azx_dev->irq_pending = 0;
621 return ok;
622 } else if (ok == 0) {
623 /* bogus IRQ, process it later */
624 azx_dev->irq_pending = 1;
625 schedule_work(&hda->irq_pending_work);
626 }
627 return 0;
628 }
629
630 #define display_power(chip, enable) \
631 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
632
633 /*
634 * Check whether the current DMA position is acceptable for updating
635 * periods. Returns non-zero if it's OK.
636 *
637 * Many HD-audio controllers appear pretty inaccurate about
638 * the update-IRQ timing. The IRQ is issued before actually the
639 * data is processed. So, we need to process it afterwords in a
640 * workqueue.
641 *
642 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
643 */
azx_position_ok(struct azx * chip,struct azx_dev * azx_dev)644 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
645 {
646 struct snd_pcm_substream *substream = azx_dev->core.substream;
647 struct snd_pcm_runtime *runtime = substream->runtime;
648 int stream = substream->stream;
649 u32 wallclk;
650 unsigned int pos;
651 snd_pcm_uframes_t hwptr, target;
652
653 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
654 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
655 return -1; /* bogus (too early) interrupt */
656
657 if (chip->get_position[stream])
658 pos = chip->get_position[stream](chip, azx_dev);
659 else { /* use the position buffer as default */
660 pos = azx_get_pos_posbuf(chip, azx_dev);
661 if (!pos || pos == (u32)-1) {
662 dev_info(chip->card->dev,
663 "Invalid position buffer, using LPIB read method instead.\n");
664 chip->get_position[stream] = azx_get_pos_lpib;
665 if (chip->get_position[0] == azx_get_pos_lpib &&
666 chip->get_position[1] == azx_get_pos_lpib)
667 azx_bus(chip)->use_posbuf = false;
668 pos = azx_get_pos_lpib(chip, azx_dev);
669 chip->get_delay[stream] = NULL;
670 } else {
671 chip->get_position[stream] = azx_get_pos_posbuf;
672 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
673 chip->get_delay[stream] = azx_get_delay_from_lpib;
674 }
675 }
676
677 if (pos >= azx_dev->core.bufsize)
678 pos = 0;
679
680 if (WARN_ONCE(!azx_dev->core.period_bytes,
681 "hda-intel: zero azx_dev->period_bytes"))
682 return -1; /* this shouldn't happen! */
683 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
684 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
685 /* NG - it's below the first next period boundary */
686 return chip->bdl_pos_adj ? 0 : -1;
687 azx_dev->core.start_wallclk += wallclk;
688
689 if (azx_dev->core.no_period_wakeup)
690 return 1; /* OK, no need to check period boundary */
691
692 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
693 return 1; /* OK, already in hwptr updating process */
694
695 /* check whether the period gets really elapsed */
696 pos = bytes_to_frames(runtime, pos);
697 hwptr = runtime->hw_ptr_base + pos;
698 if (hwptr < runtime->status->hw_ptr)
699 hwptr += runtime->buffer_size;
700 target = runtime->hw_ptr_interrupt + runtime->period_size;
701 if (hwptr < target) {
702 /* too early wakeup, process it later */
703 return chip->bdl_pos_adj ? 0 : -1;
704 }
705
706 return 1; /* OK, it's fine */
707 }
708
709 /*
710 * The work for pending PCM period updates.
711 */
azx_irq_pending_work(struct work_struct * work)712 static void azx_irq_pending_work(struct work_struct *work)
713 {
714 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
715 struct azx *chip = &hda->chip;
716 struct hdac_bus *bus = azx_bus(chip);
717 struct hdac_stream *s;
718 int pending, ok;
719
720 if (!hda->irq_pending_warned) {
721 dev_info(chip->card->dev,
722 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
723 chip->card->number);
724 hda->irq_pending_warned = 1;
725 }
726
727 for (;;) {
728 pending = 0;
729 spin_lock_irq(&bus->reg_lock);
730 list_for_each_entry(s, &bus->stream_list, list) {
731 struct azx_dev *azx_dev = stream_to_azx_dev(s);
732 if (!azx_dev->irq_pending ||
733 !s->substream ||
734 !s->running)
735 continue;
736 ok = azx_position_ok(chip, azx_dev);
737 if (ok > 0) {
738 azx_dev->irq_pending = 0;
739 spin_unlock(&bus->reg_lock);
740 snd_pcm_period_elapsed(s->substream);
741 spin_lock(&bus->reg_lock);
742 } else if (ok < 0) {
743 pending = 0; /* too early */
744 } else
745 pending++;
746 }
747 spin_unlock_irq(&bus->reg_lock);
748 if (!pending)
749 return;
750 msleep(1);
751 }
752 }
753
754 /* clear irq_pending flags and assure no on-going workq */
azx_clear_irq_pending(struct azx * chip)755 static void azx_clear_irq_pending(struct azx *chip)
756 {
757 struct hdac_bus *bus = azx_bus(chip);
758 struct hdac_stream *s;
759
760 spin_lock_irq(&bus->reg_lock);
761 list_for_each_entry(s, &bus->stream_list, list) {
762 struct azx_dev *azx_dev = stream_to_azx_dev(s);
763 azx_dev->irq_pending = 0;
764 }
765 spin_unlock_irq(&bus->reg_lock);
766 }
767
azx_acquire_irq(struct azx * chip,int do_disconnect)768 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
769 {
770 struct hdac_bus *bus = azx_bus(chip);
771
772 if (request_irq(chip->pci->irq, azx_interrupt,
773 chip->msi ? 0 : IRQF_SHARED,
774 chip->card->irq_descr, chip)) {
775 dev_err(chip->card->dev,
776 "unable to grab IRQ %d, disabling device\n",
777 chip->pci->irq);
778 if (do_disconnect)
779 snd_card_disconnect(chip->card);
780 return -1;
781 }
782 bus->irq = chip->pci->irq;
783 chip->card->sync_irq = bus->irq;
784 pci_intx(chip->pci, !chip->msi);
785 return 0;
786 }
787
788 /* get the current DMA position with correction on VIA chips */
azx_via_get_position(struct azx * chip,struct azx_dev * azx_dev)789 static unsigned int azx_via_get_position(struct azx *chip,
790 struct azx_dev *azx_dev)
791 {
792 unsigned int link_pos, mini_pos, bound_pos;
793 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
794 unsigned int fifo_size;
795
796 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
797 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
798 /* Playback, no problem using link position */
799 return link_pos;
800 }
801
802 /* Capture */
803 /* For new chipset,
804 * use mod to get the DMA position just like old chipset
805 */
806 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
807 mod_dma_pos %= azx_dev->core.period_bytes;
808
809 fifo_size = azx_stream(azx_dev)->fifo_size - 1;
810
811 if (azx_dev->insufficient) {
812 /* Link position never gather than FIFO size */
813 if (link_pos <= fifo_size)
814 return 0;
815
816 azx_dev->insufficient = 0;
817 }
818
819 if (link_pos <= fifo_size)
820 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
821 else
822 mini_pos = link_pos - fifo_size;
823
824 /* Find nearest previous boudary */
825 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
826 mod_link_pos = link_pos % azx_dev->core.period_bytes;
827 if (mod_link_pos >= fifo_size)
828 bound_pos = link_pos - mod_link_pos;
829 else if (mod_dma_pos >= mod_mini_pos)
830 bound_pos = mini_pos - mod_mini_pos;
831 else {
832 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
833 if (bound_pos >= azx_dev->core.bufsize)
834 bound_pos = 0;
835 }
836
837 /* Calculate real DMA position we want */
838 return bound_pos + mod_dma_pos;
839 }
840
841 #define AMD_FIFO_SIZE 32
842
843 /* get the current DMA position with FIFO size correction */
azx_get_pos_fifo(struct azx * chip,struct azx_dev * azx_dev)844 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
845 {
846 struct snd_pcm_substream *substream = azx_dev->core.substream;
847 struct snd_pcm_runtime *runtime = substream->runtime;
848 unsigned int pos, delay;
849
850 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
851 if (!runtime)
852 return pos;
853
854 runtime->delay = AMD_FIFO_SIZE;
855 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
856 if (azx_dev->insufficient) {
857 if (pos < delay) {
858 delay = pos;
859 runtime->delay = bytes_to_frames(runtime, pos);
860 } else {
861 azx_dev->insufficient = 0;
862 }
863 }
864
865 /* correct the DMA position for capture stream */
866 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
867 if (pos < delay)
868 pos += azx_dev->core.bufsize;
869 pos -= delay;
870 }
871
872 return pos;
873 }
874
azx_get_delay_from_fifo(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)875 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
876 unsigned int pos)
877 {
878 struct snd_pcm_substream *substream = azx_dev->core.substream;
879
880 /* just read back the calculated value in the above */
881 return substream->runtime->delay;
882 }
883
__azx_shutdown_chip(struct azx * chip,bool skip_link_reset)884 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
885 {
886 azx_stop_chip(chip);
887 if (!skip_link_reset)
888 azx_enter_link_reset(chip);
889 azx_clear_irq_pending(chip);
890 display_power(chip, false);
891 }
892
893 #ifdef CONFIG_PM
894 static DEFINE_MUTEX(card_list_lock);
895 static LIST_HEAD(card_list);
896
azx_shutdown_chip(struct azx * chip)897 static void azx_shutdown_chip(struct azx *chip)
898 {
899 __azx_shutdown_chip(chip, false);
900 }
901
azx_add_card_list(struct azx * chip)902 static void azx_add_card_list(struct azx *chip)
903 {
904 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
905 mutex_lock(&card_list_lock);
906 list_add(&hda->list, &card_list);
907 mutex_unlock(&card_list_lock);
908 }
909
azx_del_card_list(struct azx * chip)910 static void azx_del_card_list(struct azx *chip)
911 {
912 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
913 mutex_lock(&card_list_lock);
914 list_del_init(&hda->list);
915 mutex_unlock(&card_list_lock);
916 }
917
918 /* trigger power-save check at writing parameter */
param_set_xint(const char * val,const struct kernel_param * kp)919 static int param_set_xint(const char *val, const struct kernel_param *kp)
920 {
921 struct hda_intel *hda;
922 struct azx *chip;
923 int prev = power_save;
924 int ret = param_set_int(val, kp);
925
926 if (ret || prev == power_save)
927 return ret;
928
929 mutex_lock(&card_list_lock);
930 list_for_each_entry(hda, &card_list, list) {
931 chip = &hda->chip;
932 if (!hda->probe_continued || chip->disabled)
933 continue;
934 snd_hda_set_power_save(&chip->bus, power_save * 1000);
935 }
936 mutex_unlock(&card_list_lock);
937 return 0;
938 }
939
940 /*
941 * power management
942 */
azx_is_pm_ready(struct snd_card * card)943 static bool azx_is_pm_ready(struct snd_card *card)
944 {
945 struct azx *chip;
946 struct hda_intel *hda;
947
948 if (!card)
949 return false;
950 chip = card->private_data;
951 hda = container_of(chip, struct hda_intel, chip);
952 if (chip->disabled || hda->init_failed || !chip->running)
953 return false;
954 return true;
955 }
956
__azx_runtime_resume(struct azx * chip)957 static void __azx_runtime_resume(struct azx *chip)
958 {
959 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
960 struct hdac_bus *bus = azx_bus(chip);
961 struct hda_codec *codec;
962 int status;
963
964 display_power(chip, true);
965 if (hda->need_i915_power)
966 snd_hdac_i915_set_bclk(bus);
967
968 /* Read STATESTS before controller reset */
969 status = azx_readw(chip, STATESTS);
970
971 azx_init_pci(chip);
972 hda_intel_init_chip(chip, true);
973
974 /* Avoid codec resume if runtime resume is for system suspend */
975 if (!chip->pm_prepared) {
976 list_for_each_codec(codec, &chip->bus) {
977 if (codec->relaxed_resume)
978 continue;
979
980 if (codec->forced_resume || (status & (1 << codec->addr)))
981 pm_request_resume(hda_codec_dev(codec));
982 }
983 }
984
985 /* power down again for link-controlled chips */
986 if (!hda->need_i915_power)
987 display_power(chip, false);
988 }
989
990 #ifdef CONFIG_PM_SLEEP
azx_prepare(struct device * dev)991 static int azx_prepare(struct device *dev)
992 {
993 struct snd_card *card = dev_get_drvdata(dev);
994 struct azx *chip;
995
996 if (!azx_is_pm_ready(card))
997 return 0;
998
999 chip = card->private_data;
1000 chip->pm_prepared = 1;
1001 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1002
1003 flush_work(&azx_bus(chip)->unsol_work);
1004
1005 /* HDA controller always requires different WAKEEN for runtime suspend
1006 * and system suspend, so don't use direct-complete here.
1007 */
1008 return 0;
1009 }
1010
azx_complete(struct device * dev)1011 static void azx_complete(struct device *dev)
1012 {
1013 struct snd_card *card = dev_get_drvdata(dev);
1014 struct azx *chip;
1015
1016 if (!azx_is_pm_ready(card))
1017 return;
1018
1019 chip = card->private_data;
1020 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1021 chip->pm_prepared = 0;
1022 }
1023
azx_suspend(struct device * dev)1024 static int azx_suspend(struct device *dev)
1025 {
1026 struct snd_card *card = dev_get_drvdata(dev);
1027 struct azx *chip;
1028 struct hdac_bus *bus;
1029
1030 if (!azx_is_pm_ready(card))
1031 return 0;
1032
1033 chip = card->private_data;
1034 bus = azx_bus(chip);
1035 azx_shutdown_chip(chip);
1036 if (bus->irq >= 0) {
1037 free_irq(bus->irq, chip);
1038 bus->irq = -1;
1039 chip->card->sync_irq = -1;
1040 }
1041
1042 if (chip->msi)
1043 pci_disable_msi(chip->pci);
1044
1045 trace_azx_suspend(chip);
1046 return 0;
1047 }
1048
azx_resume(struct device * dev)1049 static int azx_resume(struct device *dev)
1050 {
1051 struct snd_card *card = dev_get_drvdata(dev);
1052 struct azx *chip;
1053
1054 if (!azx_is_pm_ready(card))
1055 return 0;
1056
1057 chip = card->private_data;
1058 if (chip->msi)
1059 if (pci_enable_msi(chip->pci) < 0)
1060 chip->msi = 0;
1061 if (azx_acquire_irq(chip, 1) < 0)
1062 return -EIO;
1063
1064 __azx_runtime_resume(chip);
1065
1066 trace_azx_resume(chip);
1067 return 0;
1068 }
1069
1070 /* put codec down to D3 at hibernation for Intel SKL+;
1071 * otherwise BIOS may still access the codec and screw up the driver
1072 */
azx_freeze_noirq(struct device * dev)1073 static int azx_freeze_noirq(struct device *dev)
1074 {
1075 struct snd_card *card = dev_get_drvdata(dev);
1076 struct azx *chip = card->private_data;
1077 struct pci_dev *pci = to_pci_dev(dev);
1078
1079 if (!azx_is_pm_ready(card))
1080 return 0;
1081 if (chip->driver_type == AZX_DRIVER_SKL)
1082 pci_set_power_state(pci, PCI_D3hot);
1083
1084 return 0;
1085 }
1086
azx_thaw_noirq(struct device * dev)1087 static int azx_thaw_noirq(struct device *dev)
1088 {
1089 struct snd_card *card = dev_get_drvdata(dev);
1090 struct azx *chip = card->private_data;
1091 struct pci_dev *pci = to_pci_dev(dev);
1092
1093 if (!azx_is_pm_ready(card))
1094 return 0;
1095 if (chip->driver_type == AZX_DRIVER_SKL)
1096 pci_set_power_state(pci, PCI_D0);
1097
1098 return 0;
1099 }
1100 #endif /* CONFIG_PM_SLEEP */
1101
azx_runtime_suspend(struct device * dev)1102 static int azx_runtime_suspend(struct device *dev)
1103 {
1104 struct snd_card *card = dev_get_drvdata(dev);
1105 struct azx *chip;
1106
1107 if (!azx_is_pm_ready(card))
1108 return 0;
1109 chip = card->private_data;
1110
1111 /* enable controller wake up event */
1112 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
1113
1114 azx_shutdown_chip(chip);
1115 trace_azx_runtime_suspend(chip);
1116 return 0;
1117 }
1118
azx_runtime_resume(struct device * dev)1119 static int azx_runtime_resume(struct device *dev)
1120 {
1121 struct snd_card *card = dev_get_drvdata(dev);
1122 struct azx *chip;
1123
1124 if (!azx_is_pm_ready(card))
1125 return 0;
1126 chip = card->private_data;
1127 __azx_runtime_resume(chip);
1128
1129 /* disable controller Wake Up event*/
1130 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
1131
1132 trace_azx_runtime_resume(chip);
1133 return 0;
1134 }
1135
azx_runtime_idle(struct device * dev)1136 static int azx_runtime_idle(struct device *dev)
1137 {
1138 struct snd_card *card = dev_get_drvdata(dev);
1139 struct azx *chip;
1140 struct hda_intel *hda;
1141
1142 if (!card)
1143 return 0;
1144
1145 chip = card->private_data;
1146 hda = container_of(chip, struct hda_intel, chip);
1147 if (chip->disabled || hda->init_failed)
1148 return 0;
1149
1150 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1151 azx_bus(chip)->codec_powered || !chip->running)
1152 return -EBUSY;
1153
1154 /* ELD notification gets broken when HD-audio bus is off */
1155 if (needs_eld_notify_link(chip))
1156 return -EBUSY;
1157
1158 return 0;
1159 }
1160
1161 static const struct dev_pm_ops azx_pm = {
1162 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1163 #ifdef CONFIG_PM_SLEEP
1164 .prepare = azx_prepare,
1165 .complete = azx_complete,
1166 .freeze_noirq = azx_freeze_noirq,
1167 .thaw_noirq = azx_thaw_noirq,
1168 #endif
1169 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1170 };
1171
1172 #define AZX_PM_OPS &azx_pm
1173 #else
1174 #define azx_add_card_list(chip) /* NOP */
1175 #define azx_del_card_list(chip) /* NOP */
1176 #define AZX_PM_OPS NULL
1177 #endif /* CONFIG_PM */
1178
1179
1180 static int azx_probe_continue(struct azx *chip);
1181
1182 #ifdef SUPPORT_VGA_SWITCHEROO
1183 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1184
azx_vs_set_state(struct pci_dev * pci,enum vga_switcheroo_state state)1185 static void azx_vs_set_state(struct pci_dev *pci,
1186 enum vga_switcheroo_state state)
1187 {
1188 struct snd_card *card = pci_get_drvdata(pci);
1189 struct azx *chip = card->private_data;
1190 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1191 struct hda_codec *codec;
1192 bool disabled;
1193
1194 wait_for_completion(&hda->probe_wait);
1195 if (hda->init_failed)
1196 return;
1197
1198 disabled = (state == VGA_SWITCHEROO_OFF);
1199 if (chip->disabled == disabled)
1200 return;
1201
1202 if (!hda->probe_continued) {
1203 chip->disabled = disabled;
1204 if (!disabled) {
1205 dev_info(chip->card->dev,
1206 "Start delayed initialization\n");
1207 if (azx_probe_continue(chip) < 0)
1208 dev_err(chip->card->dev, "initialization error\n");
1209 }
1210 } else {
1211 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1212 disabled ? "Disabling" : "Enabling");
1213 if (disabled) {
1214 list_for_each_codec(codec, &chip->bus) {
1215 pm_runtime_suspend(hda_codec_dev(codec));
1216 pm_runtime_disable(hda_codec_dev(codec));
1217 }
1218 pm_runtime_suspend(card->dev);
1219 pm_runtime_disable(card->dev);
1220 /* when we get suspended by vga_switcheroo we end up in D3cold,
1221 * however we have no ACPI handle, so pci/acpi can't put us there,
1222 * put ourselves there */
1223 pci->current_state = PCI_D3cold;
1224 chip->disabled = true;
1225 if (snd_hda_lock_devices(&chip->bus))
1226 dev_warn(chip->card->dev,
1227 "Cannot lock devices!\n");
1228 } else {
1229 snd_hda_unlock_devices(&chip->bus);
1230 chip->disabled = false;
1231 pm_runtime_enable(card->dev);
1232 list_for_each_codec(codec, &chip->bus) {
1233 pm_runtime_enable(hda_codec_dev(codec));
1234 pm_runtime_resume(hda_codec_dev(codec));
1235 }
1236 }
1237 }
1238 }
1239
azx_vs_can_switch(struct pci_dev * pci)1240 static bool azx_vs_can_switch(struct pci_dev *pci)
1241 {
1242 struct snd_card *card = pci_get_drvdata(pci);
1243 struct azx *chip = card->private_data;
1244 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1245
1246 wait_for_completion(&hda->probe_wait);
1247 if (hda->init_failed)
1248 return false;
1249 if (chip->disabled || !hda->probe_continued)
1250 return true;
1251 if (snd_hda_lock_devices(&chip->bus))
1252 return false;
1253 snd_hda_unlock_devices(&chip->bus);
1254 return true;
1255 }
1256
1257 /*
1258 * The discrete GPU cannot power down unless the HDA controller runtime
1259 * suspends, so activate runtime PM on codecs even if power_save == 0.
1260 */
setup_vga_switcheroo_runtime_pm(struct azx * chip)1261 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1262 {
1263 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1264 struct hda_codec *codec;
1265
1266 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1267 list_for_each_codec(codec, &chip->bus)
1268 codec->auto_runtime_pm = 1;
1269 /* reset the power save setup */
1270 if (chip->running)
1271 set_default_power_save(chip);
1272 }
1273 }
1274
azx_vs_gpu_bound(struct pci_dev * pci,enum vga_switcheroo_client_id client_id)1275 static void azx_vs_gpu_bound(struct pci_dev *pci,
1276 enum vga_switcheroo_client_id client_id)
1277 {
1278 struct snd_card *card = pci_get_drvdata(pci);
1279 struct azx *chip = card->private_data;
1280
1281 if (client_id == VGA_SWITCHEROO_DIS)
1282 chip->bus.keep_power = 0;
1283 setup_vga_switcheroo_runtime_pm(chip);
1284 }
1285
init_vga_switcheroo(struct azx * chip)1286 static void init_vga_switcheroo(struct azx *chip)
1287 {
1288 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1289 struct pci_dev *p = get_bound_vga(chip->pci);
1290 struct pci_dev *parent;
1291 if (p) {
1292 dev_info(chip->card->dev,
1293 "Handle vga_switcheroo audio client\n");
1294 hda->use_vga_switcheroo = 1;
1295
1296 /* cleared in either gpu_bound op or codec probe, or when its
1297 * upstream port has _PR3 (i.e. dGPU).
1298 */
1299 parent = pci_upstream_bridge(p);
1300 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1301 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1302 pci_dev_put(p);
1303 }
1304 }
1305
1306 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1307 .set_gpu_state = azx_vs_set_state,
1308 .can_switch = azx_vs_can_switch,
1309 .gpu_bound = azx_vs_gpu_bound,
1310 };
1311
register_vga_switcheroo(struct azx * chip)1312 static int register_vga_switcheroo(struct azx *chip)
1313 {
1314 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1315 struct pci_dev *p;
1316 int err;
1317
1318 if (!hda->use_vga_switcheroo)
1319 return 0;
1320
1321 p = get_bound_vga(chip->pci);
1322 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1323 pci_dev_put(p);
1324
1325 if (err < 0)
1326 return err;
1327 hda->vga_switcheroo_registered = 1;
1328
1329 return 0;
1330 }
1331 #else
1332 #define init_vga_switcheroo(chip) /* NOP */
1333 #define register_vga_switcheroo(chip) 0
1334 #define check_hdmi_disabled(pci) false
1335 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
1336 #endif /* SUPPORT_VGA_SWITCHER */
1337
1338 /*
1339 * destructor
1340 */
azx_free(struct azx * chip)1341 static void azx_free(struct azx *chip)
1342 {
1343 struct pci_dev *pci = chip->pci;
1344 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1345 struct hdac_bus *bus = azx_bus(chip);
1346
1347 if (hda->freed)
1348 return;
1349
1350 if (azx_has_pm_runtime(chip) && chip->running) {
1351 pm_runtime_get_noresume(&pci->dev);
1352 pm_runtime_forbid(&pci->dev);
1353 pm_runtime_dont_use_autosuspend(&pci->dev);
1354 }
1355
1356 chip->running = 0;
1357
1358 azx_del_card_list(chip);
1359
1360 hda->init_failed = 1; /* to be sure */
1361 complete_all(&hda->probe_wait);
1362
1363 if (use_vga_switcheroo(hda)) {
1364 if (chip->disabled && hda->probe_continued)
1365 snd_hda_unlock_devices(&chip->bus);
1366 if (hda->vga_switcheroo_registered)
1367 vga_switcheroo_unregister_client(chip->pci);
1368 }
1369
1370 if (bus->chip_init) {
1371 azx_clear_irq_pending(chip);
1372 azx_stop_all_streams(chip);
1373 azx_stop_chip(chip);
1374 }
1375
1376 if (bus->irq >= 0)
1377 free_irq(bus->irq, (void*)chip);
1378
1379 azx_free_stream_pages(chip);
1380 azx_free_streams(chip);
1381 snd_hdac_bus_exit(bus);
1382
1383 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1384 release_firmware(chip->fw);
1385 #endif
1386 display_power(chip, false);
1387
1388 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1389 snd_hdac_i915_exit(bus);
1390
1391 hda->freed = 1;
1392 }
1393
azx_dev_disconnect(struct snd_device * device)1394 static int azx_dev_disconnect(struct snd_device *device)
1395 {
1396 struct azx *chip = device->device_data;
1397 struct hdac_bus *bus = azx_bus(chip);
1398
1399 chip->bus.shutdown = 1;
1400 cancel_work_sync(&bus->unsol_work);
1401
1402 return 0;
1403 }
1404
azx_dev_free(struct snd_device * device)1405 static int azx_dev_free(struct snd_device *device)
1406 {
1407 azx_free(device->device_data);
1408 return 0;
1409 }
1410
1411 #ifdef SUPPORT_VGA_SWITCHEROO
1412 #ifdef CONFIG_ACPI
1413 /* ATPX is in the integrated GPU's namespace */
atpx_present(void)1414 static bool atpx_present(void)
1415 {
1416 struct pci_dev *pdev = NULL;
1417 acpi_handle dhandle, atpx_handle;
1418 acpi_status status;
1419
1420 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1421 dhandle = ACPI_HANDLE(&pdev->dev);
1422 if (dhandle) {
1423 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1424 if (ACPI_SUCCESS(status)) {
1425 pci_dev_put(pdev);
1426 return true;
1427 }
1428 }
1429 }
1430 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
1431 dhandle = ACPI_HANDLE(&pdev->dev);
1432 if (dhandle) {
1433 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1434 if (ACPI_SUCCESS(status)) {
1435 pci_dev_put(pdev);
1436 return true;
1437 }
1438 }
1439 }
1440 return false;
1441 }
1442 #else
atpx_present(void)1443 static bool atpx_present(void)
1444 {
1445 return false;
1446 }
1447 #endif
1448
1449 /*
1450 * Check of disabled HDMI controller by vga_switcheroo
1451 */
get_bound_vga(struct pci_dev * pci)1452 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1453 {
1454 struct pci_dev *p;
1455
1456 /* check only discrete GPU */
1457 switch (pci->vendor) {
1458 case PCI_VENDOR_ID_ATI:
1459 case PCI_VENDOR_ID_AMD:
1460 if (pci->devfn == 1) {
1461 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1462 pci->bus->number, 0);
1463 if (p) {
1464 /* ATPX is in the integrated GPU's ACPI namespace
1465 * rather than the dGPU's namespace. However,
1466 * the dGPU is the one who is involved in
1467 * vgaswitcheroo.
1468 */
1469 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1470 (atpx_present() || apple_gmux_detect(NULL, NULL)))
1471 return p;
1472 pci_dev_put(p);
1473 }
1474 }
1475 break;
1476 case PCI_VENDOR_ID_NVIDIA:
1477 if (pci->devfn == 1) {
1478 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1479 pci->bus->number, 0);
1480 if (p) {
1481 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1482 return p;
1483 pci_dev_put(p);
1484 }
1485 }
1486 break;
1487 }
1488 return NULL;
1489 }
1490
check_hdmi_disabled(struct pci_dev * pci)1491 static bool check_hdmi_disabled(struct pci_dev *pci)
1492 {
1493 bool vga_inactive = false;
1494 struct pci_dev *p = get_bound_vga(pci);
1495
1496 if (p) {
1497 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1498 vga_inactive = true;
1499 pci_dev_put(p);
1500 }
1501 return vga_inactive;
1502 }
1503 #endif /* SUPPORT_VGA_SWITCHEROO */
1504
1505 /*
1506 * allow/deny-listing for position_fix
1507 */
1508 static const struct snd_pci_quirk position_fix_list[] = {
1509 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1510 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1511 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1512 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1513 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1514 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1515 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1516 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1517 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1518 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1519 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1520 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1521 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1522 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1523 {}
1524 };
1525
check_position_fix(struct azx * chip,int fix)1526 static int check_position_fix(struct azx *chip, int fix)
1527 {
1528 const struct snd_pci_quirk *q;
1529
1530 switch (fix) {
1531 case POS_FIX_AUTO:
1532 case POS_FIX_LPIB:
1533 case POS_FIX_POSBUF:
1534 case POS_FIX_VIACOMBO:
1535 case POS_FIX_COMBO:
1536 case POS_FIX_SKL:
1537 case POS_FIX_FIFO:
1538 return fix;
1539 }
1540
1541 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1542 if (q) {
1543 dev_info(chip->card->dev,
1544 "position_fix set to %d for device %04x:%04x\n",
1545 q->value, q->subvendor, q->subdevice);
1546 return q->value;
1547 }
1548
1549 /* Check VIA/ATI HD Audio Controller exist */
1550 if (chip->driver_type == AZX_DRIVER_VIA) {
1551 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1552 return POS_FIX_VIACOMBO;
1553 }
1554 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1555 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1556 return POS_FIX_FIFO;
1557 }
1558 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1559 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1560 return POS_FIX_LPIB;
1561 }
1562 if (chip->driver_type == AZX_DRIVER_SKL) {
1563 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1564 return POS_FIX_SKL;
1565 }
1566 return POS_FIX_AUTO;
1567 }
1568
assign_position_fix(struct azx * chip,int fix)1569 static void assign_position_fix(struct azx *chip, int fix)
1570 {
1571 static const azx_get_pos_callback_t callbacks[] = {
1572 [POS_FIX_AUTO] = NULL,
1573 [POS_FIX_LPIB] = azx_get_pos_lpib,
1574 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1575 [POS_FIX_VIACOMBO] = azx_via_get_position,
1576 [POS_FIX_COMBO] = azx_get_pos_lpib,
1577 [POS_FIX_SKL] = azx_get_pos_posbuf,
1578 [POS_FIX_FIFO] = azx_get_pos_fifo,
1579 };
1580
1581 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1582
1583 /* combo mode uses LPIB only for playback */
1584 if (fix == POS_FIX_COMBO)
1585 chip->get_position[1] = NULL;
1586
1587 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1588 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1589 chip->get_delay[0] = chip->get_delay[1] =
1590 azx_get_delay_from_lpib;
1591 }
1592
1593 if (fix == POS_FIX_FIFO)
1594 chip->get_delay[0] = chip->get_delay[1] =
1595 azx_get_delay_from_fifo;
1596 }
1597
1598 /*
1599 * deny-lists for probe_mask
1600 */
1601 static const struct snd_pci_quirk probe_mask_list[] = {
1602 /* Thinkpad often breaks the controller communication when accessing
1603 * to the non-working (or non-existing) modem codec slot.
1604 */
1605 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1606 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1607 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1608 /* broken BIOS */
1609 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1610 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1611 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1612 /* forced codec slots */
1613 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1614 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1615 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),
1616 /* WinFast VP200 H (Teradici) user reported broken communication */
1617 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1618 {}
1619 };
1620
1621 #define AZX_FORCE_CODEC_MASK 0x100
1622
check_probe_mask(struct azx * chip,int dev)1623 static void check_probe_mask(struct azx *chip, int dev)
1624 {
1625 const struct snd_pci_quirk *q;
1626
1627 chip->codec_probe_mask = probe_mask[dev];
1628 if (chip->codec_probe_mask == -1) {
1629 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1630 if (q) {
1631 dev_info(chip->card->dev,
1632 "probe_mask set to 0x%x for device %04x:%04x\n",
1633 q->value, q->subvendor, q->subdevice);
1634 chip->codec_probe_mask = q->value;
1635 }
1636 }
1637
1638 /* check forced option */
1639 if (chip->codec_probe_mask != -1 &&
1640 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1641 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1642 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1643 (int)azx_bus(chip)->codec_mask);
1644 }
1645 }
1646
1647 /*
1648 * allow/deny-list for enable_msi
1649 */
1650 static const struct snd_pci_quirk msi_deny_list[] = {
1651 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1652 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1653 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1654 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1655 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1656 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1657 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1658 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1659 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1660 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1661 {}
1662 };
1663
check_msi(struct azx * chip)1664 static void check_msi(struct azx *chip)
1665 {
1666 const struct snd_pci_quirk *q;
1667
1668 if (enable_msi >= 0) {
1669 chip->msi = !!enable_msi;
1670 return;
1671 }
1672 chip->msi = 1; /* enable MSI as default */
1673 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
1674 if (q) {
1675 dev_info(chip->card->dev,
1676 "msi for device %04x:%04x set to %d\n",
1677 q->subvendor, q->subdevice, q->value);
1678 chip->msi = q->value;
1679 return;
1680 }
1681
1682 /* NVidia chipsets seem to cause troubles with MSI */
1683 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1684 dev_info(chip->card->dev, "Disabling MSI\n");
1685 chip->msi = 0;
1686 }
1687 }
1688
1689 /* check the snoop mode availability */
azx_check_snoop_available(struct azx * chip)1690 static void azx_check_snoop_available(struct azx *chip)
1691 {
1692 int snoop = hda_snoop;
1693
1694 if (snoop >= 0) {
1695 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1696 snoop ? "snoop" : "non-snoop");
1697 chip->snoop = snoop;
1698 chip->uc_buffer = !snoop;
1699 return;
1700 }
1701
1702 snoop = true;
1703 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1704 chip->driver_type == AZX_DRIVER_VIA) {
1705 /* force to non-snoop mode for a new VIA controller
1706 * when BIOS is set
1707 */
1708 u8 val;
1709 pci_read_config_byte(chip->pci, 0x42, &val);
1710 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1711 chip->pci->revision == 0x20))
1712 snoop = false;
1713 }
1714
1715 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1716 snoop = false;
1717
1718 chip->snoop = snoop;
1719 if (!snoop) {
1720 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1721 /* C-Media requires non-cached pages only for CORB/RIRB */
1722 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1723 chip->uc_buffer = true;
1724 }
1725 }
1726
azx_probe_work(struct work_struct * work)1727 static void azx_probe_work(struct work_struct *work)
1728 {
1729 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
1730 azx_probe_continue(&hda->chip);
1731 }
1732
default_bdl_pos_adj(struct azx * chip)1733 static int default_bdl_pos_adj(struct azx *chip)
1734 {
1735 /* some exceptions: Atoms seem problematic with value 1 */
1736 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1737 switch (chip->pci->device) {
1738 case 0x0f04: /* Baytrail */
1739 case 0x2284: /* Braswell */
1740 return 32;
1741 }
1742 }
1743
1744 switch (chip->driver_type) {
1745 case AZX_DRIVER_ICH:
1746 case AZX_DRIVER_PCH:
1747 return 1;
1748 default:
1749 return 32;
1750 }
1751 }
1752
1753 /*
1754 * constructor
1755 */
1756 static const struct hda_controller_ops pci_hda_ops;
1757
azx_create(struct snd_card * card,struct pci_dev * pci,int dev,unsigned int driver_caps,struct azx ** rchip)1758 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1759 int dev, unsigned int driver_caps,
1760 struct azx **rchip)
1761 {
1762 static const struct snd_device_ops ops = {
1763 .dev_disconnect = azx_dev_disconnect,
1764 .dev_free = azx_dev_free,
1765 };
1766 struct hda_intel *hda;
1767 struct azx *chip;
1768 int err;
1769
1770 *rchip = NULL;
1771
1772 err = pcim_enable_device(pci);
1773 if (err < 0)
1774 return err;
1775
1776 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1777 if (!hda)
1778 return -ENOMEM;
1779
1780 chip = &hda->chip;
1781 mutex_init(&chip->open_mutex);
1782 chip->card = card;
1783 chip->pci = pci;
1784 chip->ops = &pci_hda_ops;
1785 chip->driver_caps = driver_caps;
1786 chip->driver_type = driver_caps & 0xff;
1787 check_msi(chip);
1788 chip->dev_index = dev;
1789 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1790 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1791 INIT_LIST_HEAD(&chip->pcm_list);
1792 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1793 INIT_LIST_HEAD(&hda->list);
1794 init_vga_switcheroo(chip);
1795 init_completion(&hda->probe_wait);
1796
1797 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1798
1799 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1800 chip->fallback_to_single_cmd = 1;
1801 else /* explicitly set to single_cmd or not */
1802 chip->single_cmd = single_cmd;
1803
1804 azx_check_snoop_available(chip);
1805
1806 if (bdl_pos_adj[dev] < 0)
1807 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1808 else
1809 chip->bdl_pos_adj = bdl_pos_adj[dev];
1810
1811 err = azx_bus_init(chip, model[dev]);
1812 if (err < 0)
1813 return err;
1814
1815 /* use the non-cached pages in non-snoop mode */
1816 if (!azx_snoop(chip))
1817 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC_SG;
1818
1819 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1820 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1821 chip->bus.core.needs_damn_long_delay = 1;
1822 }
1823
1824 check_probe_mask(chip, dev);
1825
1826 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1827 if (err < 0) {
1828 dev_err(card->dev, "Error creating device [card]!\n");
1829 azx_free(chip);
1830 return err;
1831 }
1832
1833 /* continue probing in work context as may trigger request module */
1834 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
1835
1836 *rchip = chip;
1837
1838 return 0;
1839 }
1840
azx_first_init(struct azx * chip)1841 static int azx_first_init(struct azx *chip)
1842 {
1843 int dev = chip->dev_index;
1844 struct pci_dev *pci = chip->pci;
1845 struct snd_card *card = chip->card;
1846 struct hdac_bus *bus = azx_bus(chip);
1847 int err;
1848 unsigned short gcap;
1849 unsigned int dma_bits = 64;
1850
1851 #if BITS_PER_LONG != 64
1852 /* Fix up base address on ULI M5461 */
1853 if (chip->driver_type == AZX_DRIVER_ULI) {
1854 u16 tmp3;
1855 pci_read_config_word(pci, 0x40, &tmp3);
1856 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1857 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1858 }
1859 #endif
1860
1861 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio");
1862 if (err < 0)
1863 return err;
1864
1865 bus->addr = pci_resource_start(pci, 0);
1866 bus->remap_addr = pcim_iomap_table(pci)[0];
1867
1868 if (chip->driver_type == AZX_DRIVER_SKL)
1869 snd_hdac_bus_parse_capabilities(bus);
1870
1871 /*
1872 * Some Intel CPUs has always running timer (ART) feature and
1873 * controller may have Global time sync reporting capability, so
1874 * check both of these before declaring synchronized time reporting
1875 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1876 */
1877 chip->gts_present = false;
1878
1879 #ifdef CONFIG_X86
1880 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1881 chip->gts_present = true;
1882 #endif
1883
1884 if (chip->msi) {
1885 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1886 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1887 pci->no_64bit_msi = true;
1888 }
1889 if (pci_enable_msi(pci) < 0)
1890 chip->msi = 0;
1891 }
1892
1893 pci_set_master(pci);
1894
1895 gcap = azx_readw(chip, GCAP);
1896 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1897
1898 /* AMD devices support 40 or 48bit DMA, take the safe one */
1899 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1900 dma_bits = 40;
1901
1902 /* disable SB600 64bit support for safety */
1903 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1904 struct pci_dev *p_smbus;
1905 dma_bits = 40;
1906 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1907 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1908 NULL);
1909 if (p_smbus) {
1910 if (p_smbus->revision < 0x30)
1911 gcap &= ~AZX_GCAP_64OK;
1912 pci_dev_put(p_smbus);
1913 }
1914 }
1915
1916 /* NVidia hardware normally only supports up to 40 bits of DMA */
1917 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1918 dma_bits = 40;
1919
1920 /* disable 64bit DMA address on some devices */
1921 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1922 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1923 gcap &= ~AZX_GCAP_64OK;
1924 }
1925
1926 /* disable buffer size rounding to 128-byte multiples if supported */
1927 if (align_buffer_size >= 0)
1928 chip->align_buffer_size = !!align_buffer_size;
1929 else {
1930 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1931 chip->align_buffer_size = 0;
1932 else
1933 chip->align_buffer_size = 1;
1934 }
1935
1936 /* allow 64bit DMA address if supported by H/W */
1937 if (!(gcap & AZX_GCAP_64OK))
1938 dma_bits = 32;
1939 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1940 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
1941 dma_set_max_seg_size(&pci->dev, UINT_MAX);
1942
1943 /* read number of streams from GCAP register instead of using
1944 * hardcoded value
1945 */
1946 chip->capture_streams = (gcap >> 8) & 0x0f;
1947 chip->playback_streams = (gcap >> 12) & 0x0f;
1948 if (!chip->playback_streams && !chip->capture_streams) {
1949 /* gcap didn't give any info, switching to old method */
1950
1951 switch (chip->driver_type) {
1952 case AZX_DRIVER_ULI:
1953 chip->playback_streams = ULI_NUM_PLAYBACK;
1954 chip->capture_streams = ULI_NUM_CAPTURE;
1955 break;
1956 case AZX_DRIVER_ATIHDMI:
1957 case AZX_DRIVER_ATIHDMI_NS:
1958 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1959 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1960 break;
1961 case AZX_DRIVER_GENERIC:
1962 default:
1963 chip->playback_streams = ICH6_NUM_PLAYBACK;
1964 chip->capture_streams = ICH6_NUM_CAPTURE;
1965 break;
1966 }
1967 }
1968 chip->capture_index_offset = 0;
1969 chip->playback_index_offset = chip->capture_streams;
1970 chip->num_streams = chip->playback_streams + chip->capture_streams;
1971
1972 /* sanity check for the SDxCTL.STRM field overflow */
1973 if (chip->num_streams > 15 &&
1974 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1975 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1976 "forcing separate stream tags", chip->num_streams);
1977 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1978 }
1979
1980 /* initialize streams */
1981 err = azx_init_streams(chip);
1982 if (err < 0)
1983 return err;
1984
1985 err = azx_alloc_stream_pages(chip);
1986 if (err < 0)
1987 return err;
1988
1989 /* initialize chip */
1990 azx_init_pci(chip);
1991
1992 snd_hdac_i915_set_bclk(bus);
1993
1994 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1995
1996 /* codec detection */
1997 if (!azx_bus(chip)->codec_mask) {
1998 dev_err(card->dev, "no codecs found!\n");
1999 /* keep running the rest for the runtime PM */
2000 }
2001
2002 if (azx_acquire_irq(chip, 0) < 0)
2003 return -EBUSY;
2004
2005 strcpy(card->driver, "HDA-Intel");
2006 strscpy(card->shortname, driver_short_names[chip->driver_type],
2007 sizeof(card->shortname));
2008 snprintf(card->longname, sizeof(card->longname),
2009 "%s at 0x%lx irq %i",
2010 card->shortname, bus->addr, bus->irq);
2011
2012 return 0;
2013 }
2014
2015 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2016 /* callback from request_firmware_nowait() */
azx_firmware_cb(const struct firmware * fw,void * context)2017 static void azx_firmware_cb(const struct firmware *fw, void *context)
2018 {
2019 struct snd_card *card = context;
2020 struct azx *chip = card->private_data;
2021
2022 if (fw)
2023 chip->fw = fw;
2024 else
2025 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2026 if (!chip->disabled) {
2027 /* continue probing */
2028 azx_probe_continue(chip);
2029 }
2030 }
2031 #endif
2032
disable_msi_reset_irq(struct azx * chip)2033 static int disable_msi_reset_irq(struct azx *chip)
2034 {
2035 struct hdac_bus *bus = azx_bus(chip);
2036 int err;
2037
2038 free_irq(bus->irq, chip);
2039 bus->irq = -1;
2040 chip->card->sync_irq = -1;
2041 pci_disable_msi(chip->pci);
2042 chip->msi = 0;
2043 err = azx_acquire_irq(chip, 1);
2044 if (err < 0)
2045 return err;
2046
2047 return 0;
2048 }
2049
2050 /* Denylist for skipping the whole probe:
2051 * some HD-audio PCI entries are exposed without any codecs, and such devices
2052 * should be ignored from the beginning.
2053 */
2054 static const struct pci_device_id driver_denylist[] = {
2055 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2056 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2057 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2058 {}
2059 };
2060
2061 static const struct hda_controller_ops pci_hda_ops = {
2062 .disable_msi_reset_irq = disable_msi_reset_irq,
2063 .position_check = azx_position_check,
2064 };
2065
2066 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS);
2067
azx_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)2068 static int azx_probe(struct pci_dev *pci,
2069 const struct pci_device_id *pci_id)
2070 {
2071 struct snd_card *card;
2072 struct hda_intel *hda;
2073 struct azx *chip;
2074 bool schedule_probe;
2075 int dev;
2076 int err;
2077
2078 if (pci_match_id(driver_denylist, pci)) {
2079 dev_info(&pci->dev, "Skipping the device on the denylist\n");
2080 return -ENODEV;
2081 }
2082
2083 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS);
2084 if (dev >= SNDRV_CARDS)
2085 return -ENODEV;
2086 if (!enable[dev]) {
2087 set_bit(dev, probed_devs);
2088 return -ENOENT;
2089 }
2090
2091 /*
2092 * stop probe if another Intel's DSP driver should be activated
2093 */
2094 if (dmic_detect) {
2095 err = snd_intel_dsp_driver_probe(pci);
2096 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2097 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
2098 return -ENODEV;
2099 }
2100 } else {
2101 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2102 }
2103
2104 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2105 0, &card);
2106 if (err < 0) {
2107 dev_err(&pci->dev, "Error creating card!\n");
2108 return err;
2109 }
2110
2111 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2112 if (err < 0)
2113 goto out_free;
2114 card->private_data = chip;
2115 hda = container_of(chip, struct hda_intel, chip);
2116
2117 pci_set_drvdata(pci, card);
2118
2119 err = register_vga_switcheroo(chip);
2120 if (err < 0) {
2121 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2122 goto out_free;
2123 }
2124
2125 if (check_hdmi_disabled(pci)) {
2126 dev_info(card->dev, "VGA controller is disabled\n");
2127 dev_info(card->dev, "Delaying initialization\n");
2128 chip->disabled = true;
2129 }
2130
2131 schedule_probe = !chip->disabled;
2132
2133 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2134 if (patch[dev] && *patch[dev]) {
2135 dev_info(card->dev, "Applying patch firmware '%s'\n",
2136 patch[dev]);
2137 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2138 &pci->dev, GFP_KERNEL, card,
2139 azx_firmware_cb);
2140 if (err < 0)
2141 goto out_free;
2142 schedule_probe = false; /* continued in azx_firmware_cb() */
2143 }
2144 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2145
2146 #ifndef CONFIG_SND_HDA_I915
2147 if (CONTROLLER_IN_GPU(pci))
2148 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2149 #endif
2150
2151 if (schedule_probe)
2152 schedule_delayed_work(&hda->probe_work, 0);
2153
2154 set_bit(dev, probed_devs);
2155 if (chip->disabled)
2156 complete_all(&hda->probe_wait);
2157 return 0;
2158
2159 out_free:
2160 snd_card_free(card);
2161 return err;
2162 }
2163
2164 #ifdef CONFIG_PM
2165 /* On some boards setting power_save to a non 0 value leads to clicking /
2166 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2167 * figure out how to avoid these sounds, but that is not always feasible.
2168 * So we keep a list of devices where we disable powersaving as its known
2169 * to causes problems on these devices.
2170 */
2171 static const struct snd_pci_quirk power_save_denylist[] = {
2172 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2173 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2174 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2175 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2176 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2177 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2178 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2179 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2180 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2181 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2182 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2183 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2184 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2185 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2186 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2187 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2188 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2189 /* https://bugs.launchpad.net/bugs/1821663 */
2190 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2191 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2192 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2193 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2194 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2195 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2196 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2197 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2198 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2199 /* https://bugs.launchpad.net/bugs/1821663 */
2200 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2201 {}
2202 };
2203 #endif /* CONFIG_PM */
2204
set_default_power_save(struct azx * chip)2205 static void set_default_power_save(struct azx *chip)
2206 {
2207 int val = power_save;
2208
2209 #ifdef CONFIG_PM
2210 if (pm_blacklist) {
2211 const struct snd_pci_quirk *q;
2212
2213 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
2214 if (q && val) {
2215 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
2216 q->subvendor, q->subdevice);
2217 val = 0;
2218 }
2219 }
2220 #endif /* CONFIG_PM */
2221 snd_hda_set_power_save(&chip->bus, val * 1000);
2222 }
2223
2224 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2225 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2226 [AZX_DRIVER_NVIDIA] = 8,
2227 [AZX_DRIVER_TERA] = 1,
2228 };
2229
azx_probe_continue(struct azx * chip)2230 static int azx_probe_continue(struct azx *chip)
2231 {
2232 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2233 struct hdac_bus *bus = azx_bus(chip);
2234 struct pci_dev *pci = chip->pci;
2235 int dev = chip->dev_index;
2236 int err;
2237
2238 if (chip->disabled || hda->init_failed)
2239 return -EIO;
2240 if (hda->probe_retry)
2241 goto probe_retry;
2242
2243 to_hda_bus(bus)->bus_probing = 1;
2244 hda->probe_continued = 1;
2245
2246 /* bind with i915 if needed */
2247 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2248 err = snd_hdac_i915_init(bus);
2249 if (err < 0) {
2250 /* if the controller is bound only with HDMI/DP
2251 * (for HSW and BDW), we need to abort the probe;
2252 * for other chips, still continue probing as other
2253 * codecs can be on the same link.
2254 */
2255 if (CONTROLLER_IN_GPU(pci)) {
2256 dev_err(chip->card->dev,
2257 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2258 goto out_free;
2259 } else {
2260 /* don't bother any longer */
2261 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2262 }
2263 }
2264
2265 /* HSW/BDW controllers need this power */
2266 if (CONTROLLER_IN_GPU(pci))
2267 hda->need_i915_power = true;
2268 }
2269
2270 /* Request display power well for the HDA controller or codec. For
2271 * Haswell/Broadwell, both the display HDA controller and codec need
2272 * this power. For other platforms, like Baytrail/Braswell, only the
2273 * display codec needs the power and it can be released after probe.
2274 */
2275 display_power(chip, true);
2276
2277 err = azx_first_init(chip);
2278 if (err < 0)
2279 goto out_free;
2280
2281 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2282 chip->beep_mode = beep_mode[dev];
2283 #endif
2284
2285 chip->ctl_dev_id = ctl_dev_id;
2286
2287 /* create codec instances */
2288 if (bus->codec_mask) {
2289 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2290 if (err < 0)
2291 goto out_free;
2292 }
2293
2294 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2295 if (chip->fw) {
2296 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2297 chip->fw->data);
2298 if (err < 0)
2299 goto out_free;
2300 #ifndef CONFIG_PM
2301 release_firmware(chip->fw); /* no longer needed */
2302 chip->fw = NULL;
2303 #endif
2304 }
2305 #endif
2306
2307 probe_retry:
2308 if (bus->codec_mask && !(probe_only[dev] & 1)) {
2309 err = azx_codec_configure(chip);
2310 if (err) {
2311 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
2312 ++hda->probe_retry < 60) {
2313 schedule_delayed_work(&hda->probe_work,
2314 msecs_to_jiffies(1000));
2315 return 0; /* keep things up */
2316 }
2317 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
2318 goto out_free;
2319 }
2320 }
2321
2322 err = snd_card_register(chip->card);
2323 if (err < 0)
2324 goto out_free;
2325
2326 setup_vga_switcheroo_runtime_pm(chip);
2327
2328 chip->running = 1;
2329 azx_add_card_list(chip);
2330
2331 set_default_power_save(chip);
2332
2333 if (azx_has_pm_runtime(chip)) {
2334 pm_runtime_use_autosuspend(&pci->dev);
2335 pm_runtime_allow(&pci->dev);
2336 pm_runtime_put_autosuspend(&pci->dev);
2337 }
2338
2339 out_free:
2340 if (err < 0) {
2341 pci_set_drvdata(pci, NULL);
2342 snd_card_free(chip->card);
2343 return err;
2344 }
2345
2346 if (!hda->need_i915_power)
2347 display_power(chip, false);
2348 complete_all(&hda->probe_wait);
2349 to_hda_bus(bus)->bus_probing = 0;
2350 hda->probe_retry = 0;
2351 return 0;
2352 }
2353
azx_remove(struct pci_dev * pci)2354 static void azx_remove(struct pci_dev *pci)
2355 {
2356 struct snd_card *card = pci_get_drvdata(pci);
2357 struct azx *chip;
2358 struct hda_intel *hda;
2359
2360 if (card) {
2361 /* cancel the pending probing work */
2362 chip = card->private_data;
2363 hda = container_of(chip, struct hda_intel, chip);
2364 /* FIXME: below is an ugly workaround.
2365 * Both device_release_driver() and driver_probe_device()
2366 * take *both* the device's and its parent's lock before
2367 * calling the remove() and probe() callbacks. The codec
2368 * probe takes the locks of both the codec itself and its
2369 * parent, i.e. the PCI controller dev. Meanwhile, when
2370 * the PCI controller is unbound, it takes its lock, too
2371 * ==> ouch, a deadlock!
2372 * As a workaround, we unlock temporarily here the controller
2373 * device during cancel_work_sync() call.
2374 */
2375 device_unlock(&pci->dev);
2376 cancel_delayed_work_sync(&hda->probe_work);
2377 device_lock(&pci->dev);
2378
2379 clear_bit(chip->dev_index, probed_devs);
2380 pci_set_drvdata(pci, NULL);
2381 snd_card_free(card);
2382 }
2383 }
2384
azx_shutdown(struct pci_dev * pci)2385 static void azx_shutdown(struct pci_dev *pci)
2386 {
2387 struct snd_card *card = pci_get_drvdata(pci);
2388 struct azx *chip;
2389
2390 if (!card)
2391 return;
2392 chip = card->private_data;
2393 if (chip && chip->running)
2394 __azx_shutdown_chip(chip, true);
2395 }
2396
2397 /* PCI IDs */
2398 static const struct pci_device_id azx_ids[] = {
2399 /* CPT */
2400 { PCI_DEVICE(0x8086, 0x1c20),
2401 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2402 /* PBG */
2403 { PCI_DEVICE(0x8086, 0x1d20),
2404 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2405 /* Panther Point */
2406 { PCI_DEVICE(0x8086, 0x1e20),
2407 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2408 /* Lynx Point */
2409 { PCI_DEVICE(0x8086, 0x8c20),
2410 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2411 /* 9 Series */
2412 { PCI_DEVICE(0x8086, 0x8ca0),
2413 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2414 /* Wellsburg */
2415 { PCI_DEVICE(0x8086, 0x8d20),
2416 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2417 { PCI_DEVICE(0x8086, 0x8d21),
2418 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2419 /* Lewisburg */
2420 { PCI_DEVICE(0x8086, 0xa1f0),
2421 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2422 { PCI_DEVICE(0x8086, 0xa270),
2423 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2424 /* Lynx Point-LP */
2425 { PCI_DEVICE(0x8086, 0x9c20),
2426 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2427 /* Lynx Point-LP */
2428 { PCI_DEVICE(0x8086, 0x9c21),
2429 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2430 /* Wildcat Point-LP */
2431 { PCI_DEVICE(0x8086, 0x9ca0),
2432 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2433 /* Sunrise Point */
2434 { PCI_DEVICE(0x8086, 0xa170),
2435 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2436 /* Sunrise Point-LP */
2437 { PCI_DEVICE(0x8086, 0x9d70),
2438 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2439 /* Kabylake */
2440 { PCI_DEVICE(0x8086, 0xa171),
2441 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2442 /* Kabylake-LP */
2443 { PCI_DEVICE(0x8086, 0x9d71),
2444 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2445 /* Kabylake-H */
2446 { PCI_DEVICE(0x8086, 0xa2f0),
2447 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2448 /* Coffelake */
2449 { PCI_DEVICE(0x8086, 0xa348),
2450 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2451 /* Cannonlake */
2452 { PCI_DEVICE(0x8086, 0x9dc8),
2453 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2454 /* CometLake-LP */
2455 { PCI_DEVICE(0x8086, 0x02C8),
2456 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2457 /* CometLake-H */
2458 { PCI_DEVICE(0x8086, 0x06C8),
2459 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2460 { PCI_DEVICE(0x8086, 0xf1c8),
2461 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2462 /* CometLake-S */
2463 { PCI_DEVICE(0x8086, 0xa3f0),
2464 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2465 /* CometLake-R */
2466 { PCI_DEVICE(0x8086, 0xf0c8),
2467 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2468 /* Icelake */
2469 { PCI_DEVICE(0x8086, 0x34c8),
2470 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2471 /* Icelake-H */
2472 { PCI_DEVICE(0x8086, 0x3dc8),
2473 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2474 /* Jasperlake */
2475 { PCI_DEVICE(0x8086, 0x38c8),
2476 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2477 { PCI_DEVICE(0x8086, 0x4dc8),
2478 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2479 /* Tigerlake */
2480 { PCI_DEVICE(0x8086, 0xa0c8),
2481 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2482 /* Tigerlake-H */
2483 { PCI_DEVICE(0x8086, 0x43c8),
2484 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2485 /* DG1 */
2486 { PCI_DEVICE(0x8086, 0x490d),
2487 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2488 /* DG2 */
2489 { PCI_DEVICE(0x8086, 0x4f90),
2490 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2491 { PCI_DEVICE(0x8086, 0x4f91),
2492 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2493 { PCI_DEVICE(0x8086, 0x4f92),
2494 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2495 /* Alderlake-S */
2496 { PCI_DEVICE(0x8086, 0x7ad0),
2497 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2498 /* Alderlake-P */
2499 { PCI_DEVICE(0x8086, 0x51c8),
2500 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2501 { PCI_DEVICE(0x8086, 0x51c9),
2502 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2503 { PCI_DEVICE(0x8086, 0x51cd),
2504 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2505 /* Alderlake-M */
2506 { PCI_DEVICE(0x8086, 0x51cc),
2507 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2508 /* Alderlake-N */
2509 { PCI_DEVICE(0x8086, 0x54c8),
2510 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2511 /* Elkhart Lake */
2512 { PCI_DEVICE(0x8086, 0x4b55),
2513 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2514 { PCI_DEVICE(0x8086, 0x4b58),
2515 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2516 /* Raptor Lake */
2517 { PCI_DEVICE(0x8086, 0x7a50),
2518 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2519 { PCI_DEVICE(0x8086, 0x51ca),
2520 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2521 { PCI_DEVICE(0x8086, 0x51cb),
2522 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2523 { PCI_DEVICE(0x8086, 0x51ce),
2524 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2525 { PCI_DEVICE(0x8086, 0x51cf),
2526 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2527 /* Meteorlake-P */
2528 { PCI_DEVICE(0x8086, 0x7e28),
2529 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2530 /* Broxton-P(Apollolake) */
2531 { PCI_DEVICE(0x8086, 0x5a98),
2532 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2533 /* Broxton-T */
2534 { PCI_DEVICE(0x8086, 0x1a98),
2535 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2536 /* Gemini-Lake */
2537 { PCI_DEVICE(0x8086, 0x3198),
2538 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2539 /* Haswell */
2540 { PCI_DEVICE(0x8086, 0x0a0c),
2541 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2542 { PCI_DEVICE(0x8086, 0x0c0c),
2543 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2544 { PCI_DEVICE(0x8086, 0x0d0c),
2545 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2546 /* Broadwell */
2547 { PCI_DEVICE(0x8086, 0x160c),
2548 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2549 /* 5 Series/3400 */
2550 { PCI_DEVICE(0x8086, 0x3b56),
2551 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2552 { PCI_DEVICE(0x8086, 0x3b57),
2553 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2554 /* Poulsbo */
2555 { PCI_DEVICE(0x8086, 0x811b),
2556 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE |
2557 AZX_DCAPS_POSFIX_LPIB },
2558 /* Oaktrail */
2559 { PCI_DEVICE(0x8086, 0x080a),
2560 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2561 /* BayTrail */
2562 { PCI_DEVICE(0x8086, 0x0f04),
2563 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2564 /* Braswell */
2565 { PCI_DEVICE(0x8086, 0x2284),
2566 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2567 /* ICH6 */
2568 { PCI_DEVICE(0x8086, 0x2668),
2569 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2570 /* ICH7 */
2571 { PCI_DEVICE(0x8086, 0x27d8),
2572 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2573 /* ESB2 */
2574 { PCI_DEVICE(0x8086, 0x269a),
2575 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2576 /* ICH8 */
2577 { PCI_DEVICE(0x8086, 0x284b),
2578 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2579 /* ICH9 */
2580 { PCI_DEVICE(0x8086, 0x293e),
2581 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2582 /* ICH9 */
2583 { PCI_DEVICE(0x8086, 0x293f),
2584 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2585 /* ICH10 */
2586 { PCI_DEVICE(0x8086, 0x3a3e),
2587 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2588 /* ICH10 */
2589 { PCI_DEVICE(0x8086, 0x3a6e),
2590 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2591 /* Generic Intel */
2592 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2593 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2594 .class_mask = 0xffffff,
2595 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2596 /* ATI SB 450/600/700/800/900 */
2597 { PCI_DEVICE(0x1002, 0x437b),
2598 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2599 { PCI_DEVICE(0x1002, 0x4383),
2600 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2601 /* AMD Hudson */
2602 { PCI_DEVICE(0x1022, 0x780d),
2603 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2604 /* AMD, X370 & co */
2605 { PCI_DEVICE(0x1022, 0x1457),
2606 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2607 /* AMD, X570 & co */
2608 { PCI_DEVICE(0x1022, 0x1487),
2609 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2610 /* AMD Stoney */
2611 { PCI_DEVICE(0x1022, 0x157a),
2612 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2613 AZX_DCAPS_PM_RUNTIME },
2614 /* AMD Raven */
2615 { PCI_DEVICE(0x1022, 0x15e3),
2616 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2617 /* ATI HDMI */
2618 { PCI_DEVICE(0x1002, 0x0002),
2619 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2620 AZX_DCAPS_PM_RUNTIME },
2621 { PCI_DEVICE(0x1002, 0x1308),
2622 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2623 { PCI_DEVICE(0x1002, 0x157a),
2624 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2625 { PCI_DEVICE(0x1002, 0x15b3),
2626 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2627 { PCI_DEVICE(0x1002, 0x793b),
2628 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2629 { PCI_DEVICE(0x1002, 0x7919),
2630 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2631 { PCI_DEVICE(0x1002, 0x960f),
2632 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2633 { PCI_DEVICE(0x1002, 0x970f),
2634 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2635 { PCI_DEVICE(0x1002, 0x9840),
2636 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2637 { PCI_DEVICE(0x1002, 0xaa00),
2638 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2639 { PCI_DEVICE(0x1002, 0xaa08),
2640 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2641 { PCI_DEVICE(0x1002, 0xaa10),
2642 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2643 { PCI_DEVICE(0x1002, 0xaa18),
2644 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2645 { PCI_DEVICE(0x1002, 0xaa20),
2646 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2647 { PCI_DEVICE(0x1002, 0xaa28),
2648 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2649 { PCI_DEVICE(0x1002, 0xaa30),
2650 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2651 { PCI_DEVICE(0x1002, 0xaa38),
2652 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2653 { PCI_DEVICE(0x1002, 0xaa40),
2654 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2655 { PCI_DEVICE(0x1002, 0xaa48),
2656 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2657 { PCI_DEVICE(0x1002, 0xaa50),
2658 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2659 { PCI_DEVICE(0x1002, 0xaa58),
2660 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2661 { PCI_DEVICE(0x1002, 0xaa60),
2662 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2663 { PCI_DEVICE(0x1002, 0xaa68),
2664 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2665 { PCI_DEVICE(0x1002, 0xaa80),
2666 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2667 { PCI_DEVICE(0x1002, 0xaa88),
2668 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2669 { PCI_DEVICE(0x1002, 0xaa90),
2670 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2671 { PCI_DEVICE(0x1002, 0xaa98),
2672 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2673 { PCI_DEVICE(0x1002, 0x9902),
2674 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2675 { PCI_DEVICE(0x1002, 0xaaa0),
2676 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2677 { PCI_DEVICE(0x1002, 0xaaa8),
2678 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2679 { PCI_DEVICE(0x1002, 0xaab0),
2680 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2681 { PCI_DEVICE(0x1002, 0xaac0),
2682 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2683 AZX_DCAPS_PM_RUNTIME },
2684 { PCI_DEVICE(0x1002, 0xaac8),
2685 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2686 AZX_DCAPS_PM_RUNTIME },
2687 { PCI_DEVICE(0x1002, 0xaad8),
2688 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2689 AZX_DCAPS_PM_RUNTIME },
2690 { PCI_DEVICE(0x1002, 0xaae0),
2691 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2692 AZX_DCAPS_PM_RUNTIME },
2693 { PCI_DEVICE(0x1002, 0xaae8),
2694 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2695 AZX_DCAPS_PM_RUNTIME },
2696 { PCI_DEVICE(0x1002, 0xaaf0),
2697 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2698 AZX_DCAPS_PM_RUNTIME },
2699 { PCI_DEVICE(0x1002, 0xaaf8),
2700 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2701 AZX_DCAPS_PM_RUNTIME },
2702 { PCI_DEVICE(0x1002, 0xab00),
2703 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2704 AZX_DCAPS_PM_RUNTIME },
2705 { PCI_DEVICE(0x1002, 0xab08),
2706 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2707 AZX_DCAPS_PM_RUNTIME },
2708 { PCI_DEVICE(0x1002, 0xab10),
2709 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2710 AZX_DCAPS_PM_RUNTIME },
2711 { PCI_DEVICE(0x1002, 0xab18),
2712 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2713 AZX_DCAPS_PM_RUNTIME },
2714 { PCI_DEVICE(0x1002, 0xab20),
2715 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2716 AZX_DCAPS_PM_RUNTIME },
2717 { PCI_DEVICE(0x1002, 0xab28),
2718 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2719 AZX_DCAPS_PM_RUNTIME },
2720 { PCI_DEVICE(0x1002, 0xab30),
2721 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2722 AZX_DCAPS_PM_RUNTIME },
2723 { PCI_DEVICE(0x1002, 0xab38),
2724 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2725 AZX_DCAPS_PM_RUNTIME },
2726 /* VIA VT8251/VT8237A */
2727 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2728 /* VIA GFX VT7122/VX900 */
2729 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2730 /* VIA GFX VT6122/VX11 */
2731 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2732 /* SIS966 */
2733 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2734 /* ULI M5461 */
2735 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2736 /* NVIDIA MCP */
2737 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2738 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2739 .class_mask = 0xffffff,
2740 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2741 /* Teradici */
2742 { PCI_DEVICE(0x6549, 0x1200),
2743 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2744 { PCI_DEVICE(0x6549, 0x2200),
2745 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2746 /* Creative X-Fi (CA0110-IBG) */
2747 /* CTHDA chips */
2748 { PCI_DEVICE(0x1102, 0x0010),
2749 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2750 { PCI_DEVICE(0x1102, 0x0012),
2751 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2752 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2753 /* the following entry conflicts with snd-ctxfi driver,
2754 * as ctxfi driver mutates from HD-audio to native mode with
2755 * a special command sequence.
2756 */
2757 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2758 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2759 .class_mask = 0xffffff,
2760 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2761 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2762 #else
2763 /* this entry seems still valid -- i.e. without emu20kx chip */
2764 { PCI_DEVICE(0x1102, 0x0009),
2765 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2766 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2767 #endif
2768 /* CM8888 */
2769 { PCI_DEVICE(0x13f6, 0x5011),
2770 .driver_data = AZX_DRIVER_CMEDIA |
2771 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2772 /* Vortex86MX */
2773 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2774 /* VMware HDAudio */
2775 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2776 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2777 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2778 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2779 .class_mask = 0xffffff,
2780 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2781 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2782 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2783 .class_mask = 0xffffff,
2784 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2785 /* Zhaoxin */
2786 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2787 { 0, }
2788 };
2789 MODULE_DEVICE_TABLE(pci, azx_ids);
2790
2791 /* pci_driver definition */
2792 static struct pci_driver azx_driver = {
2793 .name = KBUILD_MODNAME,
2794 .id_table = azx_ids,
2795 .probe = azx_probe,
2796 .remove = azx_remove,
2797 .shutdown = azx_shutdown,
2798 .driver = {
2799 .pm = AZX_PM_OPS,
2800 },
2801 };
2802
2803 module_pci_driver(azx_driver);
2804